Increasing bondability and bonding strength of gold stud bumps onto copper pads with a deposited titanium barrier layer

A flip-chip assembly is an attractive scheme for use in high performance and miniaturized microelectronics packaging. Wafer bumping is essential before chips can be flip-bonded to a substrate. Wafer bumping can be used for mechanical-single point stud bump bonding (SBB), and is based on conventional thermosonic wire bonding. This work proposes depositing a titanium barrier layer between the copper film and the silver bonding layer to achieve perfect bondability and sufficiently strong thermosonic bonding between a stud bump and the copper pad.A titanium layer was deposited on the copper pads to prevent copper atoms from out-diffusing during thermosonic stud bump bonding. A silver film was then deposited on the surface of the titanium film as a bonding layer to increase the bondability and bonding strength for stud bumps onto copper pads. The integration of the silver bonding layer with a diffusion barrier layer of titanium on the copper pads yielded 100% bondability between the stud bump and pads. The strength of bonding between the gold bumps on the copper pads significantly exceeds the minimum average values in JEDEC specifications. The diffusion barrier layer of titanium effectively prevents copper atoms from out-diffusing to the silver bonding layer surface during thermosonic bonding, which fact can be interpreted with reference to the experimental results of energy dispersive spectrometry (EDS) and analyses of Auger depth profiles. This diffusion barrier layer of titanium efficiently provides perfect bondability and sufficiently strong bonding between a stud bump and copper pads with a silver bonding layer.     

The use of Mahalanobis-Taguchi System to improve flip-chip bumping height inspection efficiency

With the electronics industry advancing rapidly toward faster, smaller, lighter, and cheaper products, flip-chip packaging has been extensively used in microelectronics. The interconnection of the flip-chip offers several advantages over the widely used wire bonding technique. To obtain a reliable interconnection of the flip-chip, it is important to maintain adequate height of bumps that are plated on the chips. The bump height inspection process is time-consuming in practice and often becomes a constraint during production. The present study aims at solving the bump height inspection efficiency problem. Mahalanobis-Taguchi System (MTS) method is used to reduce the number of bump height measurement points whilst maintaining a high-accuracy inspection level. The results indicate that the numbers of bump height inspection features are significantly reduced from 10 to 6 without losing classification accuracy; and inspection time can be reduced by 40%. By reduction of inspection features, the operation time of the bump height inspection process is reduced. Moreover, the inspection staff can select the inspection position in sequence, according to the significance of features selected by the MTS method. Moreover, they can reduce the number of inspection positions to achieve an acceptable height of bumps.     

A study in flip-chip UBM/bump reliability with effects of SnPb solder composition

This paper aims to investigate the electromigration phenomenon of under-bump-metallization (UBM) and solder bumps of a flip-chip package under high temperature operation life test (HTOL). UBM is a thin film Al/Ni(V)/Cu metal stack of 1.5 μm; while bump material consists of Sn/37Pb, Sn/90Pb, and Sn/95Pb solder. Current densities of 2500 and 5000 A/cm² and ambient temperatures of 150–160 °C are applied to study their impact on electromigration. It is observed that bump temperature has more significant influence than current density does to bump failures. Owing to its higher melting point characteristics and less content of Sn phase, Sn/95Pb solder bumps are observed to have 13-fold improvement in Mean-Time-To-Failure (MTTF) than that of eutectic Sn/37Pb. Individual bump resistance history is calculated to evaluate UBM/bump degradation. The measured resistance increase is from bumps with electrical current flowing upward into UBM/bump interface (cathode), while bumps having opposite current polarity cause only minor resistance change. The identified failure sites and modes from aforementioned high resistance bumps reveal structural damages at the region of UBM and UBM/bump interface in forms of solder cracking or delamination. Effects of current polarity and crowding are key factors to observed electromigration behavior of flip-chip packages.     

A reliable and environmentally friendly packagingtechnology-flip-chip joining using anisotropically conductive adhesive

There is an increasing demand to move the radio base station closer to the antenna for future mobile telecommunication systems. This requires a significant reduction in weight and volume and increased environmental compatibility. This work provides an evaluation of environmental impact and reliability when using anisotropically conductive adhesives (ACA) for flip-chip joining in radio base station applications. Conventional FR-4 substrate has been used to assemble a digital ASIC chip using an anisotropically conductive adhesive and flip-chip technology. The chip has a minimum pitch of 128 μm with 7.8 mm in chip 8 and has in total 144 bumps with a bump size of 114×126 μm². Bumping was made using electroless nickel/gold technology. Bonding quality has been characterized by optical and scanning electron microscopy and substrate planarity measurement. The main parameters affecting quality are misalignment and softening of the FR-4 substrate during assembly, leading to high joint resistance. Reliability testing was conducted in the form of a temperature cycling test between -40 and ±125°C for 1000 cycles, a 125°C aging test for 100 h and a 85/85 humidity test for 500 h. The results show that relatively small resistance changes were observed after the reliability test. The environmental impact evaluation was done in the form of a material content declaration and a life cycle assessment (LCA). By using flip-chip ACA joining technology, the content of environmentally risky materials has been reduced more than ten times, and the use of precious metals has been reduced more than 30 times compared to conventional surface mount technology     

Experimental study of filling behaviors in the underfill encapsulation of a flip-chip

An underfill encapsulant was used to fill the gap between the chip and the substrate around the solder joints to improve the long-term reliability of the flip-chip interconnecting system. The underfill encapsulant was filled by the capillary effect. In this study, experiments were designed to investigate the effects of bump pitch and the edge detour flow on the underfill encapsulation. The bump array was patterned on a glass plate using the lithography technology. This patterned glass plate was used to simulate a flip-chip with solder bumps. The patterned glass was bounded to a substrate to form a simulated flip-chip system. With the lithography technology, it is easy to construct the test samples for underfill flow experiments with different configuration of solder bumps. It was observed that the filling flow was affected by the bump pitch. The edge detour flow depends mainly on the arrangement of the underfill dispensing process.     

混成式焦平面阵列芯片倒装互连技术研究

介绍了为保证倒装焊接性能,设备所采取的措施。对比了不同形貌铟柱的优缺点,分析了互连可靠性与铟柱高度的关系,介绍了考核互连可靠性的方法。通过互连技术研究,我们实现了较高性能的倒装互连,互连条件选择温度在60℃-140℃范围,压力范围0．1克／铟柱-0．5克／铟柱。互连连通率〉99．9％,互连后的芯片组件在低温（77K）与常温（23℃）间不少于100次的反复冲击的情况下,测试接触性能及InSb二极管性能都无变化,满足了互连器件可靠性要求。     

Microstructure characterization of Sn-Ag solder joints between stud bumps and metal pads

The microstructure of the flip-chip solder joints fabricated using stud bumps and Pb-free solder was characterized. The Au or Cu stud bumps formed on Al pads on Si die were aligned to corresponding metal pads in the substrate, which was printed with Sn-3.5Ag paste. Joints were fabricated by reflowing the solder paste. In the solder joints fabricated using Au stud bumps, Au-Sn intermetallics spread over the whole joints, and the solder remained randomly island-shaped. The δ-AuSn, ε-AuSn₂, and η-AuSn₄ intermetallic compounds formed sequentially from the Au stud bump. The microstructure of the solder joints did not change significantly even after multiple reflows. The AuSn₄ was the main phase after reflow because of the fast dissolution of Au. In the solder joints fabricated using Cu stud bumps, the scallop-type Cu₆Sn₅ intermetallic was formed only at the Cu interface, and the solder was the main phase. The difference in the microstructure of the solder joints with Au and Cu stud bumps resulted from the dissolution-rate difference of Au and Cu into the solder.     

利用MATLAB 进行焦平面探测器的In 柱高度自动统计

In 柱制备是红外焦平面器件倒焊互连的关键工艺,In 柱高度是评价In 柱制备工艺水平的基本指标。通常的In 柱高度统计方法为随机采样人工显微镜观测法,此方法由于采样点较少将导致统计结果不全面,另一方面由于In 柱表面形貌的微观特性,人工显微镜观测引入的主观偏差将使统计结果不准确。提出了一种更合理可行的In 柱高度统计方法,首先使用激光共聚焦显微镜对In 柱表面形貌进行扫描,再利用MATLAB 软件对扫描数据进行分析以统计In 柱高度,分析时考虑In 柱表面微观形貌对In 柱高度的影响。利用此方法对1616 面阵的红外焦平面器件读出电路进行了In 柱高度统计,统计结果优于随机采样人工显微镜观测法。为评价In 柱制备工艺水平提供了更客观准确的 In 柱高度数据。     

凸点材料的选择对器件疲劳特性的影响

为了研究凸点材料对器件疲劳特性的影响,采用非线性有限元分析方法、统一型黏塑性本构方程和Coffin-Manson修正方程,对Sn3.0Ag0.5Cu,Sn63Pb37和Pb90Sn10三种凸点材料倒装焊器件的热疲劳特性进行了系统研究,对三种凸点的疲劳寿命进行了预测,并对Sn3.0Ag0.5Cu和Pb90Sn10两种凸点材料倒装焊器件进行了温度循环试验.结果表明,仿真结果与试验结果基本吻合.在热循环过程中,凸点阵列中距离器件中心最远的焊点,应力和应变变化最剧烈,需重点关注这些危险焊点的可靠性;含铅凸点的热疲劳特性较无铅凸点更好,更适合应用于高可靠的场合;而且随着铅含量的增加,凸点的热疲劳特性越好,疲劳寿命越长.     

Connection of VLSI chips to printed circuit board using stacked solder bumps

A new type of flip-chip interconnection technology usingstacked solder bumps is proposed, where the diameter of theupper solder bump is less than that of the lower ones. This isto reduce the capacitance between the stacked solder bumps and the ground plane and to prolong the lifetime ofthe solder joints.     

Formation of Pb/63Sn solder bumps using a solder droplet jetting method

Formation processes of Pb/63Sn solder droplets using a solder droplet jetting have not been sufficiently reported. Solving problems such as satellite droplets and position errors are very important for a uniform bump size and reliable flip-chip solder bump formation process. First, this paper presents the optimization of jet conditions of Pb/63Sn solder droplets and the formation process of Pb/63Sn solder bumps using a solder droplet jetting method. Second, interfacial reactions and mechanical strength of jetted Pb/63Sn solder bumps and electroless Ni-P/Au UBM joints have been investigated. Interfacial reactions have been investigated after the second solder reflow and aging, and results were compared with those of solder bumps formed by a solder screen-printing method. Third, jetted solder bumps with variable bump sizes have been demonstrated by a multiple jetting method and the control of waveform induced to a jet nozzle. Multiple droplets jetting method can control various height and size of solder bumps. Finally, real applications of jetted Pb/63Sn solder bumps have been successfully demonstrated on conventional DRAM chips and integrated passive devices (IPDs).     

Wafer level and flip chip design through solder prediction modelsand validation

In flip chip package applications, bumped dies are flip-chip assembled to substrate metal pads creating joints that serve electrically and mechanically. Resulting solder joint profiles are defined by the solder bump volume, the under bump metallurgy (LTBM) area, and the substrate metal pad size and shape. Solder bump height and diameter was predicted by the geometrical truncated sphere model and surface evolver model at the wafer level, using the known solder volume deposited by stencil printing method. The surface evolver model was used to predict the assembled solder joint height, gap height, collapse height, and maximum bump diameter of flip chip assemblies. In turn, substrate pads were fine-tuned to achieve required gap heights. Collapse heights provided the means to develop assembly tolerances and relative risk of bridging was determined from knowledge of resulting bump diameters. Through validated design of the stencil printing technology and prediction of realistic bump and assembly solder geometries, the results are improved processes and die level design and assembly. Optimized design parameters are incorporated and accurately represented in simulation and experimentally validated with assemblies     

Comparing the Impacts of the Capillary and the Molded Underfill Process on the Reliability of the Flip-Chip BGA

In the assembly process for the conventional capillary underfill (CUF) flip-chip ball grid array (FCBGA) packaging the underfill dispensing creates bottleneck. The material property of the underfill, the dispensing pattern and the curing profile all have a significant impact on the flip-chip packaging reliability. Due to the demand for high performance in the CPU, graphics and communication market, the large die size with more integrated functions using the low-K chip must meet the reliability criteria and the high thermal dissipation. In addition, the coplanarity of the flip-chip package has become a major challenge for large die packaging. This work investigates the impact of the CUF and the novel molded underfill (MUF) processes on solder bumps, low-K chip and solder ball stress, packaging coplanarity and reliability. Compared to the conventional CUF FCBGA, the proposed MUF FCBGA packaging provides superior solder bump protection, packaging coplanarity and reliability. This strong solder bump protection and high packaging reliability is due to the low coefficient of thermal expansion and high modulus of the molding compound. According to the simulation results, the maximum stress of the solder bumps, chip and packaging coplanarity of the MUF FCBGA shows a remarkable improvement over the CUF FCBGA, by 58.3%, 8.4%, and 41.8% (66 $mu {rm m}$), respectively. The results of the present study indicates that the MUF packaging is adequate for large die sizes and large packaging sizes, especially for the low-K chip and all kinds of solder bump compositions such as eutectic tin-lead, high lead, and lead free bumps.      

Al surface morphology effect on flip-chip solder bump shear strength

This paper reports the result of a study on the effect of aluminum pad surface morphology on the flip-chip solder bump reliability. The influence of the Al surface morphology on the electroless zinc/nickel/gold UBM is presented. The reliability of the solder bump as measured by ball shear force is reported. Al pad were produced using two RF sputtering systems: CVC-601 and Varian-3180. The Al targets used in CVC and Varian system were 99%Al–1%Si and 98.95%Al–1%Si–0.05%Ti respectively. The surface of the CVC sputtered Al samples were smooth while the surface of the Varian sputtered Al samples were rough. All the samples were subjected to the electroless zinc/nickel/gold plating. The results suggest that after plating, the smooth Al surface resulted in a fine nickel UBM surface while the rough Al surface formed a coarse nickel UBM surface. Ball shear test was conducted after the solder balls were bumped on the UBM. Result shows that the fine UBM surface samples have twice the shear strength compared to the samples with coarse UBM surface samples. The analysis of the results indicates that shear surface occurred at the UBM and the solder interface for samples with rough UBM surface leading to the lower shear strength. Nickel bump shear test result shows that pretreatment of Al pad surface by sodium hydroxide and nitric acid created more zinc seeds this led to better electroless nickel plating. Nickel bump shear tests also shows that double zincated bumps had higher shear strength than single zincated bumps. To obtain reliable flip-chip solder bumps, it is essential to maintain good Al pad surface morphology, pretreatment of the Al pad and undergo second zincation.     

Optoelectronic and microwave transmission characteristics of indium solder bumps for low-temperature flip-chip applications

This paper describes low-temperature flip-chip bonding for both optical interconnect and microwave applications. Vertical-cavity surface-emitting laser (VCSEL) arrays were flip-chip bonded onto a fused silica substrate to investigate the optoelectronic characteristics. To achieve low-temperature flip-chip bonding, indium solder bumps were used, which had a low melting temperature of 156.7/spl deg/C. The current-voltage (I-V) and light-current (L-I) characteristics of the flip-chip bonded VCSEL arrays were improved by Ag coating on the indium bump. The I-V and L-I curves indicate that optical and electrical performances of Ag-coated indium bumps are superior to those of uncoated indium solder bumps. The microwave characteristics of the solder bumps were investigated by using a flip-chip-bonded coplanar waveguide (CPW) structure and by measuring the scattering parameter with an on-wafer probe station for the frequency range up to 40 GHz. The indium solder bumps, either with or without the Ag coating, provided good microwave characteristics and retained the original characteristic of the CPW signal lines without degradation of the insertion and return losses by the solder bumps.     

Controllability of novel Sn/sub 0.95/Au/sub 0.05/ microbumps using interlaminated tin and gold layers for flip-chip interconnection

A flip-chip interconnection technology using novel lead-free solder microbumps with a balling temperature as low as 220 /spl deg/C is presented. Controllability of newly developed Sn/sub 0.95/Au/sub 0.05/ microbumps has been examined experimentally. By varying the bump volume and the diameter of the wettable bump electrodes, Sn/sub 0.95/Au/sub 0.05/ microbumps with heights from 11 /spl mu/m to 37 /spl mu/m were successfully fabricated with a standard deviation of 1.5 /spl mu/m. The deviation of on-chip CPW impedance from 50 /spl Omega/ was lower than 10% for nonmetallization motherboard. The smaller bumps exhibited a better performance since the degradation of reflection properties is ascribed to the bump capacitance, which was estimated 10-20 fF. Because of high process yield and good performance, the flip-chip bonding using Sn/sub 0.95/Au/sub 0.05/ microbumps of the order of 20 /spl mu/m in height may be advantageous for W-band interconnection of InP- or GaAs-based devices.     

Electrothermal coupling analysis of current crowding and Joule heating in flip-chip packages

Solder bumps serve as electrical paths as well as structural support in a flip-chip package assembly. Owing to the differences of feature sizes and electric resistivities between a solder bump and its adjacent traces, current densities around the regions where traces connect the solder bump increase in a significant amount. This current crowding effect along with the induced Joule heating would accelerate fatigue failure due to electromigration. In this paper we apply the three-dimensional electrothermal coupling analysis to investigate current crowding and Joule heating in a flip-chip package assembly carrying different constant electric currents under different ambient temperatures. Experiments are conducted to calibrate temperature-dependent electric resistivities of solder alloy, Al trace, and Cu trace, and to verify the numerical model by comparing calculated and measured maximum temperatures on the die surface. Through the electrothermal coupling analysis, effects of current crowding and Joule heating induced by different solder bump structures are examined and compared.     

Fundamental Study of the Intermixing of 95Pb-5Sn High-Lead Solder Bumps and 37Pb-63Sn Pre-Solder on Chip-Carrier Substrates

This study investigated the intermixing of 95Pb-5Sn solder bumps and 37Pb-63Sn pre-solder in flip-chip solder joints. The reaction conditions included multiple reflows (up to ten) at 240°C, whereby previously solder-coated parts are joined by heating without using additional solder. We found that the molten pre-solder had an irregular shape similar to a calyx (i.e., a cup-like structure) wrapped around a high-lead solder bump. The height to which the molten pre-solder ascended along the solid high-lead solder bump increased with the number of reflows. The molten pre-solder was able to reach the under bump metallurgy (UBM)/95Pb-5Sn interface after three to five reflows. The molten pre-solder at the UBM/95Pb-5Sn interface generated two important phenomena: (1) the molten solder dewetted (i.e., flowed away from the soldered surface) along the UBM/95Pb-5Sn interface, particularly when the number of reflows was high, and (2) the molten pre-solder transported Cu␣atoms to the UBM/95Pb-5Sn interface, which in turn caused the Ni-Sn compounds at the chip-side interface to change into (Cu_0.6Ni_0.4)₆Sn₅.     

Investigation of flip chip under bump metallization systems of Cupads

In this study, UBM material systems for flip chip solder bumps on Cu pads were investigated using the electroless copper (E-Cu) and electroless nickel (E-Ni) plating methods; and the effects of the interfacial reaction between UBMs and Sn-36Pb-2Ag solders on the solder bump joint reliability were also investigated to optimize UBM materials for flip chip on Cu pads. For the E-Cu UBM, scallop-like Cu₆Sn₅, intermetallic compound (IMC) forms at the solder/E-Cu interface, and bump fracture occurred along this interface under a relatively small load. In contrast, at the E-Ni/E-Cu UBM, E-Ni serves as a good diffusion-barrier layer. The E-Ni effectively limited the growth of the IMC at the interface, and the polygonal-shape Ni₃ Sn₄ IMC resulted in a relatively higher adhesion strength compared with the E-Cu UBM. As a result, electroless deposited UBM systems were successfully demonstrated as low cost UBM alternatives on Cu pads. It was found that the E-Ni/E-Cu UBM material system was a better choice for solder flip chip interconnection on Cu pads than the E-Cu UBM     

Eutectic Sn-Ag solder bump process for ULSI flip chip technology

A novel eutectic Pb-free solder bump process, which provides several advantages over conventional solder bump process schemes, has been developed. A thick plating mask can be fabricated for steep wall bumps using a nega-type resist with a thickness of more than 50 μm by single-step spin coating. This improves productivity for mass production. The two-step electroplating is performed using two separate plating reactors for Ag and Sn. The Sn layer is electroplated on the Ag layer. Eutectic Sn-Ag alloy bumps can be easily obtained by annealing the Ag/Sn metal stack. This electroplating process does not need strict control of the Ag to Sn content ratio in alloy plating solutions. The uniformity of the reflowed bump height within a 6-in wafer was less than 10%. The Ag composition range within a 6-in wafer was less than ±0.3 wt.% Ag at the eutectic Sn-Ag alloy, analyzed by ICP spectrometry. SEM observations of the Cu/barrier layer/Sn-Ag solder interface and shear strength measurements of the solder bumps were performed after 5 times reflow at 260°C in N₂ ambient. For the Ti(100 nm)/Ni(300 nm)/Pd(50 nm) barrier layer, the shear strength decreased to 70% due to the formation of Sn-Cu intermetallic compounds. Thicker Ti in the barrier metal stack improved the shear strength. The thermal stability of the Cu/barrier layer/Sn-Ag solder metal stack was examined using Auger electron spectrometry analysis. After annealing at 150°C for 1000 h in N₂ ambient, Sn did not diffuse into the Cu layer for Ti(500 nm)/Ni(300 nm)/Pd(50 nm) and Nb(360 nm)/Ti(100 nm)/Ni(300 nm)/Pd(50 nm) barrier metal stacks. These results suggest that the Ti/Ni/Pd barrier metal stack available to Sn-Pb solder bumps and Au bumps on Al pads is viable for Sn-Ag solder bumps on Cu pads in upcoming ULSIs