Bipolar high-gain limiting amplifier IC for optical-fiber receivers operating up to 4 Gbit/s

A monolithic integrated high-gain limiting amplifier for future optical-fiber receivers is described. It is characterized by the following features: high insertion-voltage gain (maximum 54 dB); high input dynamic range (about 52 dB) at constant output-voltage swing (400 mV/SUB p-p/); high operating speed (up to at least 4 Gb/s); low power dissipation (350 mW at 50-/spl Omega/ load); standard supply voltage (5 V); 50-/spl Omega/ output buffer; one-chip solution; and small fabrication costs by use of a 2-/spl mu/m standard bipolar technology without needing polysilicon self-aligning processes. The good values of operating speed and power consumption, which the authors believe has until now not nearly been achieved by other comparable bipolar amplifier ICs, are a result of careful circuit design and optimization. The amplifier was extended to a high-sensitivity (amplitude and time) decision circuit operating at up to 4.0 Gb/s by adding a high-speed master-slave D-flip-flop IC fabricated with the same technology.     

10-Gb/s limiting amplifier and laser/modulator driver in 0.18-/spl mu/m CMOS technology

A limiting amplifier incorporates active feedback, inductive peaking, and negative Miller capacitance to achieve a voltage gain of 50 dB, a bandwidth of 9.4 GHz, and a sensitivity of 4.6 mV/sub pp/ for a bit-error rate of 10/sup -12/ while consuming 150 mW. A driver employs T-coil peaking and negative impedance conversion to achieve operation at 10 Gb/s while delivering a current of 100 mA to 25-/spl Omega/ lasers or a voltage swing of 2 V/sub pp/ to 50-/spl Omega/ modulators with a power dissipation of 675 mW. Fabricated in 0.18-/spl mu/m CMOS technology, both prototypes operate with a 1.8-V supply.     

6-k/spl Omega/ 43-Gb/s differential transimpedance-limiting amplifier with auto-zero feedback and high dynamic range

A high-gain, 43-Gb/s InP HBT transimpedance-limiting amplifier (TIALA) with 100-/spl mu/A/sub pp/ sensitivity and 6 mA/sub pp/ input overload current is presented. The circuit also operates as a limiting amplifier with 40-dB differential gain, better than 15-dB input return loss, and a record-breaking sensitivity of 8 mV/sub pp/ at 43 Gb/s. It features a differential TIA stage with inductive noise suppression in the feedback network and consumes less than 450mW from a single 3.3-V supply. The TIALA has 6-k/spl Omega/ (76dB/spl Omega/) differential transimpedance gain and 35-GHz bandwidth and comprises the transimpedance and limiting gain functions, an auto-zero dc feedback circuit, signal level monitor, and slicing level adjust functions. Other important features include 45-dB isolation and 800-mV/sub pp/ differential output.     

High-gain transimpedance amplifier in InP-based HBT technology forthe receiver in 40-Gb/s optical-fiber TDM links

A monolithic integrated transimpedance amplifier for the receiver in a 40-Gb/s optical-fiber TDM system has been fabricated in an InP-based HBT technology. Despite its high gain (transimpedance of 2 kΩ in the limiting mode, 10 kΩ in the linear mode) the complete amplifier was realized on a single chip. Clear output eye diagrams were measured up to 43 Gb/s under realistic driving conditions. The voltage swing of 0.6 V_pp at the differential 50 Ω output does not change within the demanded input dynamic range of 6 dB. At the upper input current level even 48 Gb/s were achieved. The power consumption is approximately 600 mW at a single supply voltage of -5.5 V     

40-Gb/s circuits built from a 120-GHz f/sub T/ SiGe technology

Product designs for 40-Gb/s applications fabricated from SiGe BiCMOS technologies are now becoming available. In this paper we first briefly discuss heterojunction bipolar transistor (HBT) device operation at high speed, demonstrating that perceived concerns regarding lower BV/sub CEO/ and higher current densities required to operate silicon HBTs at such high speeds do not in actuality limit design or performance. The high-speed portions of the 40-Gb/s system are then addressed individually. We demonstrate the digital capability through a 4: 1 multiplexer and a 1 : 4 demultiplexer running over 50 Gb/s error free at a -3.3-V power supply. We also demonstrate a range of analog elements, including a lumped limiting amplifier which operates with a 35-GHz bandwidth, a transimpedance amplifier with 220-/spl Omega/ gain and 49.1-GHz bandwidth, a 21.5-GHz voltage-controlled oscillator with over -100-dBc/Hz phase noise at 1-MHz offset, and a modulator driver which runs a voltage swing twice the BV/sub CEO/ of the high-speed SiGe HBT. These parts demonstrate substantial results toward product offerings, on each of the critical high-speed elements of the 40-Gb/s system.     

Low-power InP/GaAsSb/InP DHBT cascode transimpedance amplifier with GBP/P/sub dc/ of 7.2 GHz/mW

A low-power high gain-bandwidth monolithic cascode transimpedance amplifier using novel InP/GaAsSb/InP DHBT technology was investigated. The amplifier exhibited state-of-the-art performance of 17.3 dB gain, 12 GHz bandwidth, 55 dB/spl Omega/ transimpedance, and a corresponding gain-bandwidth of 6.7 THz/spl Omega/ while consuming only 12.2 mW DC power. It also achieved good gain-bandwidth-product per DC power figure-of-merit (GBP/P/sub dc/) of 7.2 GHz/mW     

A 3-V fully differential distributed limiting driver for 40-Gb/s optical transmission systems

A fully differential 40-Gb/s electro-absorption modulator driver is presented. Based on a distributed limiting architecture, the circuit can supply up to 3.0-V/sub pp/ (peak-to-peak) per side in a 50-/spl Omega/ load at data rates as high as 44 Gb/s. Both the input and the output are internally matched to 50 /spl Omega/ and exhibit return loss of better than 10 dB up to 50 GHz. Additional features of the driver include the use of a single -5.2-V supply, output swing control (1.7-3.0-V/sub pp/ per side), dc output offset control (-0.15 V to -1.1 V), and pulsewidth control (30% to 66%). The driver architecture was optimized based on a comprehensive analytical derivation of the frequency response of cascaded source-coupled field-effect transistor logic blocks using both single and double source-follower topologies.     

A high-speed 850-nm optical receiver front-end in 0.18-/spl mu/m CMOS

A high-speed optical interface circuit for 850-nm optical communication is presented. Photodetector, transimpedance amplifier (TIA), and post-amplifier are integrated in a standard 0.18-/spl mu/m 1.8-V CMOS technology. To eliminate the slow substrate carriers, a differential n-well diode topology is used. Device simulations clarify the speed advantage of the proposed diode topology compared to other topologies, but also demonstrate the speed-responsivity tradeoff. Due to the lower responsivity, a very sensitive transimpedance amplifier is needed. At 500 Mb/s, an input power of -8 dBm is sufficient to have a bit error rate of 3/spl middot/10/sup -10/. Next, the design of a broadband post-amplifier is discussed. The small-signal frequency dependent gain of the traditional and modified Cherry-Hooper stage is analyzed. To achieve broadband operation in the output buffer, so-called "f/sub T/ doublers" are used. For a differential 10 mV/sub pp/ 2/sup 31/-1 pseudo random bit sequence, a bit error rate of 5/spl middot/10/sup -12/ at 3.5 Gb/s has been measured. At lower bit-rates, the bit error rate is even lower: a 1-Gb/s 10-mV/sub pp/ input signal results in a bit error rate of 7/spl middot/10/sup -14/. The TIA consumes 17mW, while the post-amplifier circuit consumes 34 mW.     

A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end

A fully integrated 10-Gb/s optical receiver analog front-end (AFE) design that includes a transimpedance amplifier (TIA) and a limiting amplifier (LA) is demonstrated to require less chip area and is suitable for both low-cost and low-voltage applications. The AFE is fabricated using a 0.18-/spl mu/m CMOS technology. The tiny photo current received by the receiver AFE is amplified to a differential voltage swing of 400 mV/sub (pp)/. In order to avoid off-chip noise interference, the TIA and LA are dc-coupled on the chip instead of ac-coupled though a large external capacitor. The receiver front-end provides a conversion gain of up to 87 dB/spl Omega/ and -3dB bandwidth of 7.6 GHz. The measured sensitivity of the optical receiver is -12dBm at a bit-error rate of 10/sup -12/ with a 2/sup 31/-1 pseudorandom test pattern. Three-dimensional symmetric transformers are utilized in the AFE design for bandwidth enhancement. Operating under a 1.8-V supply, the power dissipation is 210 mW, and the chip size is 1028 /spl mu/m/spl times/1796 /spl mu/m.     

Substrate coupling in a high-gain 30-Gb/s SiGe amplifier-modeling, suppression, and measurement

For demonstrating substrate coupling in high-gain broadband amplifiers, a limiting differential transimpedance amplifier has been developed and fabricated in a SiGe bipolar technology. It operates up to 30 Gb/s and stands out for a maximum (nonlinear) transimpedance in the limiting mode of 25 k/spl Omega/, resulting in a gain /spl times/ speed product as high as 750 k/spl Omega//spl middot/Gb/s. This record value could be achieved by applying several techniques for suppression of noise coupling simultaneously. The effectiveness of each technique was verified experimentally by measuring the output eye diagrams of different mounted amplifier versions. The high accuracy potential of the substrate modeling tools applied for optimizing the amplifier design has been demonstrated separately by measurements on special (mounted) test structures up to 40 GHz. These investigations also showed the strong degradation of shielding measures by bond inductances with increasing frequency.     

1.25 Gb/s低功耗CMOS光接收机限幅放大器

设计并实现了用于光纤用户网和千兆以太网光接收机的限幅放大器。电路采用有源电感负载来拓展带宽、稳定直流工作点 ,通过直接耦合技术来提高增益、降低功耗。测试结果表明 ,在从 5 m Vp- p到 5 0 0 m Vp- p,即40 d B的输入动态范围内 ,在 5 0 Ω负载上的单端输出电压摆幅稳定在 2 80 m Vp- p。在 5 V电源电压下 ,功耗仅为1 30 m W。电路可稳定工作在 1 5 5 Mb/s、62 2 Mb/s、1 .2 5 Gb/s三个速率上。     

Optical receiver IC for CD/DVD/blue-laser application

In this paper, an optoelectronic receiver IC for CD, DVD, and Blue-Laser optical data storage applications is presented. The IC was developed in a 0.5-/spl mu/m BiCMOS technology with integrated PIN photodiodes. It includes a new architecture of high-speed and low-noise variable gain transimpedance amplifiers witch current preamplifier input. The amplifier transimpedance gain is programmable over a gain range of 130 /spl Omega/ to 270 k/spl Omega/ by a serial interface. The amplifier small-signal bandwidth is 260 MHz for the highest gain, which gives a gain-bandwidth product of 70 THz/spl Omega/ and a sensitivity improvement by a factor of 2 compared to published OEICs. The amplifiers support a special write/clip mode which realizes a nonlinear gain reduction for high input signals. The output voltage buffers are 130-/spl Omega/ impedance matched for optimized data transmission over a flex cable. The impedance is generated by active-impedance synthesis to increase the output dynamic range.     

Design of a low-power 3.5-GHz broad-band CMOS transimpedance amplifier for optical transceivers

This paper describes a novel low-power low-noise CMOS voltage-current feedback transimpedance amplifier design using a low-cost Agilent 0.5-/spl mu/m 3M1P CMOS process technology. Theoretical foundations for this transimpedance amplifier by way of gain, bandwidth and noise analysis are developed. The bandwidth of the amplifier was extended using the inductive peaking technique, and, simulation results indicated a -3-dB bandwidth of 3.5 GHz with a transimpedance gain of /spl ap/60 dBohms. The dynamic range of the amplifier was wide enough to enable an output peak-to-peak voltage swing of around 400 mV for a test input current swing of 100 /spl mu/A. The output noise voltage spectral density was 12 nV//spl radic/Hz (with a peak of /spl ap/25 nV//spl radic/Hz), while the input-referred noise current spectral density was below 20 pA//spl radic/Hz within the amplifier frequency band. The amplifier consumes only around 5 mA from a 3.3-V power supply. A test chip implementing the transimpedance amplifier was also fabricated using the low-cost CMOS process.     

1-Gb/s 80-dB/spl Omega/ fully differential CMOS transimpedance amplifier in multichip on oxide technology for optical interconnects

A 1-Gb/s differential transimpedance amplifier (TIA) is realized in a 0.25-/spl mu/m standard CMOS technology, incorporating the regulated cascode input configuration. The TIA chip is then integrated with a p-i-n photodiode on an oxidized phosphorous-silicon (OPS) substrate by employing the multichip-on-oxide (MCO) technology. The MCO TIA demonstrates 80-dB/spl Omega/ transimpedance gain, 670-MHz bandwidth for 1-pF photodiode capacitance, 0.54-/spl mu/A average input noise current, -17-dBm sensitivity for 10/sup -12/ bit-error rate (BER), and 27-mW power dissipation from a single 2.5-V supply. It also shows negligible switching noise effect from an embedded VCO on the OPS substrate. Furthermore, a four-channel MCO TIA array is implemented for optical interconnects, resulting in less than -40-dB crosstalk between adjacent channels.     

Design and anaylsis of a 2.5-Gbps optical receiver analog front-end in a 0.35-/spl mu/m digital CMOS technology

This paper presents the design of an optical receiver analog front-end circuit capable of operating at 2.5 Gbit/s. Fabricated in a low-cost 0.35-/spl mu/m digital CMOS process, this integrated circuit integrates both transimpedance amplifier and post limiting amplifier on a single chip. In order to facilitate high-speed operations in a low-cost CMOS technology, the receiver front-end has been designed utilizing several enhanced bandwidth techniques, including inductive peaking and current injection. Moreover, a power optimization methodology for a multistage wide band amplifier has been proposed. The measured input-referred noise of the optical receiver is about 0.8 /spl mu/A/sub rms/. The input sensitivity of the receiver front-end is 16 /spl mu/A for 2.5-Gbps operation with bit-error rate less than 10/sup -12/, and the output swing is about 250 mV (single-ended). The front-end circuit drains a total current of 33 mA from a 3-V supply. Chip size is 1650 /spl mu/m/spl times/1500 /spl mu/m.     

Modulator driver and photoreceiver for 20 Gb/s optic-fiber links

Two integrated circuits, a modulator driver and a photoreceiver integrating a metal-semiconductor-metal (MSM) photodetector, a differential transimpedance amplifier and two limiting amplifier stages for high-speed optical-fiber links are presented. The IC's were manufactured in a 0.2 μm gate-length AlGaAs-GaAs high-electron mobility transistor (HEMT) technology with a f_T of 60 GHz. The modulator driver IC operates up to 25 Gb/s with an output voltage swing of 3.3 V_p-p at each output. The 1.3-1.55 μm wavelength monolithically integrated photoreceiver optoelectronic integrated circuit (OEIC) has a bandwidth of 17 GHz with a high transimpedance gain of 12 kΩ. Eye diagrams are demonstrated at 20 Gb/s with an output voltage of 1 V_p.p     

应用于10Gb/s光接收机的全差分CMOS跨阻前置电路设计

设计了一种的低成本、低功耗的10 Gb/s光接收机全差跨阻前置放大电路。该电路由跨阻放大器、限幅放大器和输出缓冲电路组成,其可将微弱的光电流信号转换为摆幅为400 mVpp的差分电压信号。该全差分前置放大电路采用0.18 m CMOS工艺进行设计,当光电二极管电容为250 fF时,该光接收机前置放大电路的跨阻增益为92 dB,-3 dB带宽为7.9 GHz,平均等效输入噪声电流谱密度约为23 pA/(0~8 GHz)。该电路采用电源电压为1.8 V时,跨阻放大器功耗为28 mW,限幅放大器功耗为80 mW,输出缓冲器功耗为40 mW,其芯片面积为800 m1 700 m。     

High-gain differential CMOS transimpedance amplifier with on-chip buried double junction photodiode

An integrated fully differential CMOS transimpedance amplifier (TIA) with buried double junction photodiode input is described. The TIA features a variable high transimpedance gain (250 k/spl Omega/ to 2.5 M/spl Omega/), large DC photocurrent rejection capability (>55 dB) and low input referred noise density at 100 kHz (2pA//spl radic/Hz).     

Low-voltage high performance compact all cascode CMOS current mirror

A high performance and compact current mirror with extremely low input and high output resistances (R/sub in//spl sim/0.01/spl Omega/, R/sub out//spl sim/10 G/spl Omega/), high copying accuracy, very low input and output voltage requirements (V/sub in/, V/sub out//spl ges/V/sub DSsat/), high bandwidth (200 MHz using a 0.5 /spl mu/m CMOS technology) and low settling time (25 ns) is proposed. Simulations and experimental results are shown that validate the circuit.     

2.5Gb/Scmos光接收机跨阻前置放大器

给出了一种利用0.35μm CMOS工艺实现的2.5Gb/s跨阻前置放大器。此跨阻放大器的增益为59 dB*Ω,3dB带宽为2GHz,2GHz处的等效输入电流噪声为0.8×10-22 A2/Hz。在标准的5V电源电压下,功耗为250mW。PCML单端输出信号电压摆幅为200mVp-p。整个芯片面积为1.0mm×1.1mm。