低压下极大规模集成电路碱性铜化学机械抛光液的研究

对低压下铜化学机械抛光(CMP)碱性抛光液的性能进行了研究.在分析碱性抛光液作用机理的基础上,对铜移除速率、表面粗糙度等性能进行了考察.结果表明:加入络合剂R(NH2)m(OH)n实现铜在碱性抛光液中的溶解,同时提高了的铜移除速率(41.34kPa:1050nm/min; 6.89kPa:440nm/min)并降低了表...     

Analysis of process variations impact on the single-event transient quenching in 65 nm CMOS combinational circuits

Single-event transient pulse quenching(Quenching effect)is employed to effectively mitigate WSET(SET pulse width).It enhanced along with the increased charge sharing which is norm for future advanced technologies.As technology scales,parameter variation is another serious issue that significantly affects circuit’s performance and single-event response.Monte Carlo simulations combined with TCAD(Technology Computer-Aided Design)simulations are conducted on a six-stage inverter chain to identify and quantify the impact of charge sharing and parameter variation on pulse quenching.Studies show that charge sharing induce a wider WSET spread range.The difference of WSET range between no quenching and quenching is smaller in NMOS(N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor)simulation than that in PMOS’(P-Channel Metal-Oxide-Semiconductor Field-Effect Transistor),so that from parameter variation view,quenching is beneficial in PMOS SET mitigation.The individual parameter analysis indicates that gate oxide thickness(TOXE)and channel length variation(XL)mostly affect SET response of combinational circuits.They bring 14.58%and 19.73%average WSET difference probabilities for no-quenching cases,and 105.56%and 123.32%for quenching cases.     

65 nm闪存芯片擦除时间退化的优化设计

随着制造工艺进入65 nm节点,闪存的可靠性问题也越来越突出,其中闪存芯片擦除速度随着擦写循环的增加出现明显退化。该文从单个存储器件的擦写退化特性入手,详细讨论了隧穿氧化层缺陷的产生原因、对器件性能的影响及其导致整个芯片擦除时间退化的内在机理,并提出针对性的优化方案:采用阶梯脉冲电压擦写方式减缓存储单元退化;对非选中区块进行字线浮空偏置以抑制擦除时的阵列干扰。该文基于65 nm NOR Flash工艺平台开发了128 Mb闪存芯片,并对该方案进行了验证,测试结果表明,采用优化设计方案的芯片经过10万次擦写后的Sector擦除时间为104.9 ms,较采用常规方案的芯片（大于200 ms）具有明显的提升。     

Experimental characterization of the bipolar effect on P-hit single-event transients in 65 nm twin-well and triple-well CMOS technologies

Single-event charge collection is controlled by drift, diffusion and the bipolar effect. Previous work has established that the bipolar effect is significant in the p-type metal-oxide-semiconductor field-effect transistor (PMOS) in 90 nm technology and above. However, the consequences of the bipolar effect on P-hit single-event transients have still not completely been characterized in 65 nm technology. In this paper, characterization of the consequences of the bipolar effect on P-hit single-event transients is performed by heavy ion experiments in both 65 nm twin-well and triple-well complementary metal-oxide-semiconductor (CMOS) technologies. Two inverter chains with clever layout structures are explored for the characterization. Ge (linear energy transfer (LET) = 37.4 MeV cm²/mg) and Ti (LET = 22.2 MeV cm²/mg) particles are also employed. The experimental results show that with Ge (Ti) exposure, the average pulse reduction is 49 ps (45 ps) in triple-well CMOS technology and 42 ps (32 ps) in twin-well CMOS technology when the bipolar effect is efficiently mitigated. This characterization will provide an important reference for radiation hardening integrated circuit design.     

基于65 nm体硅CMOS技术的DICE-DFF和TMR-DFF SEU辐射硬化方法分析

基于65 nm体硅CMOS工艺,采用移位寄存器链方式对普通触发器(DFF)、2种双互锁触发器(DICE-DFF,FDICE-DFF)、普通触发器空间三模冗余(TMR-DFF)和2种普通触发器时间三模冗余(TTMR-DFF300,TTMR-DFF600)这6种结构进行单粒子翻转(SEU)性能试验评估。利用Ti、Cu、Br、I、Au和Bi这6种离子对被测电路进行轰击,试验结果表明,普通触发器单粒子翻转截面最大,约为3.5×10?8～1.7×10?7 cm2/bit;时钟间隔时间600 ps的时间三模冗余结构触发器单粒子翻转截面最小,约为5×10?11～7×10?10 cm2/bit,仅为普通触发器的0.1%左右。同时,针对6种触发器单元,从速度、面积、晶体管数量以及抗SEU性能多方面进行综合分析,为后续超大规模集成电路抗SEU设计提供了一定的指导意义。     

铜合金表面Ti/TiN多层膜的制备、结构及其性能

为了研究多层膜的腐蚀性能,促进多层膜在生产中的应用,采用电弧离子镀技术,通过调整环境N₂和Ar气的时间比例在铜衬底上成功制备了不同调制周期的Ti/TiN多层膜.利用x 射线衍射谱和交流阻抗谱研究了该多层膜的结构和腐蚀性能.表面形貌显示,沉积的Ti/TiN多层膜具有明显的周期性,环境中N2和Ar气的时间比例决定了多层膜的调制周期,N₂气时间越长,多层膜中TiN相层越厚.腐蚀性能测定表明,多层膜的调制周期影响其耐蚀性,当调制周期为550nm时,沉积膜的耐腐蚀性最好.     

悬浮液直接进样-火焰原子吸收法测定土壤中的铜

将悬浮液直接进样技术应用于火焰原子吸收光谱法对土壤中铜的测定,探讨了介质酸度以及悬浮液浓度对测定结果的影响,并与采用湿法处理的样品测定结果进行了比较,结果令人满意。     

Siliconizing formation mechanism and its property by slurry pack cementation on electro-deposited nickel layer into copper matrix

Silicide coating was prepared on electro-deposited nickel layer by the slurry pack cementation process on copper matrix at 1173 K for 12 h using SiO₂ as Si source, pure Al powder as reducer, a dual activator of NaF+NH₄Cl and albumen (egg white) as cohesive agent. Microstructure, properties and siliconizing mechanism of silicide coating were discussed. The experimental results show that the silicide coating with 220 μm thickness is mainly composed of a Ni₂Si phase and a small amount of Ni₃₁Si₁₂ phase. Its mean microhardness (HV 790) is ten times than that of copper substrate (HV 70). The coefficient of friction decreases from 0.8 of pure copper to about 0.3 of the siliconzed sample. SiF₂, SiCl₂ and SiCl₃ are responsible for the transportation and deposition of Si during the slurry pack cementation process.     

交接配线在用户线路网中的应用分析

文章对我国用户线路网中的主要配线方式——交接配线的各种形式进行了分析比较，对每种方式的具体运用环境进行了介绍。电缆容量的确定方法作了说明。     

Characterization of single-event multiple cell upsets in a custom SRAM in a 65 nm triple-well CMOS technology

In this paper, the characterization of single event multiple cell upsets(MCUs) in a custom SRAM is performed in a 65 nm triple-well CMOS technology, and O(linear energy transfer(LET) = 3.1 Me V cm2/mg), Ti(LET = 22.2 Me V cm2/mg) and Ge(LET = 37.4 Me V cm2/mg) particles are employed. The experimental results show that the percentage of MCU events in total upset events is 71.11%, 83.47% and 85.53% at O, Ti and Ge exposures. Moreover, due to the vertical well isolation layout, 100%(O), 100%(Ti) and 98.11%(Ge) MCU cluster just present at one or two adjacent columns, but there are still 4 cell upsets in one MCU cluster appearing on the same word wire. The characterization indicates that MCUs have become the main source of soft errors in SRAM, and even though combining the storage array interleaving distance(ID) scheme with the error detection and correction(EDAC) technique, the MCUs cannot be completely eliminated, new radiation hardened by design techniques still need to be further studied.