Parallel trellis Viterbi algorithm for sparse channels

The Viterbi algorithm (VA), which normally operates using a single trellis, can be optimally reformulated into a set of independent trellises for a special class of sparse intersymbol interference (ISI) channels. These independent trellises operate in parallel and have less overall complexity than a single trellis. This trellis decomposition can be applied to a more general class of sparse channels approximately resulting in a suboptimal reduced complexity equalizer     

Suboptimum Viterbi algorithm for trellis-coded QAM scheme inmultipath Rayleigh fading channels

A new suboptimum Viterbi algorithm for trellis-coded quadrature amplitude modulation based on the channel state information of the multipath Rayleigh fading channel is proposed. Simulation results show that the proposed algorithm has merits for applications that require low bit energy-to-noise ratio     

Generalised Viterbi algorithm for trellis coded signals transmittedthrough broadband wireless channels

A receiver structure is proposed for trellis coded signals transmitted through broadband wireless channels based on the generalised Viterbi algorithm (GVA). Simulation results show that the proposed receiver structure is suitable for high bit rate wireless applications and gives close to optimal performances with reasonable complexity     

引入梯度导引似p范数约束的稀疏信道估计算法

为克服l0和l1范数约束的最小均方算法在不同信道稀疏程度下对稀疏信道估计中出现的收敛性能起伏较大等缺点,提出一种新的似p范数约束的最小均方算法,通过在最小均方算法代价函数中引入p值可变的似p范数约束以适应信道的不同稀疏程度,并在验证代价函数凸性的基础上导出p值的梯度导引寻优。文中最后给出仿真实验及其讨论,实验结果表明了新算法的优越性。     

Viterbi decoding for impulsive interference satellite channels

Data taken from real satellite channels point to the fact that such non-Gaussian behaviour as burst noise exists. Since the probability density function (p.d.f.) which minimizes the Fisher information (I_f) subject to the given variance of noise is Gaussian, performance can be improved by taking into account the non-Gaussian nature of the actual noise p.d.f. To achieve the higher efficiency, a modem, which consists of a maximum likelihood sequence detector (MLSD) implemented by an adaptive Viterbi algorithm (VA), is introduced in this paper. The new form of the algorithm, based on the m-interval polynomial approximation (MIPA) method, which adjusts the operation of the VA decoder to ensure its robustness to changing and/or non-Gaussian noise conditions, leads to an improvement of the error probability in operation of the receiver. In contrast to coding techniques, this improvement through digital signal processing is not obtained at the expense of bandwidth expansion. Monte Carlo simulation results involving bit error rate (BER) support theoretical conclusions.     

The expectation-maximization Viterbi algorithm for blind adaptive channel equalization

A blind maximum-likelihood equalization algorithm is described and its convergence behavior is analyzed. Since the algorithm employs the Viterbi algorithm (VA) to execute the expectation step of the expectation-maximization (EM) iteration, we call it the expectation-maximization Viterbi algorithm (EMVA). An EMVA-based blind channel-acquisition technique which achieves a high global convergence probability is developed. The performance of the method is evaluated via numerical simulations under static and fading channel conditions.     

New adaptive Viterbi detector for fast-fading mobile-radio channels

A new method to significantly increase the performance of an adaptive Viterbi detector used on fast-fading mobile-radio channels is presented. The proposed method, which uses a predictor to counter the delay of the channel estimates, may reduce the bit error rate for high SNR by up to 90%.<>     

A burst-error-correcting Viterbi algorithm

A dual-mode burst-error-correcting algorithm that combines maximum-likelihood decoding with a burst detection scheme is presented. The decoder nominally operates as a Viterbi decoder and switches to time diversity error recovery whenever an uncorrectable error pattern is identified. It is demonstrated that the new scheme outperforms interleaving strategies under the constraint of a fixed overall decoding delay. It also proves to be more powerful than known adaptive burst decoding schemes, such as the Gallager burst finding scheme. As the new method can be used with soft decision decoding, it is mainly intended for use on random-error channels affected by occasional severe bursts     

Implementing the Viterbi algorithm

The Viterbi algorithm, an application of dynamic programming, is widely used for estimation and detection problems in digital communications and signal processing. It is used to detect signals in communication channels with memory, and to decode sequential error-control codes that are used to enhance the performance of digital communication systems. The Viterbi algorithm is also used in speech and character recognition tasks where the speech signals or characters are modeled by hidden Markov models. The article explains the basics of the Viterbi algorithm as applied to systems in digital communication systems, and speech and character recognition. It also focuses on the operations and the practical memory requirements to implement the Viterbi algorithm in real-time     

部分响应信道Viterbi算法研究

目前的磁盘存储系统为了满足高数据传输速率和高数据存储密度的要求,造成数字序列之间存在严重的码间干扰,阻碍接收端获得可靠信息。本文基于将磁记录信道均衡为离散时间的部分响应信道模型,接收端采用Viterbi算法对ISI（intersymbol interference）进行检测。通过对PRML检测方案的原理进行理论分析后,给出了磁记录系统中常用的3种部分响应信道模型的计算机仿真。结果表明Viterbi算法能有效地对ISI信道进行检测。     

A new transform algorithm for Viterbi decoding

Implementation of the Viterbi decoding algorithm has attracted a great deal of interest in many applications, but the excessive hardware/time consumption caused by the dynamic and backtracking decoding procedures make it difficult to design efficient VLSI circuits for practical applications. A transform algorithm for maximum-likelihood decoding is derived from trellis coding and Viterbi decoding processes. Dynamic trellis search operations are paralleled and well formulated into a set of simple matrix operations referred to as the Viterbi transform (VT). Based on the VT, the excessive memory accesses and complicated data transfer scheme demanded by the trellis search are eliminated. Efficient VLSI array implementations of the VT have been developed. Long constraint length codes can be decoded by combining the processors as the building blocks     

High-performance VLSI architecture for the Viterbi algorithm

The Viterbi (1967) algorithm (VA) is known to be an efficient method for the realization of maximum-likelihood (ML) decoding of convolutional codes. The VA is characterized by a graph, called a trellis, which defines the transitions between states. To define an area efficient architecture for the VA is equivalent to obtaining an efficient mapping of the trellis. We present a methodology that permits the efficient hardware mapping of the VA onto a processor network of arbitrary size. This formal model is employed for the partitioning of the computations among an arbitrary number of processors in such a way that the data are recirculated, optimizing the use of the PEs and the communications. Therefore, the algorithm is mapped onto a column of processing elements and an optimal design solution is obtained for a particular set of area and/or speed constraints. Furthermore, the management of the surviving path memory for its mapping and distribution among the processors was studied. As a result, we obtain a regular and modular design appropriate for its VLSI implementation in which the only necessary communications between processors are the data recirculations between stages     

Iterative Viterbi algorithm for concatenated multidimensional TCM

A novel compound code is designed for the multidimensional (M-D) Wei (1987) trellis code combined with a simple parity-check code. Using the iterative Viterbi decoding algorithm, we can achieve a remarkable performance improvement with low computational complexity. Simulation results show that at a bit error rate (BER) of 3.7 × 10^-6 about 2.2-dB additional net gain has been obtained over the conventional scheme of the 4-D 16-state Wei code at a spectral efficiency of 6.7871 bit/T     

Efficient Viterbi algorithm for signals with ISI

The authors propose an efficient method of implementing the Viterbi algorithm at Nyquist-rate, for linearly modulated signals corrupted by ISI and AWGN. When signalling is M-ary and ISI extends over L-1 symbols, this scheme results in M+CL (complex multiplications, C is the number of samples per symbol), whereas the whitened-matched-filter based Viterbi algorithm requires M^L complex multiplications     

联合判决估计的Viterbi译码算法

利用相邻几组判决数据之间的相互关系，对这几组数据进行联合判决估计，从而提两了Viterbi译码性能。从理论分析和仿真结果来看，当译码深度τ=2m左右时，译码性能相当于深度2τ传统算法的性能。此外，仿真表明参考状态的位置对性能影响不大。因此该算法在保证同等性能前提下，对留选路径存储的规模和功耗减少约20％，对回溯单元减少达30％。     

On the Viterbi decoding algorithm

A new interpretation of the Viterbi decoding algorithm based on the state-space approach to dyamical systems is presented. In this interpretation the optimum decoder solves a generalized regulator control problem by dynamic programming techniques.     

High-performance iterative Viterbi algorithm for conventionalserial concatenated codes

The Viterbi algorithm (1967) and conventional serial concatenated codes (CSCC) have been widely applied in digital communication systems over the last 30 years. We show that the Shannon capacity of additive white Gaussian noise (AWGN) channels can be approached by CSCCs and the iterative VA (IVA). We firstly study the algebraic properties of CSCCs. We then present the IVA to decode these codes. We also analyze the performance of the IVA and conclude that a better performance can be achieved if we replace the powerful block codes by some simple parity codes. One of the key results in this paper shows that by using a proper design for the decoding method, codes with small loops can be very efficiently decoded using a min-sum type algorithm. The numerical results show that the IVA can closely approach the Shannon sphere-packing lower bound and the Shannon limit. For block sizes ranging from 56 information bits to 11970 information bits, the IVA can perform to within about 1 dB of the Shannon sphere-packing lower bound at a block error rate of 10^-4. We show that the IVA has a very low complexity and can be applied to many current standard systems, for example, the Qualcomm code-division multiple-access (CDMA) system and the NASA concatenated system, with very little modification or, for some cases, without any modification     

A new architecture for the fast Viterbi algorithm

A novel architecture design to speed up the Viterbi algorithm is proposed. By increasing the number of states in the trellis, the serial operation of a traditional add-compare-select unit is transformed into a parallel operation, thus achieving a substantial speed increase. The proposed architecture would increase the speed by 33% at the expense of a fairly modest increase in area, thus becoming an attractive approach in high-speed applications. A simple example is shown to illustrate the proposed algorithm in maximum-likelihood sequence detector. A comparative synthesis is made to compare the proposed architecture with other approaches, and synthesis simulations confirm the projection of the throughput gain. Also, the proposed algorithm is extended to the block-processing architecture, and we show that an additional 50% speedup is achieved.     

Multitrellis Viterbi algorithm for indoor systems using narrowbeamantennas

In earlier work, the performance (in terms of data eye closure) of a threshold detector in 2- and 4-PSK modulation schemes has been analyzed for wireless indoor systems using narrowbeam antennas. Here, assuming the channel is known, a very efficient implementation of the Viterbi algorithm (VA) is included in the receiver, and a bit-error rate (BER) criterion is used to evaluate the receiver robustness to channel conditions. In contrast to the earlier work, it is seen that 4-PSK signals with VA detectors are indeed more robust than 2-PSK signals to channel conditions     

Performance of the Viterbi algorithm for interleaved convolutionalcodes

This paper presents a maximum-likelihood decoder for error-burst channels with a very efficient implementation. In particular, the encoder is formed of an interleaved convolutional code with generator polynomials of the type [g⁽¹⁾(D^I), g⁽²⁾(D^I)] (for a rate 1/2 coder), where I may assume a very high integer value. The decoder consists of the Viterbi algorithm (VA) optimized for these sparse polynomials. For a given decoded bit-error probability, the required delay time and memory requirements of this approach are more inferior by far than those of the traditional method of interleaving. Moreover, for bursts of an average length less than 1/2, this method provides better performance than the dual-mode burst-error-correcting algorithm