Reliability study of 3D IC packaging based on through-silicon interposer (TSI) and silicon-less interconnection technology (SLIT) using finite element analysis

Three-dimensional (3D) integration using the through-silicon via (TSV) approach becomes one promising technology in 3D packaging. 2.5D through-silicon interposer (TSI) is one of the applications of TSV technology, which provides a platform for realizing heterogeneous integration on the TSI interposer. However, TSV manufacturing faces several challenges including high cost. Si-less interconnection technology (SLIT) could overcome such challenges and provide the similar function and benefits as TSI interposer. In SLIT technology, TSVs and silicon substrate are eliminated and the back-end-of-line (BEOL) structures are the same as that in the TSI interposer. Thermo-mechanical reliability is still one important concern under process condition and thermal cycling (TC) test condition for both packaging technologies. In this study, solder joint reliability has been investigated and compared for both packaging technologies through finite element analysis (FEA). Reflow process induced low-k stress and package warpage have also been simulated and compared between packages with TSI and SLIT technologies. The simulation results show that SLIT-based package has comparable micro bump TC reliability as TSI-based package, but SLIT-based package has better C4 joint TC reliability than TSI-based package. SLIT-based package also has lower reflow-induced package warpage and low-k stress than TSI-based package. FEA simulation results verify that SLIT-based packaging is one of promising packaging technologies with good thermo-mechanical performance and cost efficiency.     

An overview of solder bump shape prediction algorithms withvalidations

The trend to reduce the size of electronic packages and develop increasingly sophisticated electronic devices with more, higher density inputs/outputs (I/Os), leads to the use of area array packages using chip scale packaging (CSP), flip chip (FC), and wafer level packaging (WLP) technologies. Greater attention has been paid to the reliability of solder joints and the assembly yield of the surface mounting process as use of advanced electronic packaging technologies has increased. The solder joint reliability has been observed to be highly dependent on solder joint geometry as well as solder material properties, such that predicting solder reflow shape became a critical issue for the electronic research community. In general, the truncated sphere method, the analytical solution and the energy-based algorithm are the three major methods for solder reflow geometry prediction. This research develops solder joint reliability design guidelines to accurately predict both the solder bump geometry and the standoff height for reflow soldered joints in area array packages. Three simulation methods such as truncated-sphere theory force-balanced analytical solution and energy-based approach for prediction of the solder bump geometry are each examined in detail, and the thermal enhanced BGA (TBGA) and flip chip packages are selected as the benchmark models to compare the simulation and experimental results. The simulation results indicate that all three methods can accurately predict the solder reflow shape in an accurate range     

Non-destructive identification of defects in integrated circuit packages by scanning acoustic microscopy

Scanning acoustic microscopy (SAM) has emerged as a powerful tool for the detection of defects in ceramic or plastic packaged integrated circuits. At the Singapore Institute of Standards and Industrial Research, we have been using SAM to identify packaging and/or assembly related defects across a broad spectrum of integrated circuit packages. In many cases, it has been the only technology available that is capable of quickly and non-destructively determining the precise failure mode, such as delamination.     

高密度陶瓷倒装焊封装可靠性试验开路后的失效定位

陶瓷材料具有优良的综合特性,被广泛应用于高可靠微电子封装.陶瓷倒装焊封装的特殊结构使得对其进行失效分析相较其他传统封装形式更为困难.针对一款在可靠性试验中发生开路的高密度陶瓷倒装焊封装器件,制定了一套从非破坏性到破坏性的试验方案对其进行分析.通过时域反射计(TDR)测试排除了基板内部失效的可能性,通过X射线(X-ray)检测、超声扫描显微镜(SAM)和光学显微分析初步断定失效位置,并最终通过扫描电子显微镜和X射线能谱仪实现了对该器件的准确的失效定位,确定失效位置为基板端镀Ni层.该失效分析方法对其他陶瓷倒装焊封装的失效检测及分析有一定的借鉴意义.     

大功率白光LED封装设计与研究进展

封装设计、材料和结构的不断创新使发光二极管(LED)性能不断提高.从光学、热学、电学、机械、可靠性等方面,详细评述了大功率白光LED封装的设计和研究进展,并对封装材料和工艺进行了具体介绍.提出LED的封装设计应与芯片设计同时进行,并且需要对光、热、电、结构等性能统一考虑.在封装过程中,虽然材料(散热基板、荧光粉、灌封胶)选择很重要,但封装工艺(界面热阻、封装应力)对LED光效和可靠性影响也很大.     

一种宽带多通道瓦片式T/R组件的研制

介绍了一种多通道瓦片式T/R组件的研制方法和关键技术。针对组件结构尺寸紧张、工作频率高且频带宽的要求,提出了一种新的高集成T/R组件三维立体组装方法,同时采用了多功能单片微波集成电路(MMIC)芯片技术、多芯片组装(MCM)技术提高集成度。通过对组件的热设计和密封性设计,确保了组件使用的长期可靠性。成功研制出尺寸为41.8 mm×8 mm×8.2 mm、质量不超过13 g的瓦片式T/R组件,具有4个收发通道,每个通道包含6位数控移相器和6位数控衰减器。该组件集成度高、散热性好、可靠性高,较传统T/R组件在尺寸和重量上具有突破性的优势,大大减小了雷达尺寸,使其更好地满足高性能共形有源相控阵雷达的需要。     

The processing technology and electronic packaging of CVD diamond: a case study for GaAs/CVD diamond plastic packages

The demand for increased performance, increased reliability, and low cost from commercial off-the-shelf electronics technologies has increased the viability assessment efforts for a plethora of new materials targeting the electronics packaging industry. Over the last decade, a widening acceptance of CVD diamond (CVDD) as an engineered material has been due, in part, to its demonstrated performance advantages in monolithic, discrete, hybrid, and module scale electronic packaging applications. Realizing this advantage at palatable costs however requires integrating electronic packaging requirements and designs with the unique properties and processing requirements of CVDD. In this light, this case study examines pertinent CVDD properties and processing, CVDD-enhanced SOIC and QFP package assembly, and the subsequent performance/reliability results for diamond-enhanced, plastic-packaged, GaAs MESFET and PHEMT MMICs.     

Void-free Au-Sn eutectic bonding of GaAs dice and its characterization using scanning acoustic microscopy

A new technique to produce perfect bonding between GaAs dice and alumina substrates is reported. Utilizing this technique, void-free bondings have been achieved consistently. The quality of the bonded devices is confirmed by a Scanning Acoustic Microscope (SAM) having a spatial resolution of 25 μm. Thermal cycling between -25° C and 125° C, and thermal shock between -196° C and 135° C, have been used to assess the reliability of the specimens. The SAM was used to study the variation of the bonds in the tests. After the tests, the bonds show no sign of degradation and the GaAs dice did not crack. Shear test has also been performed. All the well bonded specimens passed the shear test. The shear strength correlated very well with the SAM images of the specimens taken before the test.     

电子封装失效分析新技术--双波透射SAM

介绍了在反射式SAM技术基础上开发的一种失效分析新技术－－双波诱射SAM技术的原理和应用特点。该技术依据声波在界面的反射系数R与材料声阻Z的关系，采用双程透射方法，通过人射和反射声波强度的对比分析，对界面缺陷进行定位，它是解决传统反射式SAM技术不能准确探测复杂结构界面缺陷、替代（单波）透射技术的又一新方法。     

表面镀层对封帽质量的影响

气密封装工艺技术是混合电路制造的关键技术。在可靠性要求较高的场合,对混合电路产品提出了水汽含量、漏气率和粒子碰撞噪声检测(PIND)合格率的指标要求。封装内部的多余物对电子器件的可靠性带来严重影响。主要从盒体的表面镀层方面进行讨论,分析了不同的金属化结构和不同的镀层厚度对气密封装的影响。实验表明,当封装使用的压力较大时,化学镀镍外壳的镀层容易出现裂纹,造成外壳锈蚀。外壳使用化学镀镍、电镀金结构时,其PIND不合格率较高。当镀层厚度超标时,不仅PIND不合格率较高,也会出现漏气问题。     

System on Wafer: A New Silicon Concept in SiP

System integration is clearly a driving force for innovation in packaging. The need for miniaturization has led to new architectures that combine disparate technologies and materials. Today several different approaches have been developed. These include technologies like system in package. In this way, a new concept for heterogeneous integration is currently being developed at CEA-LETI and is called system on wafer (SoW). This concept is based on a chip to wafer approach. Every component is achieved by using wafer-level technologies, and the final system is performed by single component mounting on a silicon substrate. The main strength of this approach is to use silicon as a substrate for components and for basic support. To perform the SoW, a generic technological toolbox is needed. This includes every standard packaging technology such as flip chip, signal rerouting, and passive component integration as well as new advanced technologies such as microelectromechanical systems packaging, advanced interconnections, energy source integration, integrated cooling, or silicon through vias. In this paper, the SoW concept will be presented and the generic toolbox for SoW achievement will be described.      

Advanced HiCTE flip chip packaging of 90-nm Cu/Low-K chips: Underfill,novel terminal pad structures,and processing optimization

Packaging of 90-nm Cu/Low-K chips presents a serious challenge, which requires an advanced ceramic flip chip solution. Finer Cu interconnects are expected to interact differently with the current underfill-to-die passivation stack-up structures used for Al or previous Cu technology nodes especially in system level applications. Furthermore, the more porous and brittle-proned advanced Low-K (K<3) dielectrics present additional process incompatibility problems such as stress-induced crackings and delaminations. These reliability issues in various stress-relieving passivation structures and materials (i.e., Benzocyclobutene (BCB) and single versus double SiOxNy passivations) have not been extensively studied. This study analyzes the effect of the eight metal layer 90-nm Cu/Low-K flip chip devices through designed experiments using two relatively different underfill materials, standard terminal pad and novel passivation structures, and JEDEC Level-3 reliability stressings: temperature cycling (TC), highly accelerated stress testing (HAST), and high-temperature storage (HTS). Black Diamond Low-K and HiCTE ceramic substrates are employed for the large package form factor. The active Si uses eutectic stencil-pasted SnPb bump and BGA balls with Ti/Ni-V/Al-Cu reflectory thin film-deposited under bump metallurgy (UBM). It is found that the double passivation pad structures are less susceptible to reliability damage for various types of underfills, although a single passivation with BCB coating combined with an optimal underfill can also yield a similar favorable result. The metallurgical effect of delamination cracking, HiCTE flip chip and stress-relieving passivation structures, and the underfill interface failure mode mechanism are examined by functional testing, chemical deprocessings, scanning acoustic microscope (SAM), and scanning electron microscope (SEM)/energy-dispersive x-ray (EDX). The presented results are significant for the development of flip chip packaging technologies for future advanced Cu/Low-K generations.     

A comprehensive solution for electronic packages' reliability assessment with digital image correlation (DIC) method

The reliability assessment of electronic packages demands more accurate and efficient method for evaluating heterogeneous packages and their interconnects in various measurement conditions. The digital image correlation (DIC) method has been fully developed in the last decade. With proper improvement, this work demonstrates that DIC method has the ability to fulfill various experimental tasks and obtain the information for interconnect strain analysis, coefficient of thermal expansion (CTE) characterization, in-plane displacement and out-of-plane warpage quantification within one measurement. To some extent, it serves as a comprehensive tool for electronic packages' reliability assessment. Given that the DIC technique is new to the electronic packaging area, this work illustrates the principle of optical non-contact experiment method and presents several improvements to fit for the measurement on electronic packaging area. With these applications, it is foreseeable that the DIC method will play an important role in the reliability assessment of electronic packages.     

Getters for flat-panel displays

Getters play a crucial role in solution of the main technical issues on the way to commercial exploitation of new flat-panel technologies: packaging, reliability and lifetime. The production steps of flat-panel displays (FPDs) often include a long baking and exhaust process to minimize the impurity content prior to the final sealing, which dramatically increases the manufacturing costs up to a level that might be incompatible with mass production requirements. These problems can be tackled and solved by the introduction of a specific getter device that can permanently remove the undesirable species by the formation of irreversible chemical bonds. In this paper we will focus on long-studied FPD technologies such as vacuum-fluorescent displays, field-emission displays, and plasma display panels, showing how proper getter solutions based on special metal alloys can increase their lifetime and reliability and, in particular cases, also improve the manufacturing process conditions     

晶圆级多层堆叠技术

随着5G和人工智能等新型基础设施建设的不断推进,单纯通过缩小工艺尺寸、增加单芯片面积等方式带来的系统功能和性能提升已难以适应未来发展的需求。晶圆级多层堆叠技术作为能够突破单层芯片限制的先进集成技术成为实现系统性能、带宽和功耗等方面指标提升的重要备选方案之一。对目前已有的晶圆级多层堆叠技术及其封装过程进行了详细介绍;并对封装过程中的两项关键工艺,硅通孔工艺和晶圆键合与解键合工艺进行了分析;结合实际封装工艺对晶圆级多层堆叠过程中的可靠性管理进行了论述。在集成电路由二维展开至三维的发展过程中,晶圆级多层堆叠技术将起到至关重要的作用。     

Drop impact reliability analysis of CSP packages at board and product levels through modeling approaches

Chip scale package (CSP) and fine pitch ball grid array (BGA) packages have been increasingly used in portable electronic products such as mobile cell phones and PDA, etc. Drop impact which is inevitable during its usage could cause not only housing crack but also package to board interconnect failure, such as BGA solder breaks. Various drop tests have been used to ensure high reliability performance of packaging to withstand such impact and shock load. Due to extreme difficulty in directly measuring responses in solder joint during drop shock event, computer simulation based modeling approach has been increasingly played an important role in evaluating product reliability performance during product development. An advanced modeling technique with a comprehensive failure criterion including high strain rate effect needs to be developed to quantitatively evaluate package reliability performance especially in cross comparisons between different board and system level designs. In this paper, three drop tests have been modeled, namely, bare board drop, board with fixture drop or shock, and system level phone drop. Submodeling and explicit-implicit sequential modeling techniques are used to characterize the dynamic responses of CSP/BGA packages in different board designs. Failure criteria and effects of strain rate and edge support on BGA in multicomponent boards are also investigated. A validation test with data acquisition is used to correlate the test results with numerical results.     

Enhanced solder joint bonding strength of electronic packaging with electrowetting effect

This paper reports a novel method to enhance solder ball or solder ring bonding strength by using electrowetting-on-dielectric (EWOD) effect. With a low melting point, the metal Sn has been widely used in electronic packaging technology. Since Sn will be molten into liquid when the temperature is increased above the melting point, the method for treating liquid can be herein employed. Contact angle of the molten Pb-free balls or ring structure on silicon substrate have been experimentally changed by applying electric field across the thin dielectric film between the molten solder and the conductive silicon substrate. The contact area between the solder and the substrate is enlarged due to the decrease of the contact angle. Our testing results on the EWOD enhanced packaging structures of solder balls, flip-chip and solder ring hermetic package generally show about 50% enhancement in bonding shear strength. The significantly enhanced solder link bonding strength is hopeful for improving packaging reliability and is promising to be used in high performance silicon based electronic or microelectromechanic SiP (system in package) technologies.     

功率裸芯片的质量与可靠性保证方法

论述了常规裸芯片质量与可靠性保证的标准和技术,针对功率器件裸芯片,提出了高性能和高可靠性设计、制造工艺保障、验证筛选等质量与可靠性保证方法和技术途径;讨论了采用临时封装夹具技术,对功率裸芯片进行热敏参数筛选、结温控制老化筛选、高温高压反偏筛选等,最终实现对功率裸芯片100%的筛选,满足MCM和HIC对功率裸芯片的质量与可靠性要求。     

Analysis on the difference of the characteristic between high power IGBT modules and press pack IGBTs

The insulated gate bipolar transistor (IGBT) has been widely employed in such applications as alternate current motors and inverters for its lower driving power and lower on-state voltage. IGBT modules and press pack IGBTs are the most commonly used packaging for high-voltage and high-power-density applications. The difference in the packaging style and working conditions between IGBT modules and press pack IGBTs creates distinctions in, for instance, the thermal characteristics and reliability. Those distinctions lead to different applications and working conditions. In this paper, the development of IGBT devices has been reviewed, including the distinction of IGBT modules and press pack IGBTs in packaging style. Most importantly, the thermal and reliability characteristics have been compared in detail and the applications that are most suitable for IGBT modules and press pack IGBTs were outlined. The comparison of the thermal characteristics, reliability and applications provides guidance for users to take full advantage of the devices according to their requirements.     

化学镀镍镀钯浸金表面处理工艺概述及发展前景分析

随着电子封装系统集成度逐渐升高及组装工艺多样化的发展趋势,适应无铅焊料的化学镀镍镀钯浸金（ENEPIG）表面处理工艺恰好能够满足封装基板上不同类型的元件和不同组装工艺的要求,因此ENEPIG正成为一种适用于IC封装基板和精细线路PCB的表面处理工艺。ENEPIG工艺具有增加布线密度、减小元件尺寸、装配及封装的可靠性高、成本较低等优点,近年来受到广泛关注。文章基于对化学镍钯金反应机理的简介,结合对镀层基本性能及可靠性方面的分析,综述了ENEPIG表面处理工艺的优势并探讨了其发展前景。