Distortion in single-, two- and three-stage amplifiers

Nonlinear distortion in single-, two-, and three-stage operational amplifiers (opamps) is the main scope of this paper. For each opamp, distortion contributions from different groups of transistors are identified and plotted versus frequency. This makes it possible to find the strongest sources of distortion in the various frequency regions. Further, equations that describe the third harmonic as a function of circuit parameters and input frequency are presented. Despite the simplifications, these equations describe the third harmonic accurately. Further, they provide insight and understanding by connecting distortion to circuit parameters such as transconductances, capacitances, poles, and zeros. The comparison of the opamps shows that each opamp has a frequency region where the distortion is lower than for the other two. The three-stage op amp has far lower distortion at low frequencies, the single-stage op amp is better at high frequency and the two-stage op amp is best for the mid frequency range.     

Distortion in high-frequency FET amplifiers

A high-frequency nonlinear model of FET's is developed in which all sources of nonlinearities, including the output conductance, are accounted for. The distortion resulting from this model is represented using the Volterra series approach, and a high degree of accuracy between the theory and the measured results is obtained. Although the theory holds only for circuits that exhibit a slight deviation from linearity, it is found that fairly good agreement exists at larger signal levels. Harmonic, intermodulation, and cross-modulation distortion (CMD) that occur in a typical high-frequency single-stage FET amplifier are all analyzed and experimentally verified. It is observed that the CMD that occurs in the FET under consideration is of the AM type.     

Design of CMOS three-stage amplifiers for fast-settling switched-capacitor circuits

In this paper, a time-domain design procedure for fast-settling three-stage amplifiers is presented. In the proposed design approach, the amplifier is designed to settle within a specific time with a given settling accuracy and circuit noise budget by optimizing both the power consumption and silicon die area. Both linear and nonlinear settling regions of three-stage amplifiers are considered and optimal values of the amplifier stages transconductance and compensation capacitors are obtained using the genetic algorithm optimization. Detailed design equations are provided and circuit level simulation results using a 90 nm CMOS technology are presented to evaluate the usefulness of the proposed design scheme respected to the previously reported design approaches.     

Distortion in class a transistor amplifiers

Simple equations are developed for second-harmonic distortion in class A amplifiers, and experimental confirmation is given.     

Distortion in bipolar transistor variable-gain amplifiers

Wide-band variable-gain amplifiers consisting of bipolar junction transistors and exhibiting maximum gain larger than unity are considered. The mechanisms of distortion are analyzed at low and high frequencies. Approximate expressions for distortion are derived and give good agreement with computational results and measurements. The most common high-performance variable-gain circuit realizations are discussed and compared for distortion performance.     

Distortion in RF CMOS short-channel low-noise amplifiers

An approach to estimate the distortion in CMOS short-channel (e.g. 0.18-/spl mu/m gate length) RF low-noise amplifiers (LNAs), based on Volterra's series, is presented. Compact and accurate frequency-dependent closed-form expressions describing the effects of the different transistor parameters on harmonic distortion are derived. For the first time, the second-order distortion (HD2), in CMOS short-channel based LNAs, is studied. This is crucial for systems such as homodyne receivers. Equations describing third-order intermodulation distortion in RF LNAs are reported. The analytical analysis is verified through simulations and measured results of an 0.18-/spl mu/m CMOS 5.8-GHz folded-cascode LNA prototype chip geared toward sub-1-V operation. It is shown that the distortion is independent of the gate-source capacitance C/sub gs/ of the MOS transistors, allowing an extra degree of freedom in the design of LNA circuits. Distortion-aware design guidelines for RF CMOS LNAs are provided throughout the paper.     

Hybrid cascode feedforward compensation for nano-scale low-power ultra-area-efficient three-stage amplifiers

A modified frequency compensation technique is proposed for low-power area-efficient three-stage amplifiers driving medium to large capacitive loads. Coined hybrid cascode feedforward compensation (HCFC), the total compensation capacitor is divided and shared between two internal high-speed feedback loops instead of only one loop as is common in prior art. Detailed analysis of this technique shows significant improvement in terms of bandwidth and stability. This is verified for a 1.2-V amplifier driving a 500-pF capacitive load in 90-nm CMOS technology, where HCFC reduces the total capacitor size and improves the gain-bandwidth by at least 30% and 40% respectively, compared to the prevailing schemes.     

Distortion in polar modulated CMOS RF power amplifiers

Polar modulation of a switching RF amplifier is an excellent candidate to combine both linearity, efficiency and CMOS integration for RF power amplifiers used in mobile and wireless communication systems. In this paper, the different sources of distortion associated with polar modulation are discussed and verified by measurement results. A fully integrated linearized CMOS RF Power Amplifier for GSM–EDGE, realized in a 0.18 μm CMOS technology, is used as a benchmark to validate the presented theory. It is demonstrated how the combination of a differential delay between the amplitude signal and the phase signal, together with the AM–PM distortion of the Class E amplifier, generates an asymmetry in the output spectrum. The effect of low-pass filtering of the envelope signal is investigated and the degradation on the linearity with and without delay adjustment is given.     

Distortion and noise-induced DC offset in operational amplifiers

Experimental measurements on many different commercial operational amplifiers indicate that a sizable d.c. offset voltage occurs which is a function of input signal amplitude and frequency. This offset is shown to be the result of nonlinear distortion in the input stage. A simple nonlinear model is used to analyze the effect, and calculated and experimental results are in good agreement.     

Distortion of FM modulation in injection phase-locked oscillator amplifiers

A generalized Adler's equation for the injection-locking phenomenon is presented. The method for its approximate solution is then discussed. The modulation frequency dependence of the total nonlinear and delay distortion of the FM modulation in an injection phase-locked oscillator-amplifier is presented graphically, with either peak frequency deviation or gain as a parameter.     

Hybrid cascode compensation with feedforward stage for high-speed area-efficient three-stage CMOS amplifiers

Hybrid cascode feedforward compensation (HCFC) is proposed for low-power area-efficient three stage amplifiers driving large capacitive loads. With no overhead in power or area, the total compensation capacitor is divided and shared between two internal high-speed loops instead of solely one loop as is common in prior art. Detailed analysis of HCFC shows significant improvement in terms of stability and bandwidth. This is verified for a 1.2-V amplifier driving a 500-pF capacitive load in 90-nm CMOS technology, where HCFC reduces the total capacitor size and improves the gain-bandwidth by at least 30 and 40 %, respectively, compared to the prevailing schemes.     

Active capacitor multiplier in Miller-compensated circuits

A technique is presented whereby the compensating capacitor of an internally compensated linear regulator, Miller-compensated two-stage amplifier, is effectively multiplied. Increasing the capacitance with a current-mode multiplier allows the circuit to occupy less silicon area and to more effectively drive capacitive loads. Reducing physical area requirements while producing the same or perhaps better performance is especially useful in complex systems where most, if not all, functions are integrated onto a single integrated circuit. Die area in such systems is a luxury. The increasing demand for mobile battery-operated devices is a driving force toward higher integration. The enhanced Miller-compensation technique developed in this paper helps enable higher integration while being readily applicable to any process technology, be it CMOS, bipolar, or BiCMOS. Furthermore, the technique applies, in general, to amplifier circuits in feedback configuration. Experimentally, the integrated linear regulator (fabricated in a 1-μm BiCMOS process technology) proved to be stable for a wide variety of loading conditions: load currents of up to 200 mA, equivalent series resistance of up to 3 Ω, and load capacitors ranging from 1.5 nF to 20 μE The total quiescent current flowing through the regulator was less than 30 μA during zero load-current conditions     

Closed-loop stability analysis of microwave amplifiers

A stability analysis technique of microwave amplifiers, valid for large- or small-signal regimes, is presented. The technique calculates the system poles and zeroes from a closed-loop frequency response of the circuit linearised around its steady state. The method has been applied to an S-band monolithic amplifier, detecting spurious oscillations for certain specific bias conditions and input power levels, in good agreement with measurements     

Transient analysis of erbium-doped fiber amplifiers

The transient response of an erbium-doped fiber amplifier (EDFA) pumped at 1.48 μm, taking into account the gain-saturation effects due to the amplified spontaneous emission (ASE), is studied theoretically and experimentally. The theoretical model is used to predict the gain saturation and recovery times of an EDFA and its effects to the amplification of optical pulses     

一种三阶环形压控振荡器的分析设计

This paper describes a large tuning range low phase noise voltage-controlled ring oscillator(ring VCO)based on a different cascade voltage logic delay cell with current-source load to change the current of output node.The method for optimization is presented.Furthermore,the analysis of performance of the proposed ring VCO is confirmed by the measurement results.The three-stage proposed ring VCO was fabricated in the 180-nm CMOS process of SMIC.The measurement results show that the oscillator frequency of the ring VCO is from 0.770 to5.286 GHz and the phase noise is 97.93 dBc/Hz at an offset of 1 MHz from 5.268 GHz with a total power of15.1 mW from a 1.8 V supply while occupying only 0.00175 mm2of the core die area.     

双光束耦合三级相干光放大的理论分析

基于双光束耦合的原理提出了三级相干光放大的方法,这不仅能使3块低质量晶体取得一块高质量晶体所能达到的效果,而且解决了单级放大难以大幅度提高放大倍数的问题,理论分析表明所提方法是可行的。     

Detailed design analysis of erbium-doped fiber amplifiers

When pumping the erbium-doped fiber amplifier at 0.98 and 1.48 mu m, the optimum cutoff wavelength for step profiles with arbitrary numerical aperture is shown to be 0.80 and 0.90 mu m, respectively. The use of a confined erbium profile can improve the gain coefficient up to 45%. The index raising co-dopant is shown to be very significant for the gain coefficient when pumping at 0.98 mu m.<>     

Large-signal capabilities and analysis of distributed amplifiers

In the letter experimental results are presented which show that distributed amplifiers can be used for power applications. These results are verified by comparing an analytic model predicted using SPICE 2 simulation with measurements between 0.3 and 12 GHz. It appears that a very broad band can be achieved and that the distributed amplifiers keep their self matching properties even under large-signal operation. Distributed-amplifier characteristics, under small-signal operations, are now well known.1?4 However, recent improvements in GaAs FET technology have created new prospects in large-signal and high-frequency conditions. To our knowledge, although some experimental results have been published3, no theoretical study has been carried out for large-signal conditions. The letter provides such a study.