Flexible integration of MEMS and IC for low-cost production of wireless sensor nodes

In this paper, we proposed a flexible process for size-free MEMS and IC integration with high efficiency for MEMS ubiquitous applications in wireless sensor network. In this approach, MEMS and IC can be fabricated individually by different wafers. MEMS and IC known-good-dies (KGD) are temporarily bonded onto carrier wafer with rapid and high-accurate self-alignment by using fine pattern of hydrophobic surface assembled monolayer and capillary force of H₂O; and then KGD are de-bonded from carrier wafer and transferred to target wafer by wafer level permanent bonding with plasma surface activation to reduce bonding temperature and load force. By applying above 2-step process, size of both wafer and chip could be flexible selected. Besides, CMOS processed wafer or silicon interposer can be used as the target wafer. This approach offers us excellent process flexibilities for low-cost production of wireless sensor nodes.     

Direct bonding with on-wafer metal interconnections

A low temperature direct bonding process with encapsulated metal interconnections was proposed. The process can be realized between silicon wafers or silicon and glass wafers. To establish well-insulated electric connection, sputtered aluminum film was patterned between a bottom thermal SiO₂ and a top PE-SiO₂; the consequential uneven wafer surface was planarized through a chemical mechanical polishing (CMP) step. Benefit from this smooth surface finish, direct bonding is achieved at room temperature, and a general yielding rate of more than 95% is obtained. Test results confirmed the reliability of the bonding. The main advantages of this new technology are its electric connectivity, low thermal stress and hermeticity. This process can be utilized for the packaging of micro electro mechanical system (MEMS) devices or the production of SOI wafers with pre-fabricated electrodes and wires.     

Wafer-level bonding and direct electrical interconnection of stacked 3D MEMS by a hybrid low temperature process

The presented fabrication technology enables the direct integration of electrical interconnects during low temperature wafer bonding of stacked 3D MEMS and wafer-level packaging. The low temperature fabrication process is based on hydrophilic direct bonding of plasma activated Si/SiO₂ surfaces and the simultaneous interconnection of two metallization layers by eutectic bonding of ultra-thin AuSn connects. This hybrid wafer-level bonding and interconnection technology allows for the integration of metal interconnects and multiple materials in stacked MEMS devices. The process flow is successfully validated by fabricating test structures made out of a two wafer stack and featuring multiple ohmic electrical interconnects.     

Gold metallizations for eutectic bonding of silicon wafers

Gold eutectic bonding of silicon wafers is a good candidate for wafer level vacuum packaging of vibrating MEMS: in this paper we investigated several e-beam evaporated metallizations stacks including a titanium adhesion layer, an optional diffusion barrier (Ni or Pt) and a gold film for eutectic bonding on Si and SiO₂/Si wafers. Interdiffusion in the multilayers for annealing temperatures (380–430°C) larger than the Au–Si eutectic temperature (363°C) and times corresponding to a bonding process was characterized by RBS, roughness and resistivity measurements. Au/Pt/Ti and Au/Ti/SiO₂ were found to have the best characteristics for bonding. This was confirmed by bonding experiments.

     

Gold metallizations for eutectic bonding of silicon wafers

Gold eutectic bonding of silicon wafers is a good candidate for wafer level vacuum packaging of vibrating MEMS: in this paper we investigated several e-beam evaporated metallizations stacks including a titanium adhesion layer, an optional diffusion barrier (Ni or Pt) and a gold film for eutectic bonding on Si and SiO₂/Si wafers. Interdiffusion in the multilayers for annealing temperatures (380–430°C) larger than the Au–Si eutectic temperature (363°C) and times corresponding to a bonding process was characterized by RBS, roughness and resistivity measurements. Au/Pt/Ti and Au/Ti/SiO₂ were found to have the best characteristics for bonding. This was confirmed by bonding experiments.     

Wafer direct bonding with ambient pressure plasma activation

Ambient pressure plasma processes were applied for surface activation of semiconductor (Si, Ge and GaAs) and other wafers (glass) before direct wafer bonding for MEMS and engineered substrates. Surface properties of activated wafers were analysed. Caused by activation high bond energies were obtained for homogeneous (e.g. Si/Si) as well as for heterogeneous material combinations (for instance Si/Ge) after a subsequent low temperature annealing process at 200°C. The resulting bond energies are analogous or higher as obtained for low-pressure plasma activation processes. The advantages of the ambient pressure plasma processes are described; a technical solution is discussed demonstrating the low risk for contamination and radiation damage.     

Versatile low temperature wafer bonding and bond strength measurement by a blister test method

We present a low temperature plasma assisted bonding process that enables the bonding of silicon, silicon oxide and silicon nitride wafers among each other at annealing temperatures as low as room temperature. The process can be applied using standard clean room equipment. Surface energies of differently treated bonded samples are determined by a blister test method for square shaped cavities. For this reason, we extend the well-known blister test method for round shaped cavities to the square shaped case by a combined analytical and numerical approach. Accordingly, the energetic favored crack front propagation in the bond interface is determined by numerical simulations. The surface energies of the tested samples are calculated and compared to anodic silicon-to-Pyrex^® bonds. Surface energies of up to 2.6 J/m² can be achieved between silicon and silicon oxide wafer pairs at low annealing temperatures. Room temperature bonded samples show a surface energy of 1.9 J/m². The surface energy of silicon-to-Pyrex glass bonds yields 1.3 J/m². Small structures, e.g., bridges down to 5 μm can be bonded using the discussed bonding process. Selective bonding of silicon-to-silicon oxide wafer pairs is performed by structuring the oxide layer. The successful integration of the bonding process into the fabrication of micropumps is highlighted.     

Discussion of tooling solutions for the direct bonding of silicon wafers

Silicon-to-silicon fusion (or direct) pre-bonding is an important enabling technology for many emerging microelectronics and MEMS technologies. A silicon–silicon direct bond can be easily formed, where the wafer surfaces are highly flat and very clean (Tong and Gosele), however for practical structured MEMS devices, wafer bow and local roughness may be compromised such that it is no longer a trivial task to achieve a direct bond. Tooling has been developed to facilitate the in situ alignment and bonding of silicon-to-silicon wafers in a vacuum chamber. The rate and direction of the bond propagation are controlled, thus minimising the occurrence of non-particle related voids. The tooling system also allows wafers with “non-ideal” surfaces or warped profiles to be bonded, by maximising the area across which bonding occurs and providing in situ annealing. The ability to anneal the wafers while maintaining clamping force creates attractive forces high enough to overcome the mechanical repulsive forces between the wafers and maintain a permanent bond. The tooling system can also be configured to give control over the bow or residual stress in the bonded pair, a factor that is critical in multi-stack direct wafer bonding.     

Characterization of intermediate In/Ag layers of low temperature fluxless solder based wafer bonding for MEMS packaging

Low temperature fluxless solder for wafer bonding has received a lot of attention due to its great potential in hermetic MEMS packaging. Previous research activities mainly deploy solder alloy of eutectic composition to achieve low bonding temperature. We proposed new intermediate bonding layers (IBLs) of rich Ag composition in In–Ag materials systems. In this study, we investigated the intermetallic compounds (IMCs) at the bonding interface with respect to the bonding condition, post-bonding room temperature storage and post-bonding heat treatment. With this IBL, the IMCs of Ag₂In and Ag₉In₄ with high temperature resist to post-bonding process are derived under process condition of wafer bonding at 180 °C, 40 min and subsequent 120–130 °C annealing for 24 h. Low melting temperature IMC phase of AgIn₂ is formed in the interface after long term room temperature storage or 70 °C aging treatment. This low melting temperature IMC phase can be completely converted into high melting temperature IMCs of Ag₂In and Ag₉In₄ after 120 °C additional annealing. Based on our results, we can design the packaging process flow so as to get reliable hermetic packaged MEMS devices by using low temperature fluxless In–Ag wafer bonding.     

Effect of interfacial SiO2 thickness for low temperature O2 plasma activated wafer bonding

It was experimentally demonstrated that bonding strength strongly depends on the total SiO₂ thickness near the bonding interface for a given O₂ plasma surface activation. Systematic experiments of Si/SiO₂ and SiO₂/SiO₂ wafer bonding are performed for analyzing the evolution of the bonding surface energy with the interfacial oxide thickness. Optimum plasma exposure time increases with the interfacial SiO₂ thickness to achieve the maximum bonding strength in SiO₂/SiO₂ or SiO₂/Si. An optimal process option for plasma activated SiO₂/SiO₂ wafer bonding is proposed.     

CMOS: compatible wafer bonding for MEMS and wafer-level 3D integration

Wafer bonding became during past decade an important technology for MEMS manufacturing and wafer-level 3D integration applications. The increased complexity of the MEMS devices brings new challenges to the processing techniques. In MEMS manufacturing wafer bonding can be used for integration of the electronic components (e.g. CMOS circuitries) with the mechanical (e.g. resonators) or optical components (e.g. waveguides, mirrors) in a single, wafer-level process step. However, wafer bonding with CMOS wafers brings additional challenges due to very strict requirements in terms of process temperature and contamination. These challenges were identified and wafer bonding process solutions will be presented illustrated with examples.     

Wafer-level plasma activated bonding: new technology for MEMS fabrication

Manufacturing and integration of MEMS devices by wafer bonding often lead to problems generated by thermal properties of materials. These include alignment shifts, substrate warping and thin film stress. By limiting the thermal processing temperatures, thermal expansion differences between materials can be minimized in order to achieve stress-free, aligned substrates without warpage. Achieving wafer level bonding at low temperature employs a little magic and requires new technology development. The cornerstone of low temperature bonding is plasma activation. The plasma is chosen to compliment existing interface conditions and can result in conductive or insulating interfaces. A wide range of materials including semiconductors, glasses, quartz and even plastics respond favorably to plasma activated bonding. The annealing temperatures required to create permanent bonds are typically ranging from room temperature to 400°C for process times ranging from 15–30 min and up to 2–3 h. This new technique enables integration of various materials combinations coming from different production lines.     

Wafer bonding with nano-imprint resists as sacrificial adhesive for fabrication of silicon-on-integrated-circuit (SOIC) wafers in 3D integration of MEMS and ICs

In this paper, we present the use of thermosetting nano-imprint resists in adhesive wafer bonding. The presented wafer bonding process is suitable for heterogeneous three-dimensional (3D) integration of microelectromechanical systems (MEMS) and integrated circuits (ICs). Detailed adhesive bonding process parameters are presented to achieve void-free, well-defined and uniform wafer bonding interfaces. Experiments have been performed to optimize the thickness control and uniformity of the nano-imprint resist layer in between the bonded wafers. In contrast to established polymer adhesives such as, e.g., BCB, nano-imprint resists as adhesives for wafer-to-wafer bonding are specifically suitable if the adhesive is intended as sacrificial material. This is often the case, e.g., in fabrication of silicon-on-integrated-circuit (SOIC) wafers for 3D integration of MEMS membrane structures on top of IC wafers. Such IC integrated MEMS includes, e.g., micro-mirror arrays, infrared bolometer arrays, resonators, capacitive inertial sensors, pressure sensors and microphones.     

Surface plasma treatments enabling low temperature direct bonding

Plasma activations for wafer bonding have been investigated for their ability to induce strong bonding even at low temperature treatment. Generally occurring with plasma treatment, revelation of many bonding defects (e.g. bubbles, voids,...) during (200–500°C) low temperature annealing is an important issue. In this paper, we will focus on bonding energy and quality enhancement obtained after reactive ion etch or microwave plasma treatment, under various atmospheres. Effects of a short plasma treatment on Si and SiO₂ surfaces are highlighted hereafter. Low-density layers around bonding interfaces have been characterized by interfacial X-ray reflectivity. Evolution of these layers through subsequent annealing are discussed to help in understanding mechanisms involved through such plasma treatments.     

A new approach for handling and transferring of thin semiconductor materials

 Based on the fracture mechanics analysis of crack propagation, the phenomenon of subcritical crack growth was utilized for a controlled debonding of directly wafer-bonded interfaces. The approach allowed the well-defined separation of bonded wafers although the bond strength was high due to thermal annealing. The achieved splitting velocity depended on the wafer material, the wafer thickness ratio, the bonding process parameters, and the environmental conditions during cleaving. In combination with wafer bonding, the method can be used for a temporary stiffening and handling of thin and brittle wafers during fabrication, even if the wafers are exposed to high process temperatures. The approach can also be applied to fabricate micromechanical systems (MEMS). Received: 12 July 2001/Accepted: 26 February 2002 This paper was presented at the Conference of Micro System Technologies 2001 in March 2001.     

Microrivets for MEMS packaging: concept, fabrication, and strengthtesting

Microriveting is introduced as a novel and alternative joining technique to package MEMS devices. In contrast to the existing methods, mostly surface bonding, the reported technique joins two wafer pieces together by riveting, a mechanical joining means. Advantages include wafer joining at room temperature and low voltage, and relaxed requirements for surface preparation. The microrivets, which hold a cap-base wafer pair together, are formed by filling rivet holes through electroplating. The cap wafer has a recess to house the MEMS devices and also has through-holes to serve as rivet molds. The seed layer on the base wafer becomes the base of the rivet. The process requires only simple mechanical clamping of the wafer pair during riveting, compared with the more involved procedures needed for wafer bonding. Directionality of electroplating in an electric field is what makes this process simple and robust. Strength testing is carried out to evaluate the joining with microrivets. Different modes of rivet failure under different loading conditions are identified and investigated. Effective strength between 7 and 11 MPa was measured under normal loading with nickel microrivets. Joining strengths comparable to conventional wafer bonding processes, ease of fabrication with repeatability, and compatibility with batch fabrication show that microriveting is a feasible technique to join wafers for MEMS packaging, especially when hermetic sealing is not essential     

Low-temperature wafer bonding: a study of void formation and influence on bonding strength

The void formation has been systematically observed for low-temperature (120/spl deg/C and 400/spl deg/C) Si-Si and SiO/sub 2/-SiO/sub 2/ wafer bonding techniques in function of the annealing time (from 70 to 595 h), pressure (low vacuum and atmospheric) and surface pretreatments. Mixed solution (H/sub 2/SO/sub 4/ and H/sub 2/O/sub 2/) standard cleaning, warm nitric acid and O/sub 2/-plasma-assisted surface pretreatments have been considered and compared. The void formation is clarified according to the void distribution and the measurement of surface energy. Long annealing time periods are considered in order to reach the saturation of the interface chemical reactions. Our experiments demonstrate that the origin of voids appearing in low temperature O/sub 2/-plasma-enhanced wafer bonding is related to the great quantity of chemical reaction products. It has been shown that optimized O/sub 2/-plasma pretreatment time can lead to void-free, uniform and high surface energy (over 2.0 J/m/sup 2/) wafer bonding. In the case of SiO/sub 2/-SiO/sub 2/ wafer bonding, our experimental results show that below a certain critical silicon dioxide thickness the reaction products cannot be absorbed totally and then voids occur. Presenting a higher surface energy than warm nitric acid O/sub 2/-plasma is an extremely promising surface pretreatment solution for the increasing demand of low-temperature wafer bonding techniques.     

硅片键合界面的应力研究

本文主要研究硅片直接键合界面结构与应力大小.当抛光硅片直接键合时,界面出现极薄的过渡区,并存在微小的晶向差,但不引起多余应力.当热生长了二氧化硅层的硅片相键合时,界面存在二氧化硅层,并引起张应力,其大小与硅二氧化硅系统应力大小相当.     

Etching processes for High Aspect Ratio Micro Systems Technology (HARMST)

 This paper reports on the development of a dry etching based HARMS-Technology which will offer the potential to manufacture micro-engines, micro-turbines, micro-sensors, micro-actuators, and electronic circuits onto a single silicon IC chip. This technology is based on the highly anisotropic and selective dry etching of Si-monocrystals. The suitability of reactive ion etching for the fabrication of micro electro mechanical systems (MEMS) has been evaluated by characterising the change of lateral dimensions vs. depth in etching deep structures in silicon. Fluorine, chlorine and bromine containing gases have provided the basis for this investigation. A conventional planar RIE (Reactive Ion Etching) reactor has been used, in some cases with magnetic field enhancement or ICP (Inductive Coupled Plasma) Source and low substrate temperature. For reactive ion etching based on Cl₂ or Cl₂/HBr plasma a slightly “positive” (top wider than bottom) slope is achieved when etching structures with a depth of several 10 μm, whereas a “negative” slope is obtained when etching with an SF₆/CCl₂F₂ based plasma. Pattern transfer with vertical walls is obtained for reactive ion etching based on SF₆ (with O₂ added) when maintaining the substrate at low temperature (in range ≈−100 °C). Further optimisation of plasma chemistries and reactive ion etching procedures should result in runouts in the order or 0.1 μm/100 μm depth in Si as well as in organic materials. Etching processes for HARMST is demonstrated in the realisation in Si microturbine. Axes or stators (nonmoving parts) are etched into the initial Si-wafer. The movable parts (rotors, beams, etc.) are prepared from electro-chemically etched Si-membranes with defined thicknesses that, all movable parts are created lithographically on the SiN_xO_y surface. This is followed by dry etching the mono-crystalline Si-membrane down to the SiN_xO_y sacrificial layer on the back side of the membrane by an RIE-process. The wafer with the movable parts is flipped onto the wafer with the already etched axis and then positioned and centred. The SiN_xO_y-sacrificial layer is then dissolved by a chemical wet or vapour etch process. Subsequent bonding with a Pyrex glass wafer seals the parts. Received: 30 October 1995/Accepted: 20 May 1996