基于FPGA乘法器架构的RNS与有符号二进制量转换

RNS(余数数制系统)是一种整数运算系统,在粒度精确性,能源损耗和响应速度上有很大的优势.从RNS到二进制数的输入输出转换是基于余数算法的专用架构实现的关键.本文提出了一个基于N类模的RNS与有符号二进制量的通用转换算法在FPGAs的乘法器上的实现过程.该算法能更有效地进行有符号数与RNS的转换.基于该算法类型乘法器在同类型乘法器中显示出了速度优势.文章中该架构被映射到Altera的10K系列的FPGA上.     

On reverse converters for arbitrary multi-moduli RNS

In this paper, we propose a new design of reverse converters for residue number systems with arbitrary moduli sets consisting of any number of odd moduli and one even modulus of the type 2^k. The new converters are arithmetic-based designs, that may be implemented using only arithmetic components without any read-only memories nor lookup tables. We tackle the problem of large modular reduction imposed by the properties of Chinese Remainder Theorem (CRT) employed in our method by calculating small correction factor in parallel with weighted sum of CRT in a set of constant multipliers followed by one two-operand modulo adder. Synthesis results show delay reduction over existing designs of up to 39.23% with area reductions of up to 28.48%.     

双云安全计算架构

针对现有安全技术对云计算数据外包保护的不足,提出一个可以应用于不可信商业云环境的数据外包计算和存储双云安全框架,用户通过一个可信任的云(可以是一个私有云或是通过多个安全硬件模块建立的云)来通信,可信的云加密并校验不可信云中存储的数据以及执行的操作。通过分离计算,把可信的云用来处理对时间不敏感的安全设置操作,同时用商业不可信云来处理大量的计算,从而实现安全的云计算数据外包。     

An Efficient Scalable RNS Architecture for Large Dynamic Ranges

This paper proposes an efficient scalable Residue Number System (RNS) architecture supporting moduli sets with an arbitrary number of channels, allowing to achieve larger dynamic range and a higher level of parallelism. The proposed architecture allows the forward and reverse RNS conversion, by reusing the arithmetic channel units. The arithmetic operations supported at the channel level include addition, subtraction, and multiplication with accumulation capability. For the reverse conversion two algorithms are considered, one based on the Chinese Remainder Theorem and the other one on Mixed-Radix-Conversion, leading to implementations optimized for delay and required circuit area. With the proposed architecture a complete and compact RNS platform is achieved . Experimental results suggest gains of 17 % in the delay in the arithmetic operations, with an area reduction of 23 % regarding the RNS state of the art. When compared with a binary system the proposed architecture allows to perform the same computation 20 times faster alongside with only 10 % of the circuit area resources.     

Chaotic Oscillators Derived from Sinusoidal Oscillators Based on the Current Feedback Op Amp

A collection of novel chaotic oscillators displaying behavior similar to that of the chaotic Colpitts oscillator and requiring the same number and type of energy storage elements is proposed. The oscillators use as an active element the current feedback op amp (CFOA) mostly employed as a current negative impedance converter (INIC). Nonlinearity is introduced through a two-terminal voltage-controlled nonlinear device with an antisymmetric driving-point characteristic. The chaos generators are designed based on sinusoidal oscillators that have been modified for chaos in a semi-systematic manner. By using CFOAs, several attractive features are attained, in particular suitability for high frequency operation. Systems of third- and fourth-order ordinary differential equations describing the chaotic behaviors are derived. Experimental results, PSpice circuit simulations and numerical simulations of the derived mathematical models are included.     

余数系统在软件无线电中的应用

余数系统由于其良好的并行特性,在乘加密集型的数字信号处理系统中得到了广泛关注,而这正是构建软件无线电系统的关键所在.本文在介绍RNS基本理论的基础上,结合已有的研究成果.指出了基于RNS的数字信号处理系统关键单元及研究现状,并提出了一种基于RNS数值表征系统的DSP系统结构.结合冗余RNS的容错特性和并行性,介绍了一种基于RNS的多路并行正交通信系统,并指出了其在阵列SDR平台和航天级SDR平台设计中的应用.可以预见,在构建未来复杂SDR系统中,RNS将得到广泛应用.     

一种高效模（2n-2p）乘法器的设计

结合两类修正方法,提出了一种高效的模（2n -2p ）乘法器（n≥2 p）的实现方法。与文献[1]中设计比较,本文乘法器结构上少了一级加法,并且综合结果也显示平均面积和延迟分别有10％和13％的减小。     

基于RNS算法的高阶FIR滤波器设计

以{2n－1,2n,2n+1,2ⁿ－¹－1,2ⁿ⁺¹－1}为余数基,在余数系统(RNS)的基础上设计了一种128抽头有限脉冲响应(FIR)滤波器。针对大位宽输入,利用基于华莱士(Wallace)树结构的纯组合逻辑电路,实现了二进制到余数的转换。相较于一般抽头中乘法器级联加法器的结构,设计的乘累加(MAC)单元将加法运算合并到部分积求和中,减少了一级模加法器,使得电路延时进一步减少。此外,通过对进位保留加法器(CSA)的中间结果取模,避免了加法运算引起的位宽增加,从而降低了整个运算的复杂度。电路在FPGA上设计实现。实验结果表明,该滤波器的延时为3.55 ns,功耗为2 585 mW,消耗的硬件资源明显降低。     

Design for Test of Crystal Oscillators: A Case Study

A feasibility study of design-for-testability (DFT) of a voltagecontrolled crystal oscillator with built-in MOS switches to increase itsobservability and controllability is presented. The primary aim was toassess to what extent the operation of the circuit is changed when theswitches are introduced. The possibility of non-destructive localization offaulty components in the provided test modes and the temperature/frequencycharacteristics measurements are briefly described. Finally, on the basis ofthe presented experimental work, a design-for-test procedure for crystaloscillator circuits is summarized. The work was performed in a developmentphase of a voltage controlled temperature compensated crystaloscillator.     

一种超混沌保密通信方案与数字信号处理器实现

提出了一种基于振荡器耦合实现超混沌保密通信的新方案。在两个RC振荡器耦合产生超混沌信号基础上,构建一个包括信息在内的非线性耦合环路,实现对信息的加密与解密。对其混沌动力学行为进行了分析,包括分岔和最大Lyapunov指数。利用数字化处理技术,对连续时间系统作离散化处理和变量比例扩张变换,最后给出了用数字信号处理器来实现该方案的设计原理与硬件实现结果。     

注频锁相振荡器阵列的低相位噪声信号产生方法

提出了注频锁相振荡器阵列的拓扑结构及相位噪声模型,根据该模型简要推导了注频锁相振荡器阵列相位噪声的计算公式并对整个阵列的相位噪声进行了分析,完成了1×4单元注频锁相振荡器阵列相位噪声的测试,测试结果与理论分析吻合,最终得出了注频锁相振荡器阵列的低相位噪声信号产生方法。     

弹箭引信X波段传输线谐振无匹配振荡器

基于砷化镓场效应晶体管(GaAs FET),设计了一种低成本、结构简单的X波段振荡器。以一段传输线实现谐振网络,通过优化反馈元件及传输线电长度,实现振荡器输出无匹配设计。室温、高温、低温环境下实测振荡频率分别为9.314GHz、9.305GHz及9.323GHz;对应输出功率分别为10.26dBm、9.21dBm及11.35dBm。振荡器性能稳定,可应用于弹箭无线电引信中。     

RNS与Delta-Sigma编码的位数据流的数值转换算法及硬件实现

利用RNS(余数数制系统)可以执行并行的数据处理以及实现快速无进位算法,在VLSI(超大规模集成电路)设计中表现出低功耗、占用面积小和时延少等优良特性.根据中国剩余定理,基于(2n-1)2n(2n+1)模组,利用Verilog语言设计了RNS到位数据流的数值转换接口电路.以使传统的多位数(Bit)的复杂运算转化为多个并行的较少位数的简单运算,从而降低单次运算的复杂度、时延和功耗.该转换电路面向"Σ-Δ"编码的数据流,不同于传统的二进制数据转换,可以方便地与基于DSD(Direct Stream Digital)的Delta-Sigma系统进行无缝连接.     

New Sinusoidal Oscillators with Fully Uncoupled Control of Oscillation Frequency and Condition Using Three CCII+s

Using Sedra-Smith gyrator (IEEE Transactions on Circuit Theory 17, pp. 132–134, 1970) new realizations for grounded-resistor controlled sinusoidal oscillators using the plus-type second-generation current-conveyor (CCII+) can be systemically derived. Some of the new circuits enjoy the attractive feature of totally uncoupled frequency and condition of oscillation. Experimental and simulation results obtained using PSPICE are included.     

Integrating IPsec within OpenFlow Architecture for Secure Group Communication

Network securityprotocolssuch as IPsechave been used for many years to ensure robust end-to-end communication and are impor-tant in the context of SDN.Despite the widespread installation of IPsec to date,per-packet protection offered by the protocol isnot very compatible with OpenFlow and flow-like behavior.OpenFlow architecture cannot aggregate IPsec-ESP flows in transportmode or tunnel mode because layer-3 information is encrypted and therefore unreadable.In this paper,we propose using the Secu-rity Parameter Index(SPI)of IPsec within the OpenFlow architecture to identify and direct IPsec flows.Thisenables IPsec to con-form to the packet-based behavior of OpenFlow architecture.In addition,by distinguishing between IPsec flows,the architectureis particularly suited to secure group communication.     

A Flexible Architecture for Modular Arithmetic Hardware Accelerators based on RNS

Modular arithmetic is a building block for a variety of applications potentially supported on embedded systems. An approach to turn modular arithmetic more efficient is to identify algorithmic modifications that would enhance the parallelization of the target arithmetic in order to exploit the properties of parallel devices and platforms. The Residue Number System (RNS) introduces data-level parallelism, enabling the parallelization even for algorithms based on modular arithmetic with several data dependencies. However, the mapping of generic algorithms to full RNS-based implementations can be complex and the utilization of suitable hardware architectures that are scalable and adaptable to different demands is required. This paper proposes and discusses an architecture with scalability features for the parallel implementation of algorithms relying on modular arithmetic fully supported by the Residue Number System (RNS). The systematic mapping of a generic modular arithmetic algorithm to the architecture is presented. It can be applied as a high level synthesis step for an Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA) design flow targeting modular arithmetic algorithms. An implementation with the Xilinx Virtex 4 and Altera Stratix II Field Programmable Gate Array (FPGA) technologies of the modular exponentiation and Elliptic Curve (EC) point multiplication, used in the Rivest-Shamir-Adleman (RSA) and (EC) cryptographic algorithms, suggests latency results in the same order of magnitude of the fastest hardware implementations of these operations known to date.     

用改进的非线性电流源法分析微波振荡器的稳态响应

本文提出用改进的非线性电流源法和振荡器的振荡条件相结合,进行微波FET振荡器非线性分析的方法.非线性电流源法已经被证明为分析微波振荡器的一种行之有效的方法.但是,当电路中含有多维非线性元件时(例如FET中的I_(d5)(V_(g5),V_(d5)),以往的非线性电流源法就显得无能为力.在此,我们将对非线性电流源法进行改进,并将它运用到微波FET振荡器的非线性分析中.改进的非线性电流源法能够有效地处理含有多维非线性元件电路的分析问题,从而大大提高了非线性电流源法的分析能力和实用性,扩大了其应用范围.     

量子通信原理及进展概述

近年来,量子通信作为量子信息处理研究的一个主要方向,受到了越来越多的关注。量子通信是通过将比特信息编码在单光子等物理体系上进行通信的通信过程,理论证明任何窃听行为都会对量子通信的结果造成影响,从而保证了量子通信的绝对安全性。主要介绍了基本的量子密钥分配和量子安全直接通信方案的原理和几个具有代表性的方案,并介绍了量子通信实验研究的历史和现状。     

An Electronically Tunable Sinusoidal Oscillator Suitable for High Frequencies Operation Based on a Single Dual-Output Variable-Gain CCII

A novel sinusoidal oscillator, constructed from only one CCII with variable current gain, is presented and analyzed. The oscillator provides electronically tunable frequency, with good stability and low sensitivities, while variation of current gain does not affect the condition of oscillations. By the proposed circuit topology, the parasitic elements which exist at current conveyor terminals are absorbed by the external components and their action is diminished. Moreover, the parasitic poles of the current conveyor are taken into account and compensation technique and design criteria are applied, so that the oscillator can operate above 35 MHz.     

三点式LC振荡器振幅起振条件的简单推导方法

介绍一种物理概念明确，易于学生掌握的三点式振荡器振幅起振条件的简单推导方法。