SiC肖特基栅JFET功率特性的研究

提出了一种新型结构的SiC结型场效应晶体管,采用肖特基接触替代P+型栅区,以降低SiC JFET的工艺复杂度,并提高器件的功率特性。建立了器件的数值模型,对不同材料和结构参数下的功率特性进行了仿真。结果表明,与PN结栅相比,肖特基栅结构可以有效降低SiC JFET的开态电阻;与常规结构的双极模式SiC JFET相比,在SiC肖特基栅JFET的栅极正偏注入载流子,同样可以有效降低器件的开态电阻,折中器件的正反向特性,但不会延长开关时间。     

SiC MESFET中Ti/Pt/Au肖特基接触稳定性的研究

SiC是一种在高功率和高温应用中涌现的非常重要的半导体材料.研究了一种国产Sic MESFET 器件300℃温度应力下,存储1 000 h Ti/Pt/Au栅肖特基势垒接触的稳定性以及器件电学特性的变化.实验结果表明在300℃温度应力下,器件的最大饱和漏电流、势垒高度、阈值电压和跨导等参数均呈现明显的下降趋势,在实验前期一段时间内退化较快,而在应力后期某段时间内为渐变并趋于稳定.     

自对准栅金刚石MESFET器件研究

基于表面氢化处理的金刚石材料,利用自对准栅工艺技术研制了p型金刚石肖特基栅场效应晶体管(MESFET)。利用AFM和Raman测试方法对材料的特性进行了测试及分析。同时,对研制的金刚石MESFET器件进行了TLM以及直流特性测试及性能分析。利用TLM方法测试获得的表面氢化处理金刚石材料的方阻和Au欧姆接触比接触电阻率分别为4kΩ/□和5.24×10-4Ω.cm2。研制的1μm栅长金刚石MESFET器件的最大电流在-5V偏压下达到10mA/mm以上。     

MESFET肖特基势垒结参数提取及I-V曲线拟合

运用双指数函数模型方法分析了影响 MESFET的 Ti Pt Au-Ga As肖特基势垒结特性的各种因素及各因素间的关系 ,编制了 MESFET肖特基势垒结结参数提取和 I-V曲线拟合软件 ,实现了通过栅源正向 I-V实验数据提取反映肖特基势垒结特性的六个结参数和得到相应结参数下的理论数据 ,与实验数据吻合良好。分析了影响肖特基势垒结 I-V曲线分布的因素 ,提出了进行器件特性、参数稳定性与可靠性研究和定量分析 MESFET肖特基势垒结质量的新方法     

4H-SiC MESFET肖特基栅接触的界面参数提取

研究了界面态对4H-SiC MESFET的肖特基栅接触的影响.栅接触工艺主要采用Ti/Pt/Au蒸发,经过剥离后形成.基于热电子理论提出了一种参数提取方法,得到界面态密度和界面电容分别为4.386×1013cm-2·eV-1和8.394×10-6F/cm2,这与测量得到的器件端特性一致.     

4H-SiC MESFET肖特基栅接触的界面参数提取

研究了界面态对4H-SiC MESFET的肖特基栅接触的影响.栅接触工艺主要采用Ti/Pt/Au蒸发,经过剥离后形成.基于热电子理论提出了一种参数提取方法,得到界面态密度和界面电容分别为4.386×1013cm-2·eV-1和8.394×10-6F/cm2,这与测量得到的器件端特性一致.     

GaAs MESFET在18MΩ·cm水中的退化

业已证明:在光照下,GaAs MESFET在18MΩ·cm的水中漂洗会导致器件直流特性的迅速退化。水在肖特基势垒栅电极的周围腐蚀出一个槽,其腐蚀速率至少为22 /min。槽的形成明显地增加了MESFET的寄生电阻。     

变温C-V和传输线模型测量研究AlGaN/GaN HEMT温度特性

通过对异质结材料上制作的肖特基结构变温C-V测量和传输线模型变温测量,研究了蓝宝石衬底AlGaN/GaN异质结高电子迁移率晶体管的直流特性在25～200℃之间的变化,分析了载流子浓度分布、沟道方块电阻、欧姆比接触电阻和缓冲层泄漏电流随温度的变化规律.得出了器件饱和电流随温度升高而下降主要由输运特性退化造成,沟道泄漏电流随温度的变化主要由栅泄漏电流引起的结论.同时,证明了GaN缓冲层漏电不是导致器件退化的主要原因.     

变温C-V和传输线模型测量研究AlGaN/GaN HEMT温度特性

通过对异质结材料上制作的肖特基结构变温C-V测量和传输线模型变温测量,研究了蓝宝石衬底AlGaN/GaN异质结高电子迁移率晶体管的直流特性在25～200℃之间的变化,分析了载流子浓度分布、沟道方块电阻、欧姆比接触电阻和缓冲层泄漏电流随温度的变化规律.得出了器件饱和电流随温度升高而下降主要由输运特性退化造成,沟道泄漏电流随温度的变化主要由栅泄漏电流引起的结论.同时,证明了GaN缓冲层漏电不是导致器件退化的主要原因.     

4H-SiC MESFET与SBD中子辐照效应的研究

本文研究了4H-SiC MESFET与Ni,Ti/4H-SiC SBD的中子辐照效应,中子归一化能量为1MeV,最高中子注量和gamma射线累积总剂量分别为1×1015n/cm2和3.3Mrad(Si)。经过1×1013n/cm2的辐照剂量后, SiC MESFET的电学特性仅有轻微的变化,Ni、Ti/4H-SiC以及SiC MESFET栅极肖特基接触的 都没有明显变化;随着辐照中子注量的进一步上升,SiC MESFET的漏极电流下降,夹断电压上升。辐照剂量达到1×1014n/cm2,夹断电压从辐照前的-12.5V上升为约-11.5V。当中子辐照注量达到2.5×1014n/cm2时,SiC MESFET栅极肖特基接触的 比辐照前有一定的下降。分析认为SiC MESFET和SBD的退化主要是由中子辐照引入的体材料损伤造成的。本文的研究表明,提高器件有源区的掺杂浓度可以提高中子辐照容限。     

Neutron radiation effect on 4H-SiC MESFETs and SBDs

4H-SiC metal Schottky field effect transistors (MESFETs) and Schottky barrier diodes (SBDs) were irra-diated at room temperature with 1 MeV neutrons. The highest neutron flux and gamma-ray total dose were 1×1015n/cm2 and 3.3 Mrad(Si), respectively. After a neutron flux of 1×1013 n/cm2, the current characteristics of the MES-FET had only slightly changed, and the Schottky contacts of the gate contacts and the Ni, Ti/4H-SiC SBDs showed no obvious degradation. To further increase the neutron flux, the drain current of the SiC MESFET decreased and the threshold voltage increased. φB of the Schottky gate contact decreased when the neutron flux was more than or equal to 2.5×1014n/cm2. SiC Schottky interface damage and radiation defects in the bulk material are mainly mechanisms for performance degradation of the experiment devices, and a high doping concentration of the active region will improve the neutron radiation tolerance.     

A new Al0.3Ga0.7As/GaAs modulation-doped FET

A new Al0.3Ga0.7As/GaAs modulation-doped FET fabricated like a MESFET but operating like a JFET was successfully fabricated and tested. This new device replaces the Schottky gate of the MESFET with an n+/p+ camel diode structure, thereby allowing problems associated with the former to be overcome. The devices, which were fabricated from structures grown by molecular beam epitaxy (MBE), had a 1µm gate length, a 290µm gate width, and a 4µm channel length. The room temperature transconductance normalized to the gate width was about 95 mS/mm, which is comparable to that obtained in similar modulation-doped Schottky barrier FET's. Unlike modulation-doped Schottky barrier FET's, fabrication of this new device does not require any critical etching steps or formation of a rectifying metal contact to the rapidly oxidizing Al0.3Ga0.7As. Relatively simple fabrication procedures combined with good device performance make this camel gate FET suitable for LSI applications.     

RTD/2-D MESFET logic element for compact, ultra-low-powerelectronics

We describe compact and highly functional logic elements utilizing a two-dimensional (2-D) MESFET with a resonant tunneling diode load. The 2-D MESFET uses two lateral Schottky gate contacts to modulate the width of the 2-D electron gas layer. The novel contact geometry results in reduced gate capacitance, ultra-low-power performance, and the elimination of the Narrow Channel Effect (NCE) compared to conventional HFETs or MESFETs. The advantage of using an RTD as the load device is the reduction of the static power consumption at the logical high input level. We demonstrate low-power RTD/2-D MESFET inverter operation as well as compact NAND and NOR gates using a single RTD/2-D MESFET pair. We also present optimized inverter elements and estimate from SPICE simulations the power-delay products of RTD/2-D MESFET ring oscillators. Compared to recently reported values for CMOS on SOI, the RTD/2-D MESFET technology is expected to exhibit one order of magnitude less active power dissipation and a factor of 3 lower power-delay product     

High-transconductance enhancement-mode GaAs MESFET fabrication technology

An improved enhancement-mode GaAs MESFET was fabricated by a high dose Si ion implantation which was used to reduce the source and drain parasitic resistances, and by a Pt buried gate which was used to control the threshold voltage and reduce the interface states of the Schottky gate. 250 mS/mm transconductance has been obtained for 1-µm gate-length enhancement-mode GaAs MESFET.     

LaB_6/GaAs肖特基势垒研究

用电子束蒸发LaB_6单晶的方法,制备了LaB_6/GsAs肖特基势垒,经800℃高温退火后,势垒高度为0.70eV,理想因子为1.15～1.2。用俄歇能谱观察到LaB_6/GaAs界面有良好的热稳定性,以LaB_6为栅得到了初步的全离子注入的MESFET特性。结果表明,LaB_6有希望用于GaAs集成电路。     

Direct-Schottky-contact InP MESFET

The design and fabrication of an InP MESFET with excellent I -V characteristics are reported. A record high transconductance of 110 mS/mm was measured for a 1-μm gate length direct-Schottky-contact InP MESFET, where the InP surface was not passivated or treated prior to the deposition of the gate contact. Microwave measurements show an f_max of 11.6 GHz for this typical nominal 1-μm gate length device. A p-type planar doped layer was inserted between the buried n-type channel and the device surface at 18 nm from the gate metal. This planar layer enhances the Schottky barrier height and device performance     

MESFET fabrication on MOCVD grown Hg/sub 1-x/Cd/sub x/Te

The fabrication of the first MESFET structures on Hg/sub 1-x/Cd/sub x/Te is reported using MOCVD grown layers on GaAs substrates. The 6 mu m gate devices exhibited a room temperature transconductance of 1.0 mS/mm and pinch off voltage of -4.0 V. The Schottky barrier characteristics of the devices were critically dependent on the stoichiometric x ratio of the Hg/sub 1-x/Cd/sub x/Te with diode formation evident only at x >0.5.<>     

Millimeter-wave ion-implanted gradedInxGa1-xAs MESFETs grown by MOCVD

The authors present the fabrication and characterization of ion-implanted graded In_xGa_1-xAs/GaAs MESFETs. The In_xGa_1-xAs layers are grown on GaAs substrates by MOCVD (metal-organic chemical vapor deposition) with InAs concentration graded from 15% at the substrate to 0% at the surface. 0.5-μm gate MESFETs are fabricated on these wafers using silicon ion implantation. In addition to improved Schottky contact, the graded In_xGa _1-xAs MESFET achieves maximum extrinsic transconductance of 460 mS/mm and a current-gain cutoff frequency f_t of 61 GHz, which is the highest ever reported for a 0.5-μm gate MESFET. In comparison, In_0.1Ga_0.9As MESFETs fabricated with the same processing technique show an f_t of 55 GHz     

S-band operation of SiC power MESFET with 20 W (4.4 W/mm) output power and 60% PAE

Previous efforts have revealed instabilities in standard SiC MESFET device electrical characteristics, which have been attributed to charged surface states. This work describes the use of an undoped "spacer" layer on top of a SiC MESFET to form a "buried-channel" structure where the active current carrying channel is removed from the surface. By using this approach, the induced surface traps are physically removed from the channel region, such that the depletion depth caused by the unneutralized surface states cannot reach the conductive channel. This results in minimal RF dispersion ("gate lag") and, thus, improved RF performance. Furthermore, the buried-channel approach provides for a relatively broad and uniform transconductance (G/sub m/) with gate bias (V/sub gs/), resulting in higher efficiency MESFETs with improved linearity and lower signal distortion. SiC MESFETs having 4.8-mm gate periphery were fabricated using this buried-channel structure and were measured to have an output power of 21 W (P/sub out//spl sim/4.4 W/mm), 62% power added efficiency, and 10.6 dB power gain at 3 GHz under pulse operation. When operated at continuous wave, similar 4.8-mm gate periphery SiC MESFETs produced 9.2 W output power (P/sub out//spl sim/2 W/mm), 40% PAE, and /spl sim/7 dB associated gain at 3 GHz.     

Fabrication and characterization of a depletion-mode ZnS0.07Se0.93 MESFET

We report the fabrication and characterization of a depletion-mode n-channel ZnS_0.07Se_0.93 metal-semiconductor field effect transistor (MESFET). A ZnSSe FET could be a key element in opto-electronic integration consisting of light emitters, light receivers and MESFET pre-amplifiers. Mesa isolation, recess etching and self-alignment techniques were adopted to optimize the MESFET performance. Source and drain (S/D) ohmic contacts and gate Schottky contact were formed by Cr/In/Cr and Au deposition, respectively. Depletion mode FET's with varying gate width-to-length ratio of W/L=200 μm/20 μm, 200 μm/4 μm and 200 μm/2 μm were fabricated. A 2 μm FET was characterized as follows: the turn-on voltage, V_on≈1.75 V, the pinch-off voltage, V_p≈-13 V, the unit transconductance, g_m≈8.73 mS/mm, and the breakdown voltage with zero gate-source bias, BV≈28 V