Drain-bias dependence of threshold voltage stability of amorphous silicon TFTs

Amorphous silicon (a-Si:H) thin-film transistors (TFTs) used in emerging, nonswitch applications such as analog amplifiers or active loads, often have a bias at the drain terminal in addition to the gate that can alter their threshold voltage (V/sub T/) stability performance. At small gate stress voltages (0/spl les/V/sub ST//spl les/15 V) where the defect state creation instability mechanism is dominant, the presence of a bias at the TFT drain decreases the overall shift in V/sub T/(/spl Delta/V/sub T/) compared to the /spl Delta/V/sub T/ in the absence of a drain bias. The measured shift in V/sub T/ appears to agree with the defect pool model that the /spl Delta/V/sub T/ is proportional to the number of induced carriers in the a-Si:H channel.     

Charge trapping and detrapping characteristics in hafnium silicate gate stack under static and dynamic stress

The V/sub th/ instability of nMOSFET with HfSiON gate dielectric under various stress conditions has been evaluated. It is shown that after constant voltage stress, the threshold voltage (V/sub th/) relaxes to its initial prestress value. The relaxation rate is strongly affected by the stress duration and magnitude rather than injected charge flux or magnitude of the V/sub th/ shift. It is proposed that spatial distribution of trapped charges, which is strongly affected by the stress conditions, determines the relaxation rate. The implications of the electron trapping/detrapping processes on electrical evaluation of the high-/spl kappa/ gate dielectrics are discussed.     

Fully depleted dual-gated thin-film SOI P-MOSFETs fabricated in SOI islands with an isolated buried polysilicon backgate

P-channel dual-gated thin-film silicon-on-insulator (DG-TFSOI) MOSFETs have been fabricated with an isolated buried polysilicon backgate in an SOI island formed by epitaxial lateral overgrowth (ELO) of silicon. This structure allows individual operation of both the top and back gates rather than the conventional common backgate structure. When fully-depleted, the buried gate is used to individually shift the top gate threshold voltage (V/sub T/). A linear shift of /spl Delta/V/sub T,top///spl Delta/V/sub G,back/ of 0.5 V/V was achieved with a thin buried oxide. The effective density of interface traps (D/sub it/) for the backgate polysilicon-oxide SOI interface was measured to be 1.8/spl times/10/sup 11/ #/cm/sup 2//spl middot/eV as compared to the substrate-oxide of 1.1/spl times/10/sup 11/ #/cm/sup 2//spl middot/eV.     

The effect of IrO/sub 2/--IrO/sub 2/--Hf--LaAlO/sub 3/ gate dielectric on the bias-temperature instability of 3-D GOI CMOSFETs

We have studied the bias-temperature instability of three-dimensional self-aligned metal-gate/high-/spl kappa//Germanium-on-insulator (GOI) CMOSFETs, which were integrated on underlying 0.18 /spl mu/m CMOSFETs. The devices used IrO/sub 2/--IrO/sub 2/-Hf dual gates and a high-/spl kappa/ LaAlO/sub 3/ gate dielectric, and gave an equivalent-oxide thickness (EOT) of 1.4 nm. The metal-gate/high-/spl kappa//GOI p-and n-MOSFETs displayed threshold voltage (V/sub t/) shifts of 30 and 21 mV after 10 MV/cm, 85/spl deg/C stress for 1 h, comparable with values for the control two-dimensional (2-D) metal-gate/high-/spl kappa/-Si CMOSFETs. An extrapolated maximum voltage of -1.2 and 1.4 V for a ten-year lifetime was obtained from the bias-temperature stress measurements on the GOI CMOSFETs.     

Enhanced negative substrate bias degradation in nMOSFETs with ultrathin plasma nitrided oxide

The degradation induced by substrate hot electron (SHE) injection in 0.13-/spl mu/m nMOSFETs with ultrathin (/spl sim/2.0 nm) plasma nitrided gate dielectric was studied. Compared to the conventional thermal oxide, the ultrathin nitrided gate dielectric is found to be more vulnerable to SHE stress, resulting in enhanced threshold voltage (V/sub t/) shift and transconductance (G/sub m/) reduction. The severity of the enhanced degradation increases with increasing nitrogen content in gate dielectric with prolonged nitridation time. While the SHE-induced degradation is found to be strongly related to the injected electron energy for both conventional oxide , and plasma-nitrided oxide, dramatic degradation in threshold voltage shift for nitrided oxide is found to occur at a lower substrate bias magnitude (/spl sim/-1 V), compared to thermal oxide (/spl sim/-1.5 V). This enhanced degradation by negative substrate bias in nMOSFETs with plasma-nitrided gate dielectric is attributed to a higher concentration of paramagnetic electron trap precursors introduced during plasma nitridation.     

A highly threshold Voltage-controllable 4T FinFET with an 8.5-nm-thick Si-fin channel

Highly threshold voltage (V/sub th/)-controllable four-terminal (4T) FinFETs with an aggressively thinned Si-fin thickness down to 8.5-nm have successfully been fabricated by using an orientation-dependent wet-etching technique, and the V/sub th/ controllability by gate biasing has systematically been confirmed. The V/sub th/ shift rate (/spl gamma/=-/spl delta/V/sub th///spl delta/V/sub g2/) dramatically increases with reducing Si-fin thickness (T/sub Si/), and the extremely high /spl gamma/=0.79 V/V is obtained at the static control gate bias mode for the 8.5-nm-thick Si-fin channel device with the 1.7-nm-thick gate oxide. By the synchronized control gate driving mode, /spl gamma/=0.46 V/V and almost ideal S-slope are achieved for the same device. These experimental results indicate that the optimum V/sub th/ tuning for the high performance and low-power consumption very large-scale integrations can be realized by a small gate bias voltage in the ultrathin Si-fin channel device and the orientation-dependent wet etching is the promising fabrication technique for the 4T FinFETs.     

Charge trapping in ultrathin hafnium oxide

The charge trapping properties of ultrathin HfO/sub 2/ in MOS capacitors during constant voltage stress have been investigated. The effects of stress voltage, substrate type, annealing temperature, and gate electrode are presented in this letter. It is shown that the generation of interface-trap density under constant-voltage stress is much more significant for samples with Pt gate electrodes than that with Al gates. The trapping-induced flatband shift in HfO/sub 2/ with Al gates increases monotonically with injection fluence for p-type Si substrates, while it shows a turnaround phenomenon for n-type Si substrates due to the shift of the charge centroid. The trapping-induced flatband shift is nearly independent of stress voltage for p-type substrates, while it increases dramatically with stress voltage for n-type Si substrates due to two competing mechanisms. The trap density can be reduced by increasing the annealing temperature from 500/spl deg/C to 600/spl deg/C. The typical trapping probability for JVD HfO/sub 2/ is similar to that for ALD HfO/sub 2/.     

A technique to improve the drive current of high-voltage I/O transistors in digital CMOS technologies

By combining a 0.12-/spl mu/m-long 1.2-V thin-oxide transistor with a 0.22-/spl mu/m-long 3.3-V thick-oxide transistor in a 0.13-/spl mu/m CMOS process, a composite MOS transistor structure with a drawn gate length of 0.34 /spl mu/m is realized. Measurements show that at V/sub GS/=1.2 V and V/sub DS/=3.3 V, the composite transistor has more than two times the drain current of the minimum channel length (0.34 /spl mu/m) 3.3-V thick-oxide transistor, while having the same breakdown voltage (V/sub BK/) as the thick-oxide transistor. Exploiting these, it should be possible to implement 3.3-V I/O transistors with better combination of drive current, threshold voltage (V/sub T/) and breakdown voltage in conventional CMOS technologies without adding any process modifications.     

Impacts of gate electrode materials on threshold voltage (V/sub th/) instability in nMOS HfO/sub 2/ gate stacks under DC and AC stressing

Ultrathin nMOSFET hafnium oxide (HfO/sub 2/) gate stacks with TiN metal gate and poly-Si gate electrodes are compared to study the impact of the gate electrode on long term threshold instability reliability for both dc and ac stress conditions. The poly-Si/high-/spl kappa/ interface exhibits more traps due to interfacial reaction than the TiN/high-/spl kappa/ interface, resulting in significantly worse dc V/sub th/ instability. However, the V/sub th/ instability difference between these two stacks decreases and eventually diminishes as ac stress frequency increases, which suggests the top interface plays a minor role in charge trapping at high operating frequency. In addition, ac stress induced interface states (Nit) can be effectively recovered, resulting in negligible G/sub m/ degradation.     

Gate-induced drain leakage current degradation and its time dependence during channel hot-electron stress in n-MOSFETs

The effects of channel hot-electron stress on the gate-induced drain leakage current (GIDL) in n-MOSFETs with thin gate oxides have been studied. It is found that under worst case stress, i.e. a high density of generated interface states Delta D/sub it/, the enhanced GIDL exhibits a significant drain voltage dependence. Whereas Delta D/sub it/ increases significantly the leakage current at low V/sub d/, it has minor effects at high V/sub d/. On the other hand, the electron trapping was found to increase the leakage current rather uniformly over both low and high V/sub d/ regions. In addition, GIDL degradation can be expressed as a power law time dependence (i.e. Delta I/sub leak/=A.t/sup n/), and the time dependence value n varies according to the dominant damage mechanism (i.e. electron trapping against Delta D/sub it/), similar to that reported for on-state device degradation.<>     

Positive oxide charge-enhanced read disturb in a localized trapping storage flash memory cell

Read disturb-induced erase-state threshold voltage instability in a localized trapping storage Flash memory cell with a poly-silicon-oxide-nitride-oxide-silicon (SONOS) structure is investigated and reported. Our results show that positive trapped charge in bottom oxide generated during program/erase (P/E) cycles play a major role. Both gate voltage and drain voltage will accelerate the threshold voltage (V/sub t/) drift. Hot-carrier caused disturb effect is more severe in a shorter gate length device at low temperature. A model of positive charge-assisted electron tunneling into a trapping nitride is proposed. Influence of channel doping on the V/sub t/ drift is studied. As the cell is in an "unbiased" storage mode, tunnel detrapping of positive oxide charges is responsible for the threshold voltage shift, which is insensitive to temperature.     

High-energy tail electrons as the mechanism for the worst-case hot-carrier stress degradation of the deep submicrometer N-MOSFET

Experimental evidence, based on sensitively modulating the concentration of the high-energy tail of the electron energy distribution, reveals an important trend in the mid-to-high gate stress voltage (V/sub g/) regime, where device degradation is seen to continuously increase with the applied V/sub g/, for a given drain stress voltage V/sub d/. The shift in the worst-case degradation point from V/sub g//spl ap/V/sub d//2 to V/sub g/=V/sub d/, depicting an uncorrelated behavior with the substrate current, is caused by the injection of the high-energy tail electrons into the gate oxide, when the oxide field near the drain region becomes increasingly favorable as V/sub g/ approaches V/sub d/. This letter offers an improved framework for understanding the worst-case hot-carrier stress degradation of deep submicrometer N-MOSFETs under low bias condition.     

Path to the measurement of positive gain on the 1315-nm transition of atomic iodine pumped by O/sub 2/(a/sup 1//spl Delta/) produced in an electric discharge

Laser action at 1315 nm on the I(/sup 2/P/sub 1/2/)/spl rarr/I(/sup 2/P/sub 3/2/) transition of atomic iodine is conventionally obtained by a near-resonant energy transfer from O/sub 2/(a/sup 1//spl Delta/) which is produced using wet-solution chemistry. The system difficulties of chemically producing O/sub 2/(a/sup 1//spl Delta/) have motivated investigations into gas phase methods to produce O/sub 2/(a/sup 1//spl Delta/) using low-pressure electric discharges. We report on the path that led to the measurement of positive gain on the 1315-nm transition of atomic iodine where the O/sub 2/(a/sup 1//spl Delta/) was produced in a flowing electric discharge. Atomic oxygen was found to play both positive and deleterious roles in this system, and as such the excess atomic oxygen was scavenged by NO/sub 2/ to minimize the deleterious effects. The discharge production of O/sub 2/(a/sup 1//spl Delta/) was enhanced by the addition of a small proportion of NO to lower the ionization threshold of the gas mixture. The electric discharge was upstream of a continuously flowing supersonic cavity, which was employed to lower the temperature of the flow and shift the equilibrium of atomic iodine more in favor of the I(/sup 2/P/sub 1/2/) state. A tunable diode laser system capable of scanning the entire line shape of the (3,4) hyperfine transition of iodine provided the gain measurements.     

Influences of sulfur passivation on temperature-dependent characteristics of an AlGaAs/InGaAs/GaAs PHEMT

The influences of (NH/sub 4/)/sub 2/S/sub x/ treatment on an AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistor (PHEMT) are studied and demonstrated. Upon the sulfur passivation, the studied device exhibits better temperature-dependent dc and microwave characteristics. Experimentally, for a 1/spl times/100 /spl mu/m/sup 2/ gate/dimension PHEMT with sulfur passivation, the higher gate/drain breakdown voltage of 36.4 (21.5) V, higher turn-on voltage of 0.994 (0.69) V, lower gate leakage current of 0.6 (571) /spl mu/A/mm at V/sub GD/=-22 V, improved threshold voltage of -1.62 (-1.71) V, higher maximum transconductance of 240 (211) mS/mm with 348 (242) mA/mm broad operating regime (>0.9g/sub m,max/), and lower output conductance of 0.51 (0.53) mS/mm are obtained, respectively, at 300 (510) K. The corresponding unity current gain cutoff frequency f/sub T/ (maximum oscillation frequency f/sub max/) are 22.2 (87.9) and 19.5 (59.3) GHz at 250 and 400 K, respectively, with considerably broad operating regimes (>0.8f/sub T/,f/sub max/) larger than 455 mA/mm. Moreover, the relatively lower variations of device performances over wide temperature range (300/spl sim/510 K) are observed.     

Flexible AM OLED panel driven by bottom-contact OTFTs

Active matrix organic-light-emitting-diode (AM OLED) panels, driven by organic thin-film transistors (OTFT), have been successfully fabricated on a flexible plastic substrate. The pixel circuit consists of two bottom-contact pentacene OTFTs working as switching and driving transistors. The panel has 16 /spl times/ 16 pixels, each of which have an OLED using a phosphorescent material with an emission efficiency of 30 cd/A. A tantalum oxide (Ta/sub 2/O/sub 5/) film with a dielectric constant of 24, prepared by the anodization of Tantalum (Ta), was used as the gate insulator of the OTFTs. The passivation layer on the OTFTs was formed by a layer of silicon dioxide (SiO/sub 2/) and two layers of polyvinyl alcohol. Using OTFTs with a Ta/sub 2/O/sub 5/ gate insulator, the authors have realized a flexible active matrix OLED panel driven with a low voltage of -12 V.     

Mobility enhancement in TaN metal-gate MOSFETs using tantalum incorporated HfO/sub 2/ gate dielectric

TaN metal-gate nMOSFETs using HfTaO gate dielectrics have been investigated for the first time. Compared to pure HfO/sub 2/, a reduction of one order of magnitude in interface state density (D/sub it/) was observed in HfTaO film. This may be attributed to a high atomic percentage of Si-O bonds in the interfacial layer between HfTaO and Si. It also suggests a chemical similarity of the HfTaO-Si interface to the high-quality SiO/sub 2/-Si interface. In addition, a charge trapping-induced threshold voltage (V/sub th/) shift in HfTaO film with constant voltage stress was 20 times lower than that of HfO/sub 2/. This indicates that the HfTaO film has fewer charged traps compared to HfO/sub 2/ film. The electron mobility in nMOSFETs with HfO/sub 2/ gate dielectric was significantly enhanced by incorporating Ta.     

Novel gate voltage ramping technique for the characterisation of metal-oxide-semiconductor capacitor charge trapping properties

A novel technique is proposed to characterise the charge trapping properties of MOS capacitors by using the gate voltage ramping test. The parameter I=1-I/sub g/(t)/I/sub s/(t+ Delta t) measured during gate voltage ramping reveals the dielectric charge trapping characteristics. Positive charge trapping before dielectric breakdown was observed using this technique. A comparison between I and flatband voltage shift, Delta V/sub fb/, indicates that I gives the same information as Delta V/sub fb/ does at high stress fluences.<>     

High-performance poly-silicon TFTs using HfO/sub 2/ gate dielectric

High-performance low-temperature poly-Si thin-film transistors (TFTs) using high-/spl kappa/ (HfO/sub 2/) gate dielectric is demonstrated for the first time. Because of the high gate capacitance density and thin equivalent-oxide thickness contributed by the high-/spl kappa/ gate dielectric, excellent device performance can be achieved including high driving current, low subthreshold swing, low threshold voltage, and high ON/OFF current ratio. It should be noted that the ON-state current of high-/spl kappa/ gate-dielectric TFTs is almost five times higher than that of SiO/sub 2/ gate-dielectric TFTs. Moreover, superior threshold-voltage (V/sub th/) rolloff property is also demonstrated. All of these results suggest that high-/spl kappa/ gate dielectric is a good choice for high-performance TFTs.     

Radiation hardness comparison of MOS capacitors using tungsten polycide and cobalt polycideas gate electrode materials

In this letter, we investigate the radiation hardness of metal-oxide-semiconductor (MOS) capacitors with tungsten polycide (WSi/sub x/) and those with cobalt polycide (CoSi/sub 2/) as gate electrode materials. CoSi/sub 2/ has been considered as a gate/contact material for MOS devices in 0.18 /spl mu/m integrated circuit fabrication due to its low resistivity and good thermal stability. However, we found that MOS capacitors with a CoSi/sub 2/ gate electrode exhibited an increase in radiation-induced interface trap density shift of more than one order of magnitude, and more than eighteen times larger in radiation-induced flatband voltage shifts compared with those with the WSi/sub x/ gate electrode, after 1 Mrad Co/sup 60/ /spl gamma/-ray irradiation under no applied bias.     

A physically based analytical model for the threshold voltage of strained-Si n-MOSFETs

A physically based analytic model for the threshold voltage V/sub t/ of long-channel strained-Si--Si/sub 1-x/Ge/sub x/ n-MOSFETs is presented and confirmed using numerical simulations for a wide range of channel doping concentration, gate-oxide thicknesses, and strained-Si layer thicknesses. The threshold voltage is sensitive to both the electron affinity and bandgap of the strained-Si cap material and the relaxed-Si/sub 1-x/Ge/sub x/ substrate. It is shown that the threshold voltage difference between strained- and unstrained-Si devices increases with channel doping, but that the increase is mitigated by gate oxide thickness reduction. Strained Si devices with constant, high channel doping have a threshold voltage difference that is sensitive to Si cap thickness, for thicknesses below the equilibrium critical thickness for strain relaxation.