Clock synchronization using a linear process model

In this paper, we present a clock synchronization scheme based on a simple linear process model which describes the behaviors of clocks at a transmitter and a receiver. In the clock synchronization scheme, a transmitter sends explicit time indications or timestamps to a receiver, which uses them to synchronize its local clock to that of the transmitter. Here, it is assumed that there is no common network clock available to the transmitter and the receiver and, instead, the receiver relies on locking its clock to the arrival of the timestamps sent by the transmitter. The clock synchronization algorithm used by the receiver is based on a weighted least‐squares criterion. Using this algorithm, the receiver observes and processes several consecutive clock samples (timestamps) to generate accurate timing signals. This algorithm is very efficient computationally, and requires the storage of only a small number of clock samples in order to generate accurate timing signals. Copyright © 2006 John Wiley & Sons, Ltd.     

Circuit emulation services over Ethernet—Part 2: Prototype and experimental results

This paper describes a prototype implementation and experimental results for unstructured circuit emulation service (UCES) of T3 data stream over Ethernet. As explained in Part 1 of this paper,¹ packet‐switched networks such as Ethernet are not designed to transport TDM data and so have no inherent clock distribution and synchronization mechanisms. Thus, to allow the frequency of the source TDM stream to be regenerated at the receiver, the prototype employed the clock synchronization scheme described in Part 1 of this paper. Our experiments showed that the recovered clock conforms to ITU‐T G.824 requirements² even for networks that introduce high jitter and packet loss. Copyright © 2004 John Wiley & Sons, Ltd.     

IEEE1588协议及其在路由交换平台中的实现技术

下一代网络（NGN）是一种融合了IP技术和多媒体通信技术的全新网络,然而当涉及到传统TDM业务应用及需要进行时钟同步分配时,基于IP技术的全新网络则需要具备完善的时钟同步能力来满足相关业务的同步需求。IEEE1588协议标准的出现正好解决了在新一代路由交换平台中的时钟同步问题。这里分析了IEEE1588协议的偏移测量和延时测量时钟同步过程,并给出了IEEE1588协议在路由交换平台中的具体实现过程。     

以太网电路仿真技术及其应用

在无连接的分组交换网络中,仿真电路交换业务可以采用电路仿真技术。时分复用(TDM)业务对时延、抖动以及分组丢失等特性非常敏感,因此电路仿真要解决的根本问题就是确保仿真业务的服务质量特性要求。由于以太网具有廉价、简单、扩展性强和分布广泛等特点,通过以太网传送TDM业务的需求变得越来越明显。以太网电路仿真技术可以实现以太网透明地传输TDM业务(E1/T1和E3/T3等)。文中主要介绍了TDMoverEthernet技术的基本概念、技术要点及面临的主要技术挑战;通过与TDMoverIP、VoIP和ATM等相关技术的比较,指出了该技术的优势;最后,给出了TDMoverEthernet技术的一个应用实例。     

运动误差对双站SAR相位同步及成像的影响

收、发系统间的相位同步是双站合成孔径雷达的一项关键技术,采用锁相环接收机是实现双站SAR系统相位同步的一种可能方法.本文主要就锁相环接收机在运动误差条件下的相位同步问题进行了研究,并分析了锁相环相位误差对系统成像的影响,最后,给出了计算机仿真结果.     

A 40 Gb/s Clock and Data Recovery Module with Improved Phase‐Locked Loop Circuits

A 40 Gb/s clock and data recovery (CDR) module for a fiber‐optic receiver with improved phase‐locked loop (PLL) circuits has been successfully implemented. The PLL of the CDR module employs an improved D‐type flip‐flop frequency acquisition circuit, which helps to stabilize the CDR performance, to obtain faster frequency acquisition, and to reduce the time of recovering the lock state in the event of losing the lock state. The measured RMS jitter of the clock signal recovered from 40 Gb/s pseudo‐random binary sequence (2³¹‐1) data by the improved PLL clock recovery module is 210 fs. The CDR module also integrates a 40 Gb/s D‐FF decision circuit, demonstrating that it can produce clean retimed data using the recovered clock.     

blahblahblah测试专用文章

BSC A接口IP化后MGW与BSC之间通过IP承载网连接,不再设置TDM电路。因此,导致BSC A接口IP化后备选同步从MGW不可提取,时钟接入存在安全隐患。本文主要从时钟同步规范、时钟接入方案场景、时钟接入方案测试结果等方面进行论述,帮助设计人员在工程设计中合理的选择BSC时钟同步方案。     

Synchronization for IR‐UWB System Using a Switching Phase Detector‐Based Impulse Phase‐Locked Loop

Conventional synchronization algorithms for impulse radio require high‐speed sampling and a precise local clock. Here, a phase‐locked loop (PLL) scheme is introduced to acquire and track periodical impulses. The proposed impulse PLL (iPLL) is analyzed under an ideal Gaussian noise channel and multipath environment. The timing synchronization can be recovered directly from the locked frequency and phase. To make full use of the high harmonics of the received impulses efficiently in synchronization, the switching phase detector is applied in iPLL. It is capable of obtaining higher loop gain without a rise in timing errors. In different environments, simulations verify our analysis and show about one‐tenth of the root mean square errors of conventional impulse synchronizations. The developed iPLL prototype applied in a high‐speed ultra‐wideband transceiver shows its feasibility, low complexity, and high precision.     

城域以太网中的电路仿真业务及其应用

文章概述了基于城域以太网（MEN）的时分复用（TDM）电路仿真业务（CES）的概念，简要介绍了基于MEN的CES的主要业务类型，并着重分析了其中的TDM线路业务的主要结构及其运作方式，描述了电路仿真业务的主要接口类型与功能元件，最后对其进行了应用方案与应用前景的简要分析。     

Measurement Scheme for One‐Way Delay Variation with Detection and Removal of Clock Skew

One‐way delay variation (OWDV) has become increasingly of interest to researchers as a way to evaluate network state and service quality, especially for real‐time and streaming services such as voice‐over‐Internet‐protocol (VoIP) and video. Many schemes for OWDV measurement require clock synchronization through the global‐positioning system (GPS) or network time protocol. In clock‐synchronized approaches, the accuracy of OWDV measurement depends on the accuracy of the clock synchronization. GPS provides highly accurate clock synchronization. However, the deployment of GPS on legacy network equipment might be slow and costly. This paper proposes a method for measuring OWDV that dispenses with clock synchronization. The clock synchronization problem is mainly caused by clock skew. The proposed approach is based on the measurement of inter‐packet delay and accumulated OWDV. This paper shows the performance of the proposed scheme via simulations and through experiments in a VoIP network. The presented simulation and measurement results indicate that clock skew can be efficiently measured and removed and that OWDV can be measured without requiring clock synchronization.     

一种CCD彩色摄像系统的视频锁相同步系统

介绍一种应用于ＣＣＤ彩色摄像系统的视频锁相同步系统。基于锁相理论的视频锁相同步系统是一个二级锁相环路,包括同步信号发生电路和高频点像素时钟电路。并详细阐述了同步信号发生电路和高频点像素时钟电路的锁相原理及电路。高频点像 时钟电路的外分频电路是由现场可编门阵列实例可编程特必珂得到不同频率的高频点像素时钟。     

Timing Recovery for Backplane Ethernet

The dominant solutions for single-chip multi-port backplane Ethernet transceivers utilize a dual-loop design - a combination of a single master phase-locked loop (PLL) and multiple slave delay-locked loops (DLL). Each transmitter or receiver port has its own DLL, which delays or advances a copy of the master clock from the master PLL to generate its own clock signal for synchronization. The DLLs are typically implemented using current-mode logic phase interpolators. This paper presents an alternative solution to this synchronization problem. Instead of moving the sampling phase, timing recovery is done by changing the group delay of the receiver-side forward equalizer by rotating its tap coefficients. The standard least-mean-square algorithm is used for coefficient rotation. This solution is equivalent to a first-order PLL/DLL, which suffers from steady-state timing offset when there is a frequency offset between the transmitter and the receiver. However, the degradation in performance caused by a frequency offset is significantly reduced by using a coefficient-rotation digital-signal processor capable of detecting and reducing the offset. With a practical frequency accuracy specification of plusmn100 ppm, the improved performance can approach that of the PLL/DLL dual-loop solution.     

A 3.1 to 5 GHz CMOS Transceiver for DS‐UWB Systems

This paper presents a direct‐conversion CMOS transceiver for fully digital DS‐UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phase‐locked loop (PLL), and a voltage controlled oscillator (VCO). A single‐ended‐to‐differential converter is implemented in the down‐conversion mixer and a differential‐to‐single‐ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 mm² die using standard 0.18 µm CMOS technology and a 64‐pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low‐power, and high‐speed wireless personal area network.     

基于FPGA的EoS系统中帧处理的改进与实现

根据ITU-TX.86协议的规定,设计了一种EoS系统,实现了IP数据包在基于SDH的骨干光传输网络中的高速传输。针对现有帧处理方案在帧同步时延和时钟抖动方面存在的问题,提出了改进的快速帧同步机制和时钟提取方案。采用廉价的FPGA硬件编程实现,通过电路综合与时序仿真表明,方案在缩短帧同步时延和消除时钟抖动方面具有较好的效果。     

同步以太网测试方法

得益于移动宽带业务的强劲增长,许多移动网络运营商已经或正在把移动回传网络从传统同步传输(如SONET/SDH和T1/E1)迁移到运营级以太网。传统TDM网络不仅提供数据传输,而且能实现频率同步。这样,原来由TDM网络提供的时钟同步也同样必须在以太网络中实现,并且同步的质量和网络性能不能受到影响。再者,3G/LTE无线网络不仅需要频率同步,还需要时间/相位的同步。所以,在部署前对以太网络各个部件作同步性能的验证就显得非常必要。本文介绍了实现以太网同步的各种方式和原理、同步精度测量面临的挑战。结合IXIA业界领先的同步测试工具Anue 3500,重点对PTP技术中的路径支持设备(如边界时钟和透明时钟)的测试方法进行了探讨。     

5G网络时钟同步研究

本文介绍了网络时钟同步方案,针对5G网络中,4G与5G基站时钟同步不对齐,会导致5G用户下载速率下降、4/5G无法正常互操作等问题,分场景深入分析问题现象和原因,提出通过信号分路方式为5G提供基站同步信号、新建卫星接收天线引入、选用1588v2时钟方案等解决方案,并展望后续推进移动基站北斗/GPS 授时系统双模改造。为5G网络时钟同步建设提供了建议。     

一种适用于SoC的时钟复位管理电路设计

给出了一套适用于SoC芯片的时钟和复位管理电路设计范例,详细介绍了SoC芯片中的时钟和复位管理电路的实现方案。其中时钟管理电路支持输入时钟可选、PLL动态变频、时钟门控管理和时钟状态查询功能,能够灵活的控制各模块输入时钟开启或关闭,很好的支持SoC芯片低功耗工作模式。复位管理电路支持复位输入控制功能和复位状态查询功能。复位输入控制可以选择使能或不使能复位源触发系统复位。     

Using negative stuffing retiming for circuit emulation in a packetswitching network

A circuit emulation scheme based on negative stuffing retiming that can effectively remove large bursty delay between packets is described. The approach can be applied to various applications such as T-carrier emulation and packet voice and video communication. The key element of the proposed negative stuffing scheme is the stuffing control or when to add negative stuffing. Two stuffing control algorithms are discussed. The first one is very simple and can provide a smooth output without the need of knowing or estimating the transmitter clock. This algorithm transforms large and fast packet arrival jitter into small and slowly varying frequency wander. The second algorithm tries to estimate the transmitter clock to further reduce the wander. Both algorithms will in principle eliminate the large packet arrival jitter completely, and they also ensure no buffer overflow and underflow. To evaluate buffer delay, jitter, and wander of the recovered clock, time domain simulation has been done for DS1 and DS3 signals over a SONET STS-3c-based switching network     

量子密钥分发系统中高精度同步方案设计

针对光纤量子密钥分发(QKD)系统中信号同步的关键问题,提出了一种光同步方案。发送方通过现场可编程门阵列（FPGA）产生一定特征的同步脉冲序列驱动同步激光器,产生的同步光和信号光耦合到一根光纤传给接收方。接收方经过高速甄别后使用高频时钟来“采样”接收到的同步脉冲序列,使得双方达到严格同步;同时经过高精度延时调整后提供给单光子探测器作为门控信号,最大限度地去除暗计数。该方案具有高精度,低成本,容错性好的特点,已经成功应用于城域量子通信网络。     

全数字延时锁定环及其应用

介绍了一种区别于锁相环(PLL)和基于压控延迟线(VCDL)的延时锁定环(DLL)、全部由纯数字电路实现的DLL电路.该电路用于消除时钟时延,全数字的结构使其无条件稳定,不会累积相位误差,而且具有良好的噪声敏感度、较低的功耗和抖动性能.使其在时延补偿和时钟调整的应用中具有优势,并可全部嵌入单个芯片中.文中分析了全数字DLL的工作原理及其结构,给出了其在现场可编程门阵列(FPGA)中的应用.