An efficient algorithm for finding all DC solutions of piecewise‐linear circuits

An efficient algorithm is proposed for finding all DC solutions of transistor circuits where characteristics of transistors are represented by piecewise‐linear (PWL) convex monotone functions. This algorithm is based on a simple test (termed the linear programming, LP, test) for non‐existence of a solution to a system of PWL equations in a given region. In the conventional LP test, the system of PWL equations is transformed into an LP problem by surrounding component PWL functions by rectangles. Then the dual simplex method is applied, by which the number of pivotings per region becomes very small. In this letter, we propose a new LP test using the dual simplex method and triangles. The proposed test is not only efficient but also more powerful than the conventional test using the simplex method or rectangles. Copyright © 2008 John Wiley & Sons, Ltd.     

On simplex‐based piecewise‐linear approximations of non‐linear mappings

Simplex‐based piecewise‐linear (PWL) approximations of non‐linear mappings are needed when the robust PWL analysis is used to directly solve non‐linear equations. This paper proposes a straightforward technique for transforming the well‐known approximations into another form. This new form is computationally more efficient, since it preserves the sparse structure of the original Jacobian matrix. Furthermore, this new form of PWL approximation explicitly relates the simplex‐based PWL analysis to the conventional formulation of the Katzenelson algorithm. The proposed transform technique is also extended to treat groupwise‐separable mappings and, finally, non‐separable but sparse mappings that arise in real‐life simulation of large electronic circuits. In this paper, all these (transformed) simplex‐based PWL approximations are compared in terms of their generality and efficiency. The computational efficiency of the PWL approximation that utilizes sparsity is validated with realistic simulations. Copyright © 2005 John Wiley & Sons, Ltd.     

An efficient piecewise‐linear DC analysis method for general non‐linear circuits

The convergence problems of conventional DC analysis can be partly avoided by using piecewise‐linear analysis. This paper proposes a piecewise‐linear DC analysis method that can efficiently handle arbitrary couplings between non‐linear circuit elements. Piecewise‐linear modelling of the non‐linear circuit elements is automatically performed during simulation, using simplicial subdivisions. The number of linear regions, and thereby iterations, is considerably reduced by combining the common parts of separate simplicial subdivisions. Due to these reasons and since the method is formulated with the commonly used modified nodal approach, it has been possible to implement the method in the general‐purpose circuit simulator APLAC. The correct operation of the method is demonstrated with three examples. Copyright © 1999 John Wiley & Sons, Ltd.     

Finding all solutions of piecewise‐linear resistive circuits using the dual simplex method

An efficient algorithm is proposed for finding all solutions of piecewise‐linear (PWL) resistive circuits using linear programming (LP). This algorithm is based on a simple test (termed the LP test) for non‐existence of a solution to a system of PWL equations in a given region. In the conventional LP test, the system of PWL equations is transformed into an LP problem, to which the simplex method is applied. However, this algorithm requires a very large number of pivotings because the simplex method is applied on many regions. In this paper, we introduce the dual simplex method to the LP test, which makes the average number of pivotings per region much smaller (less than one, for example) and makes the algorithm very efficient. By numerical examples, it is shown that the proposed algorithm could find all solutions of large‐scale problems, including those where the number of variables is 300 and the number of linear regions is 10³⁰⁰, in practical computation time. Copyright © 2002 John Wiley & Sons, Ltd.     

Synthesis of multiport resistors with piecewise‐linear characteristics: a mixed‐signal architecture

Non‐linear multiport resistors are the main ingredients in the synthesis of non‐linear circuits. Recently, a particular PWL representation has been proposed as a generic design platform (IEEE Trans. Circuits Syst.‐I 2002; 49 :1138–1149). In this paper, we present a mixed‐signal circuit architecture, based on standard modules, that allows the electronic integration of non‐linear multiport resistors using the mentioned PWL structure. The proposed architecture is fully programmable so that the unit can implement any user‐defined non‐linearity. Moreover, it is modular: an increment in the number of input variables can be accommodated through the addition of an equal number of input modules. Copyright © 2005 John Wiley & Sons, Ltd.     

A novel compact piecewise‐linear representation

A new compact MAX representation for 2‐D continuous piecewise‐linear (PWL) functions is developed in this paper. The representation is promising since it can be easily generalized into higher dimensions. We also establish the explicit functional form of basis function and demonstrate that the proposed basis function is the elementary ‘building block’ from which a fully general 2‐D PWL function can be constructed. In addition, we reveal the relationship of basis function with minimal degenerate intersection and Hinging Hyperplane, which shows that the MAX model can unify Chua's canonical expression, Li's representation, lattice PWL function and Bremann's Hinging Finding Algorithm into one common theoretical framework. Copyright © 2005 John Wiley & Sons, Ltd.     

Digital architectures realizing piecewise‐linear multivariate functions: Two FPGA implementations

Digital architectures for the circuit realization of multivariate piecewise‐linear (PWL) functions are reviewed and compared. The output of the circuits is a digital word representing the value of the PWL function at the n‐dimensional input. In particular, we propose two architectures with different levels of parallelism/complexity. PWL functions with n = 3 inputs are implemented on an FPGA and experimental results are shown. The accuracy in the representation of PWL functions is tested through three benchmark examples, two concerning three‐variate static functions and one concerning a dynamical control system defined by a bi‐variate PWL function. Copyright © 2009 John Wiley & Sons, Ltd.     

Performance evaluation of the LP test algorithm for finding all solutions of piecewise‐linear resistive circuits

In this letter, the performance of the LP test algorithm, which is an algorithm for finding all solutions of piecewise‐linear resistive circuits, is evaluated by numerical experiments. It is shown that the algorithm could find all solutions of large‐scale problems (including those where the number of variables is 200–300 and the number of linear regions is 10²⁰⁰–10³⁰⁰) in practical computation time. Copyright © 2000 John Wiley & Sons, Ltd.     

Improvement of the contraction‐type LP test algorithm for finding all solutions of piecewise‐linear resistive circuits

In this letter, an effective technique is proposed for improving the computational efficiency of the contraction‐type LP test algorithm, which is an algorithm for finding all solutions of piecewise‐linear resistive circuits. Using the proposed technique, all solutions of a large‐scale problem, where the number of variables is 100 and the number of linear regions is 10¹⁰⁰, could be found in less than 10 min using a 360 MHz computer. Copyright 2001 John Wiley & Sons, Ltd.     

The piecewise‐affine model of buck converter suitable for practical stability analysis

A generalized geometrical piecewise‐affine continuous‐time model (GMD) of buck converter under pulse‐width modulated (PWM) voltage‐mode control is presented in this paper. In general, such a model can be applied to any DC‐DC power electronic converter (PEC) in which the valves are modelled as ideal switches. The GMD is suitable and convenient to analyse PEC practical stability which is a completely different concept in relation to the notion of its stability in the classical Lyapunov sense. The PEC GMD is based on its commutation structure which is a general geometrical model of its commutation. The general idea of this model consists in determining the local dynamic behaviour of PEC trajectories on the faces of its commutation structure and/or their sections. These faces and sections are treated as geometrical objects with generalized local dynamics. The analysis of buck converter practical stability is carried out using a new method based directly on the definition of this term but not Lyapunov‐like functions as in the direct method. It has been shown that PEC Lyapunov stability does not imply its practical stability. These two concepts are complementary to each other. Copyright © 2013 John Wiley & Sons, Ltd.     

A generalized geometrical piecewise‐affine model of DC‐DC power electronic converters

A generalized model of the dynamics (GMD) of DC‐DC power electronic converters (PECs) is discussed in this paper. It is a geometrical piecewise‐affine continuous‐time model. The general idea of the GMD is to determine the local dynamic behavior of trajectories on the faces of the PEC commutation structure, which is a geometrical model of its commutation. This allows us to establish the direction of PEC dynamics on these faces. It can be either ‘entering’ into specific regions in state space or ‘exiting’ from them. Therefore, the local PEC dynamics can be treated as logical (two‐state). In practice, the GMD can be used for the analysis of PEC practical stability, which is a completely different concept from the concept of PEC stability in the classical Lyapunov sense. An outline of the design‐oriented approach to PEC practical stability analysis, which is based on the GMD, has also been presented. As illustrative examples, the GMD of a boost converter under peak current‐mode control and its application are presented. These examples show that the Lyapunov stability of a given PEC does not imply its practical stability, and that the results of PEC Lyapunov stability analysis and practical stability analysis are complementary to each other. Copyright © 2013 John Wiley & Sons, Ltd.     

Discontinuity correction in piecewise‐linear models of oscillators for phase noise characterization

Decomposition of noise perturbation along Floquet eigenvectors has been extensively used in order to achieve a complete analysis of phase noise in oscillator. Piecewise‐linear approximation of nonlinear devices is usually adopted in numerical calculation based on multi‐step integration method for the determination of unperturbed oscillator solution. In this case, exact determination of the monodromy matrix can be hampered by the presence of discontinuities between models introduced by the approximation. In this paper we demonstrate that, without the proper corrections, relevant errors occur in the determination of eigenvalues and eigenvectors, if adjacent linear models presents discontinuities. We obtain this result by the analysis of a simple 2‐D oscillator with piecewise‐linear parameter. We also demonstrate that a correct calculation can be achieved introducing properly calculated state vector boundary conditions by the use of interface matrices. This correction takes into account the effects of discontinuities between the linear models, leading to exact calculation of eigenvalues and eigenvectors, and, consequently, of the phase noise spectrum. Copyright © 2006 John Wiley & Sons, Ltd.     

Current‐mode programmable piecewise‐linear neural synapses

Cellular Neural Networks with piecewise linear connection have been proposed by several authors as a generalization of the basic paradigm, which allows for more complex functionality. None of the prototypes realized to date, however, provides for such kind of synapses. As a feasibility study, a current‐mode subthreshold CMOS piecewise‐linear synapse circuit is developed in this paper. Copyright © 2003 John Wiley & Sons, Ltd.     

An interval algorithm for finding all solutions of non‐linear resistive circuits

In this letter, an efficient algorithm is proposed for finding all solutions of non‐linear (not piecewise‐linear) resistive circuits. This algorithm is based on interval analysis, the dual simplex method, and the contraction methods. By numerical examples, it is shown that the proposed algorithm could find all solutions of systems of 500–700 non‐linear circuit equations in acceptable computation time. Copyright © 2004 John Wiley & Sons, Ltd.     

New strategies in model order reduction of trajectory piecewise‐linear models

Model order reduction based on trajectory piecewise linearization (TPWL) is a beneficial technique for approximating nonlinear models. One efficient method for building projection matrix in TPWL reduction is by aggregation of projection matrices of linearization points (LPs). However, in this method, the size of projection matrix will also grow up by increasing the number of LPs, which yield the increment of the size of reduced model. In other words, the size of reduced model will depend on the number of LPs. In this paper, we will address this issue and propose two new strategies for obviating this problem. Contrarily to former works in TPWL modeling, we established a model via TWPL based on output weighting of parallel linear models. Then, we proposed two reduction strategies for suggested TPWL model. The first algorithm inspires from former works in this field but in a parallel structure that enable segregation of projection matrices whereas the second algorithm remedies the problem by considering the high‐order TPWL model as a unit linear model and reduces this model like a linear model but uses back projection method for constructing different outputs. The efficiency of methods is shown by comparison with former TPWL methods through vast simulations. Copyright © 2015 John Wiley & Sons, Ltd.     

An interleaved high step‐up DC‐DC converter with double boost paths

This paper proposed a novel high step‐up converter with double boost paths. The circuit uses two switches and one double‐path voltage multiplier cell to own the double boost and interleaved effects simultaneously. The voltage gain ratio of the proposed DC‐DC converter can be three times the ratio of the conventional boost converter such that the voltage stress of the switch can be lower. The high step‐up performance is in accordance with only one double‐path voltage multiplier cell. Therefore, the number of diodes and capacitors in the proposed converter can be reduced. Furthermore, the interleaved property of the proposed circuit can reduce the losses in the rectifier diode and capacitor. The prototype circuit with 24‐V input voltage, 250‐V output voltage, and 150‐W output power is experimentally realized to verify the validity and effectiveness of the proposed converter. Copyright © 2014 John Wiley & Sons, Ltd.     

Existence and uniqueness of solutions for DC networks containing non‐linear ideal op amps

In this paper we are concerned with networks obtained by connecting independent sources, linear resistors and non‐linear ideal op amps. A necessary and sufficient condition for the existence and uniqueness of solutions for every positive output saturation voltage of the op amps and every value of the independent sources is found. Copyright © 2001 John Wiley & Sons, Ltd.     

A soft‐switching high step‐up DC‐DC converter with a single magnetic component

A soft‐switching high step‐up DC‐DC converter with a single magnetic component is presented in this paper. The proposed converter can provide high voltage gain with a relatively low turn ratio of a transformer. Voltage doubler structure is selected for the output stage. Due to this structure, the voltage gain can be increased, and the voltage stresses of output diodes are clamped as the output voltage. Moreover, the output diode currents are controlled by a leakage inductance of a transformer, and the reverse‐recovery loss of the output diodes is significantly reduced. Two power switches in the proposed converter can operate with soft‐switching due to the reflected secondary current. The voltages across the power switches are confined to the clamping capacitor voltage. Steady‐state analysis, simulation, and experimental results for the proposed converter are presented to validate the feasibility and the performance of the proposed converter. Copyright © 2012 John Wiley & Sons, Ltd.     

Bifurcation analysis of a piecewise smooth system with non‐linear characteristics

In previous works, there are no results about the bifurcation analysis for a piecewise smooth system with non‐linear characteristics. The main purpose of this study is to calculate the bifurcation sets for a piecewise smooth system with non‐linear characteristics. We first propose a new method to track the bifurcation sets in the system. This method derives the composite discrete mapping, Poincaré mapping. As a result, it is possible to obtain the local bifurcation values in the parameter plane. As an illustrated example, we then apply this general methodology to the Rayleigh‐type oscillator containing a state‐ period‐dependent switch. In the circuit, we can find many subharmonic bifurcation sets including global bifurcations. We also show the bifurcation sets for the border‐collision bifurcations. Some theoretical results are verified by laboratory experiments. Copyright © 2005 John Wiley & Sons, Ltd.     

A non‐isolated high step‐up DC‐DC converter with integrated 3 winding coupled inductor and reduced switch voltage stress

In this paper, a non‐isolated high step‐up dc‐dc converter based on coupled inductor is proposed. The proposed converter can be used in renewable energy applications. In suggested converter, the high voltage is achieved using 3‐winding coupled inductor, which leads to low voltage rate of the switch. A clamp circuit is used to recycle the leakage inductance energy. Also, the clamp circuit prevents the creation of voltage spikes on semiconductor devices and causes the voltage stress of elements are limited to less than the output voltage. The presented theoretical analyses show that the operation of suggested converter in continuous conduction mode needs to small magnetic inductor. Therefore, the size of coupled inductor's core is reduced, and so the size and cost of presented converter will be decreased. Analysis of the proposed converter is provided with laboratory results to verify its performance.