An analytical approach to the performance evaluation of the balanced gamma switch under multicast traffic

This paper presents the performance evaluation of a new cell‐based multicast switch for broadband communications. Using distributed control and a modular design, the balanced gamma (BG) switch features high performance for unicast, multicast and combined traffic under both random and bursty conditions. Although it has buffers on input and output ports, the multicast BG switch follows predominantly an output‐buffered architecture. The performance is evaluated under uniform and non‐uniform traffic conditions in terms of cell loss ratio and cell delay. An analytical model is presented to analyse the performance of the multicast BG switch under multicast random traffic and used to verify simulation results. The delay performance under multicast bursty traffic is compared with those from an ideal pure output‐buffered multicast switch to demonstrate how close its performance is to that of the ideal but impractical switch. Performance comparisons with other published switches are also studied through simulation for non‐uniform and bursty traffic. It is shown that the multicast BG switch achieves a performance close to that of the ideal switch while keeping hardware complexity reasonable. Copyright © 2006 John Wiley & Sons, Ltd.     

Design of a non-blocking shared-memory copy network for ATM

The design of a copy network is presented for use in an ATM (asynchronous transfer mode) switch supporting BISDN (broadband integrated services digital network) traffic. Inherent traffic characteristics of BISDN services require ATM switches to handle bursty traffic with multicast connections. In typical ATM switch designs a copy network is used to replicate multicast cells before being forwarded to a point-to-point routeing network. In such designs, a single multicast cell enters the switch and is replicated once for each multicast connection. Each copy is forwarded to the routeing network with a unique destination address and is routed to the appropriate output port. Non-blocking copy networks permit multiple cells to be multicasted at once, up to the number of outputs of the copy network. Another critical feature of ATM switch design is the location of buffers for the temporary storage of transmitted cells. Buffering is required when multiple cells require a common switch resource for transmission. Typically, one cell is granted the resource and is transmitted while the remaining cells are buffered. Current switch designs associate discrete buffers with individual switch resources. Discrete buffering is not efficient for bursty traffic as traffic bursts can overflow individual switch buffers and result in dropped cells, while other buffers are under-used. A new non-blocking copy network is presented in this paper with a shared-memory input buffer. Blocked cells from any switch input are stored in a single shared input buffer. The copy network consists of three banyan networks and shared-memory queues. The design is scalable for large numbers of inputs due to low hardware complexity, O (N log₂ N), and distributed operation and control. It is shown in a simulation study that a switch incorporating the shared-memory copy network has increased throughput and lower buffer requirements to maintain low packet loss probability when compared to a switch with a discrete buffer copy network.     

Performances of the Data Vortex switch architecture under nonuniform and bursty traffic

The Data Vortex switch architecture has been proposed as a scalable low-latency interconnection fabric for optical packet switches. This self-routed hierarchical architecture employs synchronous timing and distributed traffic-control signaling to eliminate optical buffering and to reduce the required routing logic, greatly facilitating a photonic implementation. In previous work, we have shown the efficient scalability of the architecture under uniform and random traffic conditions while maintaining high throughput and low-latency performance. This paper reports on the performance of the Data Vortex architecture under nonuniform and bursty traffic conditions. The results show that the switch architecture performs well under modest nonuniform traffic, but an excessive degree of nonuniformity will severely limit the scalability. As long as a modest degree of asymmetry between the number of input and output ports is provided, the Data Vortex switch is shown to handle very bursty traffic with little performance degradation.     

Architecture design,performance analysis and VLSI implementation of a reconfigurable shared buffer for high‐speed switch/router

Modern switches and routers require massive storage space to buffer packets. This becomes more significant as link speed increases and switch size grows. From the memory technology perspective, while DRAM is a good choice to meet capacity requirement, the access time causes problems for high‐speed applications. On the other hand, though SRAM is faster, it is more costly and does not have high storage density. The SRAM/DRAM hybrid architecture provides a good solution to meet both capacity and speed requirements. From the switch design and network traffic perspective, to minimize packet loss, the buffering space allocated for each switch port is normally based on the worst‐case scenario, which is usually huge. However, under normal traffic load conditions, the buffer utilization for such configuration is very low. Therefore, we propose a reconfigurable buffer‐sharing scheme that can dynamically adjust the buffering space for each port according to the traffic patterns and buffer saturation status. The target is to achieve high performance and improve buffer utilization, while not posing much constraint on the buffer speed. In this paper, we study the performance of the proposed buffer‐sharing scheme by both a numerical model and extensive simulations under uniform and non‐uniform traffic conditions. We also present the architecture design and VLSI implementation of the proposed reconfigurable shared buffer using the 0.18 µm CMOS technology. Our results manifest that the proposed architecture can always achieve high performance and provide much flexibility for the high‐speed packet switches to adapt to various traffic patterns. Furthermore, it can be easily integrated into the functionality of port controllers of modern switches and routers. Copyright © 2008 John Wiley & Sons, Ltd.     

A Novel Algorithm for Maintaining Packet Order in Two‐Stage Switches

To enhance the scalability of high performance packet switches, a two‐stage load‐balanced switch has recently been introduced, in which each stage uses a deterministic sequence of configurations. The switch is simple to make scalable and has been proven to provide 100% throughput. However, the load‐balanced switch may missequence the packets. In this paper, we propose an algorithm called full frame stuff (FFS), which maintains packet order in the two‐stage load‐balanced switch and has excellent switching performance. This algorithm is distributed and each port can operate independently.     

An approximate analysis of shared‐buffer channel‐grouped ATM switches under imbalanced traffic

Grouping output channels in a shared‐buffer ATM switch has shown to provide great saving in buffer space and better throughput under uniform traffic. However, uniform traffic does not represent a realistic view of traffic patterns in real systems. In this paper, we extend the queuing analysis of shared‐buffer channel‐grouped (SBCG) ATM switches under imbalanced traffic, as it better represent real‐life situations. The study focuses on the impact of the grouping factor and other key switch design parameters on the performance of such switches as compared to the unichannel allocation scheme in terms of cell loss probability, throughput, mean cell delay and buffer occupancy. Numerical results from both the analytical model and simulation are presented, and the accuracy of the analysis is presented. Copyright © 2005 John Wiley & Sons, Ltd.     

Dynamic switch migration with noncooperative game towards control plane scalability in SDN

As software‐defined networking (SDN) is a logically centralized technology, the control plane scalability in SDN is increasingly important with the network scale increasing. Load balancing and maximizing resource utilization are very critical to the control plane in SDN, while switch migration is an effective approach to achieve these two performance metrics. However, switch migration is NP‐hard problem because it belongs to the problem of combinatorial optimization. To avoid the NP‐hard problem, we propose a switch migration scheme by adopting noncooperative game to improve the control plane scalability in SDN. First, we design a novel load balancing monitoring scheme to detect the load imbalance between controllers and trigger migrating switches. Then, we use noncooperative game among controllers to decide switch migration to get the maximizing overall profits. Last, we prove that our proposed approach can get Pareto optimality. Extensive simulations prove that our method is able to achieve a more scalable control plane with load balancing and maximizing resource utilization.     

两级交换机中分组有序到达算法研究

为了提高高性能分组交换机的扩展性,张尚正等人提出了一种称为负载平衡交换机(load-balancedswitch)的交换结构,该交换机分为两级交换结构,每一级都采用一种时序固定的连接方式,具有良好的扩展性;同时可以提供100%吞吐量保证。但是,负载平衡交换机的基本结构会出现分组乱序的情况。本文提出了一种在两级负载平衡交换机中保证分组顺序到达的满帧填充算法,该算法具有良好的交换特性(平均时延及吞吐量),同时也是一种分布式算法,各个端口可以独立地进行操作。     

高性能新型交换结构综述

 目前基于单级交换结构(single-stage switch)集中式调度的路由器已经不能满足Internet网络流量、网络规模和上层应用的快速发展.近年来,旨在提高路由器可扩展性、吞吐率、QoS能力的高性能交换技术,成为路由器技术研究中的一大热点.文章从体系结构、调度策略、QoS特性三个方面对高性能交换结构研究进展进行了综述,以可扩展性、实现复杂度、延迟和吞吐率保证、负载均衡及报文乱序为主要衡量指标分析比较了每一类交换结构调度算法的性能,最后提出下一步的研究课题和思路.     

Switch‐and‐examine combining with different new switch statistics for diversity over Rayleigh fading channels

Three schemes of multibranch switch‐and‐examine combining (MSEC) with switch statistics different from the signal‐to‐noise ratio used in the traditional MSEC are analyzed. For each diversity branch, with its fading factor a and low‐passed received signal r, the switch statistics for the three MSEC schemes considered in the paper are | r | , | ar | , and a linear combination of a and | r | , respectively. To illustrate the performances of the MSEC schemes, the average BER of each MSEC scheme with BPSK signaling is evaluated for independent and identically distributed Rayleigh fading channels. For performance optimization, the optimal switch thresholds of the MSEC schemes are obtained. Numerical results based on the analysis and simulations are presented for performance illustrations. Copyright © 2012 John Wiley & Sons, Ltd.     

Fault tolerance in Clos–Knockout multicast ATM switch

In this paper, we propose a new architecture for multicast ATM switches with fault tolerant capability based on the Clos–Knockout switch. In the new architecture, each stage has one more redundant switch module. If one switch module is faulty, the redundant module would replace the faulty one. On the other hand, under the fault‐free condition, the redundant modules in the second and third stages will provide additional alternative internal paths, and hence improve the performance. The performance analysis shows that the cell loss probability is lower than the original architecture when all modules are fault free, and the reliability of the original architecture is improved. Copyright © 2002 John Wiley & Sons, Ltd.     

Fast ping‐pong arbitration for input–output queued packet switches

Input–output queued switches have been widely considered as the most feasible solution for large capacity packet switches and IP routers. In this paper, we propose a ping‐pong arbitration scheme (PPA) for output contention resolution in input–output queued switches. The challenge is to develop a high speed and cost‐effective arbitration scheme in order to maximize the switch throughput and delay performance for supporting multimedia services with various quality‐of‐service (QoS) requirements. The basic idea is to divide the inputs into groups and apply arbitration recursively. Our recursive arbiter is hierarchically structured, consisting of multiple small‐size arbiters at each layer. The arbitration time of an n‐input switch is proportional to log₄?n/2? when we group every two inputs or every two input groups at each layer. We present a 256×256 terabit crossbar multicast packet switch using the PPA. The design shows that our scheme can reduce the arbitration time of the 256×256 switch to 11 gates delay, demonstrating the arbitration is no longer the bottleneck limiting the switch capacity. The priority handling in arbitration is also addressed. Copyright © 2001 John Wiley & Sons, Ltd.     

ATM在非均匀业务模式下的性能分析

本文通过对各种基于不同缓存结构和技术的ATM交换结构在非均匀业务模式下的性能进行分析,揭示了它们在不同业务模式下的性能差别,同时还给出了一种高性能的ATM交换网络的设计方法。     

A fast parallel-tree switch architecture for ATM networks

In this paper we present a novel fast packet switch architecture based on Banyan interconnection networks, called parallel-tree Banyan switch fabric (PTBSF). It consists of parallel Banyans (multiple outlets) arranged in a tree topology. The packets enter at the topmost Banyan. Internal conflicts are eliminated by using a conflict-free 3 × 4 switching element which distributes conflicting cells over different Banyans. Thus, cell loss may occur only at the lowest Banyan. Increasing the number of Banyans leads to a noticeable decrease in cell loss rate. The switch can be engineered to provide arbitrarily high throughput and low cell loss rate without the use of input buffering or cell pre-processing. The performance of the switch is evaluated analytically under uniform traffic load and by simulation, under a variety of asynchronous transfer mode (ATM) traffic loads. Compared to other proposed architectures, the switch exhibited stable and excellent performance with respect to cell loss and switching delay for all studied conditions as required by ATM traffic sources. The advantages of PTBSF are modularity, regularity, self-routing, low processing overhead, high throughput and robustness, under a variety of ATM traffic conditions. © 1998 John Wiley & Sons, Ltd.     

一种新型负载均衡交叉缓冲交换矩阵(英文)

The fast growth of Internet has created the need for high-speed switches. Recently, the crosspoint-queue switch has attracted attention because of its scalability and high performance. However, the Crosspoint-Queue switch does not perform well under non-uniform traffic. To overcome this limitation, the Load-Balanced Crosspoint-Queued switch architecture has been proposed. In this architecture, a load-balance stage is placed ahead of the Crosspoint-Queued stage. The load-balance stage transforms the incoming non-uniform traffic into nearly uniform traffic at the input port of the second stage. To avoid out-of-order cells, this stage employs flow-based queues in each crosspoint buffer. Analysis and simulation results reveal that under non-uniform traffic, this new switch architecture achieves a delay performance similar to that of the Output-Queued switch without the need for internal acceleration. In addition, its throughput is much better than that of the pure crosspoint-queued switch. Finally, it can achieve the same packet loss rate as the crosspoint-queue switch, while using a buffer size that is only 65% of that used by the crosspoint-queue switch.     

Power aware scalable multicast routing protocol for MANETs

Multicasting is an effective way to provide group communication. In mobile ad hoc networks (MANETs), multicasting can support a wide variety of applications that are characterized by a close degree of collaboration. Since MANETs exhibit severe resource constraints such as battery power, limited bandwidth, dynamic network topology and lack of centralized administration, multicasting in MANETs become complex. The existing multicast routing protocols concentrate more on quality of service parameters like end‐to‐end delay, jitter, bandwidth and power. They do not stress on the scalability factor of the multicast. In this paper, we address the problem of multicast scalability and propose an efficient scalable multicast routing protocol called ‘Power Aware Scalable Multicast Routing Protocol (PASMRP)’ for MANETs. PASMRP uses the concept of class of service with three priority levels and local re‐routing to provide scalability. The protocol also ensures fair utilization of the resources among the nodes through re‐routing and hence the lifetime of the network is increased. The protocol has been simulated and the results show that PASMRP has better scalability and enhanced lifetime than the existing multicast routing protocols. Copyright © 2005 John Wiley & Sons, Ltd.     

Scheduling of multicast traffic in high-capacity packet switches

Switches with input buffers are scalable due to their simplicity. In these switches, the port that sources a multicast session might easily get congested as it becomes more popular. We propose that destination ports should forward copies of multicast packets to other destination ports in a specified order. In this way, the multicast traffic load is evenly distributed over the switch ports. Packets are scheduled according to the weighted sequential greedy algorithm.     

Performance of a large multicast ATM switch

In this paper, we present the design of a large self-routing multicast ATM switch. The switch consists of a sorting network followed by a 3-stage routing network. We first present a simple design of a large sorting network built using small sized shared memory that can be used as a building block for a large sorting network. Small sized shared memory is also used in the 3-stage routing network making the switch modular and easy to implement using current VLSI technology. As the network uses shared memory modules, multicasting functionality is easily built into the network. The performance of the proposed network is compared with an equivalent completely shared memory switch using computer simulations under bursty traffic model. The results show that the proposed network has better performance in terms of cell loss ratio than the completely shared memory switch under moderate to heavy traffic load (0.6 ≤ effective offered load ≤ 1.2). Furthermore, multicast cell delays are drastically improved. This revised version was published online in June 2006 with corrections to the Cover Date.     

The Tera project: a hybrid queueing ATM switch architecture for LAN

The Tera ATM LAN project at Carnegie Mellon University addresses the interconnection of hundreds of workstations in the Electrical and Computer Engineering Department via an ATM-based network. The Tera network architecture consists of switched Ethernet clusters that are interconnected using an ATM network. This paper presents the Tera network architecture, including an Ethernet/ATM network interface, the Tera ATM switch, and its performance analysis. The Tera switch architecture for asynchronous transfer mode (ATM) local area networks (LAN's) incorporates a scalable nonblocking switching element with hybrid queueing discipline. The hybrid queueing strategy includes a global first-in first-out (FIFO) queue that is shared by all switch inputs and dedicated output queues with small speedup. Due to hybrid queueing, switch performance is comparable to output queueing switches. The shared input queue design is scalable since it is based on a Banyan network and N FIFO memories. The Tera switch incorporates an optimal throughput multicast stage that is also based on a Banyan network. Switch performance is evaluated using queueing analysis and simulation under various traffic patterns     

在CICQ交换结构下实现分布式的WFQ类加权公平调度算法

传统的基于crossbar的输入排队交换结构在提供良好的QoS方面存在很大的不足,而CICQ(Combined Input and Crosspoint buffered Queuing)交换结构与传统的交换结构相比,不但能在各种输入流下提供接近输出排队的吞吐率,而且能提供良好的QoS支持。该文基于CICQ结构,提出了在输入排队条件下实现基于流的分布式WFQ类分组公平调度算法的方案,并通过仿真验证了这一方案的有效性。