A comparative analysis and design of quantum‐dot cellular automata memory cell architecture

Quantum‐dot cellular automata (QCA) nanotechnology is considered as the best candidate for memory system owing to its dense packages and low power consumption. This paper analyzes the drawbacks of the previous QCA memory architectures and improves memory cell that exploits regular clock zone layout by employing two new clocking signals and a compact Read/Write circuit. The proposed layout is verified with the modified QCADesigner simulator and is analyzed by considering the noise effect. This design, occupying only a fraction of the area compared with the previous memory design, has superior performance. It is shown that the clock circuitry is very regular, helping manufacturability for physical implementation. Comparisons show that Read/Write latency of the proposed design is mitigated, the overall cell number, control cell and layout area are reduced (100%), and its performance against random charge noise is presented to be better. Copyright © 2010 John Wiley & Sons, Ltd.     

A neural network parallel algorithm for one‐dimensional gate assignment problems

A near‐optimum parallel algorithm for solving the one‐dimensional gate assignment problem is presented in this paper, where the problem is NP‐hard and one of the most fundamental layout problems in VLSI design. The proposed system is composed of n × n processing elements based on the artificial two‐dimensional maximum neural network for (n + 2)‐gate assignment problems. Our algorithm has discovered improved solutions in the benchmark problems compared with the best existing algorithms. The proposed approach is applicable to other VLSI layout problems such as the PLA (Programmable Logic Array) folding problem. © 1999 Scripta Technica, Electr Eng Jpn, 129(2): 71–77, 1999     

Design and analysis of power‐CMOS‐gate‐based switched‐capacitor DC–DC converter with step‐down and step‐up modes

A unified multi‐stage power‐CMOS‐transmission‐gate‐based quasi‐switched‐capacitor (QSC) DC–DC converter is proposed to integrate both step‐down and step‐up modes all in one circuit configuration for low‐power applications. In this paper, by using power‐CMOS‐transmission‐gate as a bi‐directional switch, the various topologies for step‐down and step‐up modes can be integrated in the same circuit configuration, and the configuration does not require any inductive elements, so the IC fabrication is promising for realization. In addition, both large‐signal state‐space equation and small‐signal transfer function are derived by state‐space averaging technique, and expressed all in one unified formulation for both modes. Based on the unified model, it is all presented for control design and theoretical analysis, including steady‐state output and power, power efficiency, maximum voltage conversion ratio, maximum power efficiency, maximum output power, output voltage ripple percentage, capacitance selection, closed‐loop control and stability, etc. Finally, a multi‐stage QSC DC–DC converter with step‐down and step‐up modes is made in circuit layout by PSPICE tool, and some topics are discussed, including (1) voltage conversion, output ripple percentage, and power efficiency, (2) output robustness against source noises and (3) regulation capability of converter with loading variation. The simulated results are illustrated to show the efficacy of the unified configuration proposed. Copyright © 2003 John Wiley & Sons, Ltd.     

An oscillatory noise‐shaped quantizer for time‐based continuous‐time sigma‐delta modulators

In this paper, a new type of an oscillatory noise‐shaped quantizer (NSQ) for time‐based continuous‐time sigma‐delta modulators is presented. The proposed NSQ is composed of an oscillatory voltage‐to‐time converter and a polyphase sampler. Using Tustin's transformation method and through the approximation of the comparator gain, a linearized model of the NSQ is introduced. This way, a novel realization of the first‐ and second‐order NSQ is presented. Its implementation is based on fully passive continuous‐time filters without needing any amplifier or power consuming element. The ploy‐phase sampler inside the NSQ is based on the combination of a time‐to‐digital and a digital‐to‐time converter. The layout of the proposed NSQ is provided in Taiwan Semiconductor Manufacturing Company 0.18 μm complementary metal‐oxide‐semiconductor 1P6M technology. The verification of the proposed NSQ is done via investigating both the system level and postlayout simulation results. Leveraging the proposed NSQ in an Lth‐order time‐based continuous‐time sigma‐delta modulator enhances the noise‐shaping order up to L + 2, confirming its superior effectiveness. This makes it possible to design high performance and wideband continuous‐time SDMs with low power consumption and relaxed design complexity.     

Analysis and design of a two‐transformer active‐clamping ZVS isolated inverse‐SEPIC converter

This paper presents a two‐transformer active‐clamping zero‐voltage‐switching (ZVS) isolated inverse‐SEPIC converter, which is mainly composed of two active‐clamping ZVS isolated inverse‐SEPIC converters. The proposed converter allows a low‐profile design for liquid crystal display TVs and servers. The presented two‐transformer active‐clamping ZVS isolated inverse‐SEPIC converter can equally share the total load current between two secondaries. Therefore, the output inductor copper loss and the output diode conduction loss can be decreased. Detailed analysis and design of this new two‐transformer active‐clamping ZVS isolated inverse‐SEPIC converter are described. Experimental results are recorded for a prototype converter with an AC input voltage ranging from 85 to 135 V, an output voltage of 12 V and a rated output current of 13.5A, operating at a switching frequency of 65 kHz. Copyright © 2012 John Wiley & Sons, Ltd.     

Gradient‐based optimization using parametric sensitivity macromodels

A new method for gradient‐based optimization of electromagnetic systems using parametric sensitivity macromodels is presented. Parametric macromodels accurately describe the parameterized frequency behavior of electromagnetic systems and their corresponding parameterized sensitivity responses with respect to design parameters, such as layout and substrate parameters. A set of frequency‐dependent rational models is built at a set of design space points by using the vector fitting method and converted into a state‐space form. Then, this set of state‐space matrices is parameterized with a proper choice of interpolation schemes, such that parametric sensitivity macromodels can be computed. These parametric macromodels, along with the corresponding parametric sensitivity macromodels, can be used in a gradient‐based design optimization process. The importance of parameterized sensitivity information for an efficient and accurate design optimization is shown in the two numerical microwave examples. Copyright © 2012 John Wiley & Sons, Ltd.     

Self‐calibrated SAR ADC based on split capacitor DAC without the use of fractional‐value capacitor

A successive approximation register analog‐to‐digital converter (SAR ADC) based on a split‐capacitor digital‐to‐analog converter (CDAC) with a split binary weighted capacitor array and C‐2C ladder is proposed. In present design, a unit split capacitor is used in the CDAC instead of the fractional‐value capacitor in the conventional configuration. The preset error induced by the unit split capacitor and the mismatch error of the upper bit CDAC are self‐calibrated. The calibration range and the impact of calibration DAC resolution on circuit linearity are studied to provide an optimum design guideline. Behavior simulation and post‐layout simulation are performed to verify the proposed calibration method. © 2013 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Cost reduction in bottom‐up hierarchical‐based VLSI floorplanning designs

From the industrial perspective, floorplanning is a crucial step in the VLSI physical design process as its efficiency determines the quality and the time‐to‐market of the product. A new perturbation method, called Cull‐and‐Aggregate Bottom‐up Floorplanner (CABF), which consists of culling and aggregating stages, is developed to perform variable‐order automated floorplanning for VLSI. CABF will generate VLSI floorplan layout by calculating the modules' dimensions' differences (hard module floorplanning problems) and the modules' areas' differences (soft module floorplanning problems). Through mathematical derivation, the hard modules floorplanning area minimization cost function (two‐dimensional) during culling stage is proven that a dimensional reduction can be carried out to be the difference‐based cost function (one‐dimensional) which simplifies the computation. During the culling stage, CABF employs linear ordering method to select and determine the order of modules where this linear runtime complexity property allows CABF to cull the modules faster. The aggregating stage of CABF will reduce the subsequent search space of this floorplanner, and the variable order aggregation enables CABF to search for the best near‐optimal solution. Based on Gigascale Systems Research Center and Microelectronics Center of North Carolina circuit benchmarks, CABF gives better optimal solutions and faster runtimes for floorplanning problems involving 9 to 600 modules. This has established that CABF is performing well in respect of reliability and scalability. Besides, CABF shows its potential to be implemented in VLSI physical design as the runtime of CABF is faster with a near‐optimal outcome as compared to the other existing algorithms. Copyright © 2013 John Wiley & Sons, Ltd.     

Multi‐template approach to realize central pattern generators for artificial locomotion control

Biologically inspired control of artificial locomotion often makes use of the concept of central pattern generator (CPG), a network of neurons establishing the locomotion pattern within a lattice of neural activity. In this paper a new approach, based on cellular neural networks (CNNs), for the design of CPGs is presented. From a biological point of view this new approach includes an approximated chemical synapse realized and implemented in a CNN structure. This allows to extend the results, previously obtained with a reaction‐diffusion‐CNN (RD‐CNN) for the locomotion control of a hexapod robot, to a more general class of artificial CPGs in which the desired locomotion pattern and the switching among patterns are realized by means of a spatio‐temporal algorithm implemented in the same CNN structure. Copyright © 2002 John Wiley & Sons, Ltd.     

Low‐power,low‐noise,active‐RC band‐pass filters using a ‘lossy’ LP–BP transformation

A new and straightforward design procedure for simple canonical topologies of allpole, active‐RC, low‐selectivity band‐pass (BP) filters, with low sensitivity to component tolerances is presented. The procedure is primarily intended for discrete‐component, low‐power filter applications using just one amplifier for relatively high‐order filters. The design procedure starts out with an ‘optimized’ low‐pass (LP) prototype filter, yielding an ‘optimized’ BP filter, whereby the wealth of ‘optimized’ single‐amplifier LP filter designs can be exploited. Using a so‐called ‘lossy’ LP–BP transformation, closed‐form design equations for the design of second‐ to eighth‐order, single‐amplifier BP filters are presented. The low sensitivity, low power consumption, and low noise features of the resulting circuits, as well as the influence of the finite gain‐bandwidth product and component spread, are demonstrated for the case of a fourth‐order filter example. The optimized single‐opamp fourth‐order filter is compared with other designs, such as the cascade of optimized Biquads. Using PSpice with a TL081 opamp model, the filter performance is simulated and the results compared and verified with measurements of a discrete‐component breadboard filter using 1% resistors, 1% capacitors, and a TL081 opamp. Copyright © 2011 John Wiley & Sons, Ltd.     

Gain compression improvement on low‐power cascaded current reuse LNAs

Current reuse low‐noise‐amplifiers (CRLNAs) have been the norm to achieve high‐gain and low‐noise figure under low‐power budgets. However, conventional CRLNAs suffer from a severe lack of large‐signal linearity, especially in conventional cascaded CRLNAs. This main drawback is related with the typical biasing method imposed in the output stage. To prove our point, a large‐signal study is performed for a single stage common‐source in two distinct biasing situations: voltage biased and current biased. On the basis of the gathered results, a new CRLNA solution is proposed to relief the large‐signal bottleneck. The suggested design is analyzed in a 0.13 µm complementary metal–oxide–semiconductor (CMOS) standard process. Post‐layout simulations show 8 dB compression point improvement compared with the conventional CRLNA solution. The CRLNA draws a current of 650 μA from a 1.2 V supply. At 2.45 GHz, a power gain of 25.3 dB and a NF of 2.3 dB are achieved, while the IIP3 is ?9 dBm. Copyright © 2016 John Wiley & Sons, Ltd.     

A common‐mode replica compensated inductor–capacitor voltage‐controlled oscillator for mixed‐signal system‐on‐chip applications

A novel 1.57 GHz complementary metal–oxide semiconductor inductor–capacitor voltage‐controlled oscillator with the common‐mode replica compensation is introduced for mixed‐signal system‐on‐chip applications. In order to alleviate power line disturbances, the center tap node of differential symmetric inductor and the replica biasing circuit are adopted in the differential voltage regulating unit to reduce power supply sensitivity. In addition, this proposed design also leads to low tuning gain and low power dissipation. The post‐layout simulation results under the Taiwan Semiconductor Manufacturing Company's mixed‐signal 0.18 µm 1P6M process show that the proposed design achieves power supply rejection of ?68.6 dB at low frequencies and 1.2 MHz/V pushing sensitivity. It exhibits phase noise of ?130.6 dBc/Hz at a 1 MHz offset from a 1.57 GHz carrier yet dissipates only 5.58 mW under a 1.8 V power supply. Copyright © 2011 John Wiley & Sons, Ltd.     

Three‐stage multiphase‐switched‐capacitor boost DC‐AC inverter

A closed‐loop scheme of a three‐stage multiphase‐switched‐capacitor boost DC‐AC inverter (MPSCI) is proposed by combining the multiphase operation and sinusoidal‐pulse‐width‐modulation (SPWM) control for low‐power step‐up DC‐AC conversion and regulation. In this MPSCI, the power unit contains two parts: MPSC booster (front) and H‐bridge (rear). The MPSC booster is suggested for an inductor‐less step‐up DC‐DC conversion, where three voltage doublers in series are controlled with multiphase operation for boosting voltage gain up to 2³ = 8 at most. The H‐bridge is employed for DC‐AC inversion, where four solid‐state switches in H‐connection are controlled with SPWM to obtain a sinusoidal AC output. In addition, SPWM is adopted for enhancing output regulation not only to compensate the dynamic error, but also to reinforce robustness to source/loading variation. The relevant theoretical analysis and design include: MPSCI model, steady‐state/dynamic analysis, voltage conversion ratio, power efficiency, stability, capacitance selection, total harmonic distortion (THD), output filter, and closed‐loop control design. Finally, the closed‐loop MPSCI is simulated, and the hardware circuit is implemented and tested. All the results are illustrated to show the efficacy of the proposed scheme. Copyright © 2011 John Wiley & Sons, Ltd.     

Compact CMOS implementation of a low‐power,current‐mode programmable cellular neural network

We report on the design and characterization of a full‐analog programmable current‐mode cellular neural network (CNN) in CMOS technology. In the proposed CNN, a novel cell‐core topology, which allows for an easy programming of both feedback and control templates over a wide range of values, including all those required for many signal processing tasks, is employed. The CMOS implementation of this network features both low‐power consumption and small‐area occupation, making it suitable for the realization of large cell‐grid sizes. Device level and Monte Carlo simulations of the network proved that the proposed CNN can be successfully adopted for several applications in both grey‐scale and binary image processing tasks. Results from the characterization of a preliminary CNN test‐chip (8×1 array), intended as a simple demonstrator of the proposed circuit technique, are also reported and discussed. Copyright © 2001 John Wiley & Sons, Ltd.     

νMOS cellular‐automaton circuit for picture thinning and shrinking

In this study we propose a design for an LSI circuit that implements a cellular automaton. The cellular automaton is a parallel and distributed architecture device suitable for high‐speed image processing. To develop a cellular automaton LSI circuit, it is necessary to design small‐size unit cell circuits that can operate according to cell–cell interaction rules. We propose to use νMOSFET devices for such cell circuits. Template matching is implemented by combining multiple input νMOSFET circuits and inverters. A cell circuit was designed for image thinning and shrinking, and its operation was analyzed using a circuit simulator. It was demonstrated that high speed operation (up to 100 MHz clock frequency) can be obtained. © 1999 Scripta Technica, Electr Eng Jpn, 126(3): 41–48, 1999     

Survey of integrated‐circuit‐oscillator phase‐noise analysis

This tutorial distills the salient phase‐noise analysis concepts and key equations developed over the last 75 years relevant to integrated circuit oscillators. Oscillator phase and amplitude fluctuations have been studied since at least 1938 when Berstein solved the Fokker–Planck equations for the phase/amplitude distributions of a resonant oscillator. The principal contribution of this work is the organized, unified presentation of eclectic phase‐noise analysis techniques, facilitating their application to integrated circuit oscillator design. Furthermore, we demonstrate that all these methods boil down to obtaining three things: (1) noise modulation function; (2) noise transfer function; and (3) current‐controlled oscillator gain. For each method, this paper provides a short background explanation of the technique, a step‐by‐step procedure of how to apply the method to hand calculation/computer simulation, and a worked example to demonstrate how to analyze a practical oscillator circuit with that method. This survey article chiefly deals with phase‐noise analysis methods, so to restrict its scope, we limit our discussion to the following: (1) analyzing integrated circuit metal–oxide–semiconductor/bipolar junction transistor‐based LC, delay, and ring oscillator topologies; (2) considering a few oscillator harmonics in our analysis; (3) analyzing thermal/flicker intrinsic device‐noise sources rather than environmental/parametric noise/wander; (4) providing mainly qualitative amplitude‐noise discussions; and (5) omitting measurement methods/phase‐noise reduction techniques. Copyright © 2013 John Wiley & Sons, Ltd.     

Analysis and design of a two‐transformer active‐clamping forward converter with parallel‐connected current doubler rectifiers

A new two‐transformer active‐clamping forward converter with parallel‐connected current doubler rectifiers (CDRs) is proposed in this paper. The presented DC–DC converter is mainly composed of two active‐clamping forward converters with secondary CDRs. Only two switches are required and each one is the auxiliary switch for the other. The circuit complexity and cost are thus reduced. The leakage inductance of the transformer or an additional resonant inductance is employed to achieve zero‐voltage‐switching (ZVS) during the dead times. Two CDRs at the secondary side are connected in parallel to reduce the current stresses of the secondary windings and the ripple current at the output side. Accordingly, the smaller output chokes and capacitors decrease the converter volume and increase the power density. Detailed analysis and design of the presented two‐transformer active‐clamping forward converter are described. Experimental results are recorded for a prototype converter with a DC input voltage of 130??180V, an output voltage of 5 V and an output current of 40 A, operating at a switching frequency of 100 kHz. Copyright © 2010 John Wiley & Sons, Ltd.     

Novel quantum‐dot cellular automata implementation of flip‐flop and phase‐frequency detector based on nand‐nor‐inverter gates

CMOS technology faces fundamental challenges such as frequency and power consumption due to the impossibility of further reducing dimensions. For these reasons, researchers have been thinking replacement of this technology with other technologies such as quantum‐dot cellular automata (QCA) technology. Many studies have been done to design digital circuits using QCA technology. Phase‐frequency detector (PFD) is one of the main blocks in electrical and communication circuits. In this paper, a novel structure for PFDs in QCA technology is proposed. In the proposed design, the novel D flip‐flop (D‐FF) with reset ability is used. The D‐FF is designed by the proposed D latch which is based on nand‐nor‐inverter (NNI) and an inverter gate. This proposed D latch has 22 cells and 0.5 clock cycle latency and 0.018‐μm² area. The inverter gate of the D‐FF has output signal with high polarization level and lower area than previous inverters, and the NNI gate of the D‐FF is a universal gate. The proposed PFD has 141 cells, 0.17‐μm² occupied area, and two clock cycle latency that is smaller compared with PFD and is based on common inverter and majority gates.     

A design method of a generalized predictive control system based on parametrization of two‐degree‐of‐freedom integral controllers

A new design method for a generalized predictive control (GPC) system based on parametrization of two‐degree‐of‐freedom integral controllers has been proposed. The objective is to guarantee stability of the control system without depending on the design parameters and to achieve low sensitivity against the plant perturbation and the disturbance. The design procedure consists of two steps. First, we design a basic integral controller for a nominal plant using the linear quadratic Gaussian (LQG) method and parametrize a class of two‐degree‐of‐freedom stabilizing controllers. Next, we tune the feedforward controller to incorporate the GPC method into our control structure. A numerical example is presented to show the effectiveness of the proposed method by comparing it with the conventional GPC method. © 1999 Scripta Technica, Electr Eng Jpn, 129(2): 62–70, 1999     

A linearized and low noise CMOS mixer with B‐type amplifier‐based sub‐harmonic balun

A low noise and high linearity down‐conversion CMOS mixer for 2.4‐GHz wireless receiver is presented in this paper. Using a sub‐harmonic balun with a simple but effective B‐type amplifier, the local oscillator frequency required for this mixer has been reduced by half, and the input local oscillator signal could be single‐ended rather than differential, which simultaneously simplifies the design of local oscillator. A distortion and noise cancelation transconductor in association with current bleeding technique is employed to improve the noise and linearity of the entire mixer under a reduced bias current without compromising the voltage gain. Fabricated in a 0.18‐µm RF CMOS technology of Global Foundries, the mixer demonstrates a voltage gain of 15.8 dB and input‐referred third‐order intercept point of 6.6 dBm with a noise figure of 2.6 dB. It consumes 7.65 mA from a 1.0‐V supply and occupies a compact area of 0.75 × 0.71 mm² including all test pads. Copyright © 2016 John Wiley & Sons, Ltd.