Substrate noise measurement by using noise-selective voltagecomparators in analog and digital mixed-signal integrated circuits

In mixed-signal integrated circuits (IC's), substrate noise produced by high-speed digital circuits passes to the on-chip analog circuits through the substrate and seriously degrades their performance. We have developed a method for measuring the substrate noise by using noise-selective chopper-type voltage comparators as noise detectors. This method can detect the wide-band substrate noise so we can analyze and further reduce its effect. A switched capacitance is selectively loaded on the output of the inverter amplifier of the comparator during the comparison period in order to reduce the noise detected at the transition from compare to auto-zero. In contrast, the noise at the transition from auto-zero to compare can be selectively detected. Waveforms of high-frequency substrate noise were reconstructed by using this on-chip-noise detector incorporating the noise-selective comparators implemented using a 0.5-μm CMOS bulk process     

基于模拟信号源的机载BDS接收机性能测试

针对机载北斗卫星导航系统(BDS)接收机无法进行实际测试的问题,基于对机载BDS接收机的首次定位时间(TTFF)、重捕时间和定位精度的分析与仿真,研究某一指标与相关参数的关系,提出利用全球导航卫星系统(GNSS)模拟信号源测试机载BDS接收机性能指标的测试方法。该方法结合真实飞行数据,利用GNSS模拟信号源模拟飞机运动过程,从而对飞行过程中机载BDS接收机的关键指标进行测试。测试结果表明:机载BDS接收机的首次定位时间满足RTCA DO-208对TTFF不大于5 min的要求;重捕时间基本满足TSO-C146d对重捕时间不大于20 s的要求;静态误差满足北斗公开服务性能规范对其不大于10 m的要求,动态误差基本满足RTCA DO-208对其小于230 m的要求,且测试结果均符合理论分析。     

A complete scheme of built-in self-tests (BIST) structure for faultdiagnosis in analog circuits and systems

The implementation of BIST in analog circuits is investigated, and a complete BIST scheme is proposed. This scheme can be included in any analog or mixed analog-digital circuit and can check its responses by following selected testing procedures. A CMOS chip supporting the proposed BIST structure is designed to facilitate the application of the scheme in a variety of analog circuits. Results from the application of the BIST scheme on active circuits are given, showing its effectiveness and its convenience     

A framework for design and testing of analog integrated circuits

A global methodology for analog and mixed analog-to-digital VLSI design requires close interaction between simulations, CAD tools, measurements, and testing. An integrated hardware and software environment (framework) that implements this methodology in a systematic way is described. As an example of its application, the modeling of errors in multistage analog-to-digital converters (ADCs) is described. The framework has a unique software organization designed to facilitate the interpretation of measurement results and the feedback of information to the design world. The perfectly modular nature of the software makes it easy to gain a fundamental understanding of error mechanisms. In the ADC example, this understanding eliminates the need to probe internal parts of a circuit since information on internal errors can be recovered from external measurements     

The test needs of application-specific integrated circuits

This paper discusses the particular test needs of non-standard, application-specific integrated circuits (ASICs). It covers the need for accurate device simulation integrated with a post-processor and test system software, to enable cost-effective testing to be performed.     

Reliability predictions for integrated circuits from test structure data

For the prediction of product reliability from test structure data the observed times to failure have to be fitted to an assumed probability distribution and extrapolated to small failure probabilities. And the probability distribution for the (small) test structure size has to be extrapolated to the corresponding distribution for the (larger) product size. With respect to the probability distribution it is shown that even in the ‘defect’ dominated case, extreme value distributions do not have to apply. This leads to considerable extrapolation uncertainties. For the size extrapolation of test structure data to the product the degree of dependence between times to failure of substructures on the same chip is of crucial importance. It can change the predicted reliability by orders of magnitude. A model describing this dependence is given and analyses yielding the required information are suggested.     

Automated selection of test frequencies for fault diagnosis in analog electronic circuits

This paper suggests three novel methods for selecting the frequencies of sinusoidal test signals to be used in fault diagnosis of analog electronic circuits. The first and second methods are based on a sensitivity analysis and show to be particularly effective in linear circuits where a priori information and designer experience can be exploited. Conversely, the third method selects the input frequencies to be used for diagnostic purposes without requiring any hypothesis about the circuit or testing design background. As such, the method is particularly appealing in complex -possibly nonlinear - circuits where the designer experience is of little value and an effective "blind" approach saves both designer and testing time. The suggested frequency selection methods are then contrasted to each other against performance and computational complexity.     

Fast and reliable top-level simulation strategy for mixed-signal integrated circuits and its application to DC?DC converters

Top-level, transient, transistor-based simulations are a critical step in the product-development cycle of mixed-signal integrated circuits. These simulations are normally performed just before fabrication and unfortunately impose cumbersome bottlenecks in the design flow. Verification is an iterative process by nature, whereby each problem found requires another simulation to ensure a proper fix is in place, and because of the complexity of a large system, minor errors can cost days, increasing design time and time-to-market. A top-level transistor-based simulation strategy is proposed with minimal time overhead. The strategy is to start with a quick, all macro-model system simulation and gradually substitute one transistor-level sub-block at a time for each additional run. For optimal results, less computationally intensive blocks, which can be determined from a proposed set of screening simulations, are replaced first. The proposed strategy was tested and applied to a buck, current-mode switching regulator, and the results show that simulation overhead is least for linear analogue functions (e.g. op-amps) and worst for high-speed nonlinear circuits (e.g. signal generators). Nonlinear and bi-stable analogue blocks such as bandgap references take more time to simulate than op-amps and less than low frequency digital functions such as power-on-reset, which in turn are less intensive than ramp and pulse generators     

Extremely bendable, high-performance integrated circuits using semiconducting carbon nanotube networks for digital, analog, and radio-frequency applications

Solution-processed thin-films of semiconducting carbon nanotubes as the channel material for flexible electronics simultaneously offers high performance, low cost, and ambient stability, which significantly outruns the organic semiconductor materials. In this work, we report the use of semiconductor-enriched carbon nanotubes for high-performance integrated circuits on mechanically flexible substrates for digital, analog and radio frequency applications. The as-obtained thin-film transistors (TFTs) exhibit highly uniform device performance with on-current and transconductance up to 15 μA/μm and 4 μS/μm. By performing capacitance-voltage measurements, the gate capacitance of the nanotube TFT is precisely extracted and the corresponding peak effective device mobility is evaluated to be around 50 cm(2)V(-1)s(-1). Using such devices, digital logic gates including inverters, NAND, and NOR gates with superior bending stability have been demonstrated. Moreover, radio frequency measurements show that cutoff frequency of 170 MHz can be achieved in devices with a relatively long channel length of 4 μm, which is sufficient for certain wireless communication applications. This proof-of-concept demonstration indicates that our platform can serve as a foundation for scalable, low-cost, high-performance flexible electronics.     

Implementation of a redox microarray: an experimental model for future nanoscale biomolecular computing using integrated circuits

The possibility of constructing high-density parallel computing architectures using molecular electronics technology is explored. By employing molecular computing devices, new circuitsystem integration could be realised. To clarify the proposed concept, an experimental model of a redox microarray is presented. A first experimental system for a redox microarray consists of a two-dimensional array of platinum microelectrodes to catalyse reversible reactions of redox-active molecules. Experimental results of active wave propagation in the redox microarray are presented to demonstrate the potential of molecular computing devices for creating artificially programmable reaction-diffusion dynamics for specific target applications.     

蓄电池综合参数自动测试仪校准方法的研究

蓄电池综合参数自动测试仪是集充电、放电、单体监测于一体的设备,现广泛用于蓄电池的生产企业和电动自行车、电动助力车、电动摩托车销售商,主要检测蓄电池的技术参数是否符合要求。为确保蓄电池综合参数自动测试仪量值传递的准确统一,通过对蓄电池综合参数自动测试仪校准方法的研究,实现对该设备计量特性的评定,该成果已作为地方计量技术规范发布实施。     

Stress test optimization using an integrated production test and field reliability model

Numerous papers and texts have been written in the reliability literature regarding the determination of the optimum test duration for a production stress or a burn‐in test. The techniques presented have largely been based on the identification of the change point at which infant mortality has largely been removed from the units. The time‐on‐test is typically the only factor that influences this decision. Few of these models have attempted to integrate the field performance or the influence of warranty costs into this decision. This paper proposes and validates a methodology that integrates the influence of the production test failures and the field performance including their respective costs into a single unified model. The objective is to identify a production test duration that minimizes the overall cost. A Weibull model is initially developed for the production test that incorporates the failure observations in different time segments of the test based on the ability to detect latent defects in the product. A separate Weibull model is then developed for the product's performance in the field that includes the lifetime of the unit. This paper identifies how both these Weibull models can be combined into a single model including both test and field costs with the objective of minimizing the overall cost. The advantage of the proposed technique is that it does not require one to track individual units from production through to the field in order to develop an integrated test and field cost model. Copyright © 2009 John Wiley & Sons, Ltd.     

Imaging flaws in soldered joints of integrated circuits using an ultrasound electronic scanning technique

An electronic scanning c-scopic 25-MHz ultrasonic imaging system has been developed for high-speed precise testing of electronic parts such as ICs. Two-dimensional scanning is performed, one axis being electronic and the other mechanical. A focused beam is formed so as to be a longitudinal wave in solid samples. Voids equal to or larger than 0.2 mm in diameter in the solder are accurately detected and their sizing data agree within 0.1 mm with those measured visually through an optical microscope after destruction. The imaging performance was examined for fatigue cracks in soldered joints. In 1000 heat cycles between -55 and +150 degrees C, cracks resulted in the soldered joints of most samples, and their growth was clearly visible. By comparing the images with those observed by a scanning electron microscope, minimum cracks of 1-mum separation were found to be detectable. The c-scan imaging of a 14x14 mm area of the joints was completed in 1.2 s by the system.     

Reliability challenges for low voltage/low power integrated circuits

This review paper discusses reliability considerations for low voltage/low power integrated circuit technologies. This growing market will continue to be dominated by scaled CMOS, with silicon on insulator technology growing in importance due to improved performance and reliability over bulk, low power CMOS. Power dissipation, performance, and reliability will be traded off at all levels of system design; this paper concentrates on device level issues. An aggressive low voltage/low power technology development path could yield a CMOS/SOI technology with 40 nm junctions, 5 nm gate oxides, and 0·9 V supplies. Such an aggressive low voltage/low power technology alters many traditional reliability problems such as metallization failure, oxide breakdown, hot carrier effects, electrostatic discharge, leakage currents, soft errors and analogue circuit noise. SOI brings additional reliability concerns such as heat dissipation through the buried oxide, bipolar latch, and back interface effects. This paper examines several of these issues and identifies a number of present and future reliability challenges for low voltage/low power technology.     

Simple,inexpensive temperature controller,using integrated circuits for cryogenic experiments

A simple and efficient temperature controller suitable for experiments at cryogenic temperatures is described. The controlling efficiency in the temperature range from 77 to 300 K has been found to be better than ± 20 mK.     

基于改进烟花算法的非线性模拟电路测试激励优化

为增强非线性模拟电路故障诊断中故障模式之间的可辨识性,提高故障诊断率,提出一种基于改进烟花算法的非线性模拟电路测试激励优化方法。该方法首先采用基于Volterra频域核和BP神经网络的方法对非线性模拟电路进行建模,进而针对烟花算法存在寻优速度慢、效率低等问题,对其爆炸算子、变异算子、选择策略等进行改进,采用改进后的烟花算法对非线性模拟电路的测试激励进行寻优,通过电路仿真表明,优化后的信号可有效提高故障可分性,从而提高故障诊断率。     

Application of Ti: W barrier metallization for integrated circuits

Aluminum metallization is the most widely used for contacts and interconnections in integrated circuits. However, the solid state diffusion of aluminum in silicon during contact sintering or high temperature packaging can result in junction shorting or leakage in shallow (<1 μm) emitter-base junction devices. The interposition of a barrier metal between the aluminum and the silicon is one solution to this problem. A sputter-deposited pseudo-alloy of Ti:W (10:90 wt.%) with PtSi contacts is suitable for this application. Resistivity ratio measurements on SiO₂/ ti:W/Al film test samples have shown that the resistivity of aluminum increases owing to diffusion of titanium or tungsten into the aluminum. However, the kinetic data show that no more than a 10% increase in the resistivity of the aluminum can be expected in the useful life of a device. High current stress data show that Ti:W/Al interconnections are comparable with those of aluminum films. Auger depth profiling of si/Ti:W/Al samples annealed at 450, 500 and 550°C in N₂ shows no aluminum at the Si-(Ti:W) interface. Application of the PtSi/Ti:W/Al metallization system for large-scale integrated circuits is described.