Constraint Based Criteria: An Approach for Test Case Selection in the Structural Testing

The selection of test cases to satisfy a structural testing criterion is a very important task because it concerns the quality of the generated test cases. The question is “How to select a test case or path to cover an element required by a structural criterion?” The Constraint Based Criteria are proposed with the goal of answering this question and improving the efficacy, that is, the number of revealed faults. These criteria permit the use of different testing strategies by associating constraints to the required elements. The constraints describe faults generally not revealed by the structural technique. The Constraint Based Criteria can also be used to assess test data sets adequacy.     

COMBINATORIAL DESIGN APPROACHES FOR TEST GENERATION

The n-way combination testing is a specification-based testing criterion, which requires that for a system consisted of a few parameters, every combination of valid values of arbitrary n(n ≥ 2) parameters be covered by at least one test. This letter proposed two different test generation algorithms based on combinatorial design for the n-way coverage criterion. The automatic test generators are implemented and some valuable empirical results are obtained.     

软件先验知识和基于测试的可靠性评估关系研究

软件测试能够为软件可靠性提供一种运行前评估．为减少达到一定可靠性目标所需要的测试用例的数量，普遍认为可以将软件的先验知识综合到基于测试的可靠性估计模型中．目前已经提出几种理论模型但是少有试验验证．本文对测试系统的定义进行了扩展，从规范、实现和测试之间的关系，研究了影响软件测试有效性的因素，并通过试验验证了基于贝塔分布模型的先验知识和基于PAC模型的先验知识在可靠性估计中的作用．本文的结论认为是软件的易测性特征而不是先验知识的多少决定了达到一定可靠性目标所需的测试用例数量．该结论有助于理解软件设计对于测试有效性的影响．     

COMBINATORIAL DESIGN APPROACHES FOR AUTOMATIC TEST GENERATION

The n-way combination testing is a specification-based testing criterion, which requires that for a system consisted of a few parameters, every combination of valid values of arbitrary n(n ≥ 2) parameters be covered by at least one test. This letter proposed two different test generation algorithms based on combinatorial design for the n-way coverage criterion. The automatic test generators are implemented and some valuable empirical results are obtained.     

Hardware Generation of Random Single Input Change Test Sequences

The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. As delay testing using external testers requires expensive ATE, built-in self test (BIST) is an alternative technique that can significantly reduce the test cost.It has been proven that Single Input Change (SIC) test sequences are more effective than classical Multiple Input Change (MIC) test sequences when a high robust delay fault coverage is targeted. It has also been shown that random SIC (RSIC) test sequences achieve a higher fault coverage than random MIC (RMIC) test sequences when both robust and non robust tests are under consideration; the experimental results were based on a software generation of RSIC sequences that are easily generated.Obviously, a hardware RSIC generation providing similar results can be obtained. However, this hardware generator must be carefully designed. In this paper, it is explained what are the criteria which must be satisfied for this purpose. A solution is proposed and illustrated with an example. Then, it is shown that a bad result may be obtained if one of these criteria is not satisfied.     

A Comprehensive Empirical Study of Count Models for Software Fault Prediction

Count models, such as the Poisson regression model, and the negative binomial regression model, can be used to obtain software fault predictions. With the aid of such predictions, the development team can improve the quality of operational software. The zero-inflated, and hurdle count models may be more appropriate when, for a given software system, the number of modules with faults are very few. Related literature lacks quantitative guidance regarding the application of count models for software quality prediction. This study presents a comprehensive empirical investigation of eight count models in the context of software fault prediction. It includes comparative hypothesis testing, model selection, and performance evaluation for the count models with respect to different criteria. The case study presented is that of a full-scale industrial software system. It is observed that the information obtained from hypothesis testing, and model selection techniques was not consistent with the predictive performances of the count models. Moreover, the comparative analysis based on one criterion did not match that of another criterion. However, with respect to a given criterion, the performance of a count model is consistent for both the fit, and test data sets. This ensures that, if a fitted model is considered good based on a given criterion, then the model will yield a good prediction based on the same criterion. The relative performances of the eight models are evaluated based on a one-way anova model, and Tukey's multiple comparison technique. The comparative study is useful in selecting the best count model for estimating the quality of a given software system     

Hierarchical Delay Test Generation

Delay testing is used to detect timing errors in a digital circuit.In this paper, we report a tool called MODET forautomatic test generation for path delay faults in modular combinational circuits. Our technique usesprecomputed robust delay tests for individual modules to computerobust delay tests for the module-level circuit. We present alongest path theorem at the module level ofabstraction which specifies the requirements for path selectionduring delay testing. Based on this theorem, we propose a pathselection procedure in module-level circuits and report efficientalgorithms for delay test generation. MODET hasbeen tested against a number of hierarchical circuits with impressivespeedups in relation to gate-level test generation.     

基于XML结构的C语言考试的自动评分系统

在C程序设计语言考试中为了解决定位难、一题多解和对于主观题没有统一的评价标准的情况,对考试系统中客观题和程序题的评分方法进行了研究。在比较结果的评分基础上,引入了XML结构的答案库,以及使用了黑盒测试方法与抽取骨架的方法,成功地解决了上述问题。在设计系统的过程中,十分注重软件的实用性。该系统设计成功后,通过在小范围内使用,初步实验结果证明自动评分模块运行稳定,评分标准能够统一。     

一种变异测试中冗余变异体的寻找方法

变异测试是一种有效的基于故障的测试方法,但大量冗余变异体所带来的昂贵的测试成本问题,阻碍了它在实际工程开发中的应用.为解决该问题,本文针对程序中的顺序语句所产生的变异体,基于故障的可达-感染-传播模型,提出了使用区间抽象域来表示程序状态,通过区间运算判断变异体之间冗余关系的算法;针对程序中的条件语句,基于谓词故障层级,分别给出了面向简单谓词和复合谓词的冗余变异体选择算法.并对这两种算法对冗余变异体的判定效果进行了分析,最后给出了在分层抽样背景下,非冗余变异体生成的约束边界条件.对Siemens和开源项目等共8个工程进行了实验,并与随机选择法进行了对比.结果表明,本文所提方法在减少变异测试时间成本的同时,可以保持较高的变异得分.     

ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions

This paper presents a comparative analysis of ADOFs (Address Decoder Open Faults) and resistive-ADOFs in embedded-SRAMs. Such faults are the primary target of this study because they are hard-to-detect faults. These faults are caused by some particular defects which may appear in the parallel transistor network of the logic gates in the address decoders. With this study, we show that the test conditions required for ADOFs testing (sensitization and observation) are also useful for resistive-ADOFs detection, but more stringent timing requirements are needed. In the last part of the paper, we propose a study on the conditions to detect ADOFs with March tests. Moreover, we propose new March elements, which are effective for ADOF testing, and which can be added to existing March tests. *This work has been partially funded by the French government under the framework of the MEDEA+ A503 “ASSOCIATE” European program.     

Balance testing and balance-testable design of logic circuits

We propose a low-cost method for testing logic circuits, termed balance testing, which is particularly suited to built-in self testing. Conceptually related to ones counting and syndrome testing, it detects faults by checking the difference between the number of ones and the number of zeros in the test response sequence. A key advantage of balance testing is that the testability of various fault types can be easily analyzed. We present a novel analysis technique which leads to necessary and sufficient conditions for the balance testability of the standard single stuck-line (SSL) faults. This analysis can be easily extended to multiple stuck-line and bridging faults. Balance testing also forms the basis for design for balance testability (DFBT), a systematic DFT technique that achieves full coverage of SSL faults. It places the unit under test in a low-cost framework circuit that guarantees complete balance testability. Unlike most existing DFT techniques, DFBT requires only one additional control input and no redesign of the underlying circuit is necessary. We present experimental results on applying balance testing to the ISCAS 85 benchmark circuits, which show that very high fault coverage is obtained for large circuits even with reduced deterministic test sets. This coverage can always be made 100% either by adding tests or applying DFBT.This research was supported by the National Science Foundation under Grant No. MIP-9200526. Parts of this paper were published in preliminary form in Proc. 23rd Symp. Fault-Tolerant Computing, Toulouse, June 1993, and in Proc. 31st Design Automation Conf, San Diego, June 1994.     

基于脚本的自动化软件测试框架

为缩短测试周期,提高软件自动化测试的效率,设计了一种自动化测试模型,在模型框架内根据测试场景定制自动化测试程序。通过框架内组件的复用,达到快速开发自动化测试程序的目的。该自动化软件测试框架模型采用了脚本技术、关键字驱动测试技术以及可扩展标记语言(XML)技术,有效提高了测试效率,减轻了测试人员的工作压力,提高了测试资产的利用率,增强了脚本的可维护性,缩短了自动化测试的准备时间。基于该框架的自动化测试程序已经在一些小型项目中得到初步应用,能够覆盖基本的功能测试需求。     

黑盒测试用例设计方法研究

为了快速地设计出完整有效的测试用例以保障软件测试质量,在分析黑盒测试用例设计技术的基础上,采用了将边界值和等价类测试技术结合起来设计测试用例的一种新的方法思路。在此以一个三角形问题为实例通过分析,先用边界值分析确定数据边界,再用等价类划分方法得到等价的数据类,从而快速获得了一个完整有效的测试用例。采用这种方法设计的测试用例具有较强的发现软件程序错误的的特点,不但能有效避免测试的盲目性,并且能提高测试效率和测试覆盖度。     

Detection of Delay Faults in Memory Address Decoders

In this paper we present an efficient test concept for detection of delay faults in memory address decoders based on the march test tactic. The proposed Transition Sequence Generator (TSG) generates an optimal transition sequence for sensitization of the delay faults in address decoders by Hayes's transformation on a reflected Gray code. It can be used for parallel Built-In Self-Testing (BIST) of high-density RAMs. We also present an efficient Design For Test (DFT) approach for immediate detection of the effects of the delay faults in the address decoders which does not change memory access time. It requires extra logic to be attached to the outputs of the address decoders. This DFT approach can be used to increase memory testability for both on-line and off-line testing of single- and multi-port RAMs.     

并发程序变异测试研究综述

变异测试是一种面向缺陷的软件测试方法,利用人为注入的缺陷引导测试数据生成,评价测试数据的有效性,在软件工程领域得到了广泛关注.依托多核架构,开发可靠的并发程序越来越迫切.近年来,很多学者尝试将变异测试技术应用于并发程序,以提高并发程序测试的效率和可靠性.首先,介绍了本文工作与已有综述的不同;然后,阐述了与并发程序和变异测试技术相关的知识;接着,从变异实施、变异测试准则、测试数据生成等3方面,综述并发程序变异测试的研究进展,包括：变异算子设计、选择变异、高阶变异、弱变异、测试数据生成方法、变异测试工具等;最后,讨论需要进一步研究的问题.     

Fast Anti-Random (FAR) Test Generation to Improve the Quality of Behavioral Model Verification

Anti-random testing has proved useful in a series of empirical evaluations. The basic premise of anti-random testing is to chose new test vectors that are as far away from existing test inputs as possible. The distance measure is either Hamming distance or Cartesian distance. Unfortunately, this method essentially requires enumeration of the input space and computation of each input vector when used on an arbitrary set of existing test data. This prevents scale-up to large test sets and/or long input vectors.We present and empirically evaluate a technique to generate anti-random vectors that is computationally feasible for large input vectors and long sequences of tests. We also show how this fast anti-random test generation (FAR) can consider retained state (i.e. effects of subsequent inputs on each other). We evaluate effectiveness of applying anti-random vectors for behavioral model verification using branch coverage as the testing criterion.     

Compaction of IDDQ Test Sequence Using Reassignment Method

IDDQ testing is an effective method for detecting short faults of CMOS circuits. Since IDDQ testing requires the measurement of current, the testing time of IDDQ testing is longer than that of logical testing. In this paper, we proposed an IDDQ test compaction method for internal short faults of gates in sequential circuits by using the reassignment method of signal values. Experimental results show that test sequences generated by weighted random vectors can be reduced to short sequences with less computation time.     

Oscillation Ring Delay Test for High Performance Microprocessors

This paper proposes a new test scheme, oscillation ring test, and its associated test circuit organization for delay fault testing for high performance microprocessors. For this test scheme, the outputs of the circuit under test are connected to its inputs to form oscillation rings and test vectors which sensitize circuit paths are sought to make the rings oscillate. High speed transition counters or oscillation detectors can then be used to detect whether the circuit is working normally or not. The sensitizable paths of oscillation rings cover all circuit lines, detecting all gate delay faults, a large part of hazard free robust path delay faults and all the stuck-at faults. It has the advantage of testing the circuit at the working speed of the circuit. Also, with some modification, the scheme can also be used to measure the maximum speed of the circuit. The scheme needs minimal simple added hardware, thus ideal for testing, embedded circuits and microprocessors.     

Design for Delay Testability in High-Speed Digital ICs

The cost-effective testing of high-speed digital ICs is becoming increasingly problematic. Even advanced, costly testers are not always capable of testing these ICs because of their high-speed limitations. This paper focuses on a Design for Delay Testability (DfDT) technique such that high-speed ICs can be tested using inexpensive, low-speed test systems. Also extensions for possible full BIST of delay faults are addressed.     

High-efficiency test pattern generating mechanism

A high-efficiency test pattern generating mechanism blending the weighted-random-pattern generator and the controllable-linear-feedback-shift register is proposed in this paper. This mechanism tests a logic circuit in two phases. In the first phase, the weighted-random-pattern generator generates the test patterns to drop some of the faults from the fault list containing the faults that have not been tested in the initial testing performed by the patterns generated from the automatic-test-pattern generator. In the second phase, the controllable-linear-feedback-shift register generates the test patterns to test the deterministic faults that have not been tested in the first phase. We adopt controllable-linear- feedback-shift register to generate the deterministic patterns instead of modifying the configuration of the weighted-random-pattern generator such that a better fault coverage can be achieved with a lower hardware penalty and a shorter test length.