High-breakdown-voltage MESFET with a low-temperature-grown GaAspassivation layer and overlapping gate structure

GaAs MESFETs were fabricated using a low-temperature-grown (LTG) high-resistivity GaAs layer to passivate the doped channel between the gate and source and between the gate and the drain. The gate was fabricated such that the source and drain edges of the metal gate overlapped the LTG GaAs passivation layer. The electric fields at the edges of the gate were reduced by this special combination of LTG GaAs passivation and gate geometry, resulting in a gate-drain breakdown voltage of 42 V. This value is over 60% higher than that of similar MESFETs fabricated without the gate overlap     

MOCVD-grown 0.25-μm MESFET's using tertiary butyl arsine as thearsenic source

High-performance 0.25-μm-gate MESFETs on MOCVD-grown epitaxial structure have been fabricated using tertiary butyl arsine (TBA) as the arsenic source. TBA, a liquid-phase organometallic arsenic compound, is a promising alternate arsenic source due to its lower vapor pressure, which makes it safer to handle than arsine. DC characterizations show that the extrinsic peak transconductance is 508 mS/mm. From on-wafer S-parameter measurements, the MESFETs show a current-gain cutoff frequency of 55 GHz and a maximum-available-gain cutoff frequency of 93 GHz. These results represent the best results reported for MOCVD-grown MESFETs using a TBA source and compare favorably with the previously reported f_t of 40 GHz for molecular beam epitaxy (MBE)-grown MESFETs     

Fabrication and characterization of 4H-SiC planar MESFETs

The planar 4H-SiC MESFETs were fabricated by employing an ion-implantation process instead of a recess gate etching process, which is commonly adapted in compound semiconductor MESFETs, to eliminate potential damage to the gate region during etching process. Excellent ohmic and Schottky contact properties were achieved by using the modified RCA cleaning of 4H-SiC surface and the sacrificial thermal oxide layer. The fabricated MESFETs was also free from drain current instability, which the most of SiC MESFETs have been reported to suffer for the charge trapping. The drain current recovery characteristics were also improved by passivating the surface with a thermal oxide layer and eliminating the charge trapping at the surface. The performance of fabricated MESFETs was characterized by analyzing the small-signal equivalent circuit parameters extracted from the measured parameters.     

S波段脉冲大功率SiC MESFET

采用自主开发的3英寸(75mm)SiC外延技术和SiC MESFET的设计及工艺加工技术,成功地实现了S波段中长脉宽条件下(脉宽300μs,占空比10%),输出功率大于200W,功率增益大于11dB,功率附加效率大于30%的性能样管,脉冲顶降小于0.5dB,实现了大功率输出条件下的较高功率增益和功率附加效率及较小的脉冲顶降,初步显示了SiC功率器件的优势。器件设计采用多胞合成技术,为减小引线电感对功率增益的影响,采用了源引线双边接地技术;为提高器件的工作频率,采用了电子束写栅技术;为提高栅的可靠性,采用了加厚栅金属和国家授权的栅平坦化发明专利技术;同时采用了以金为主体的多层难熔金属化系统,提高了器件的抗电迁徙能力。     

A novel sub-half micron Al-Cu via plug interconnect using lowdielectric constant material as inter-level dielectric

A novel Al-Cu via plug interconnect using low dielectric constant (low-ϵ) material as inter-level dielectric (ILD) has been demonstrated. The interconnect structure was fabricated by spin-on deposition of the low-ϵ ILD and physical vapor deposition (PVD) of the Al-Cu. Excellent local ILD planarization was achieved by a two-step spin-on coating process. The dielectric constant of the low-ϵ no is about 2.7, which leads to significant interconnect wiring capacitance reduction. For the first time, completely filled Al-Cu:0.5% plugs with nearly vertical sidewalls were fabricated in organic low-ϵ ILD. Excellent via fill was observed with via size down to 0.30 μm. Low via resistance and excellent via reliability have been observed     

Printed circuit board as a MEMS platform for focused ion beam technology

By combining low-cost printed circuit board technology and focused ion beam techniques, a simple method has been developed to produce thermal microsensors in a robust package with straightforward electrical connectivity. Two devices have been developed to demonstrate the principle. The first was fabricated using a single step process comprised of FIB deposited platinum. The second device utilised a multistep process using FIB milled thermally evaporated Au on a PCB platform with through-plated vias. The performance of these devices was tested by measuring their thermo-electrical characteristics.     

Application of heterojunction FET to power amplifier for cellulartelephone

The high power properties of heterojunction FETs (H-FET have been investigated. The H-FETs are fabricated by using a strained AlGaAs/GaInAs/GaAs/AlGaAs selectively-doped double heterojunction structure. As compared with GaAs MESFETs, the H-FETs show 1.5 dB higher saturation power and 8% higher power-added efficiency than those of the MESFETs, at 950 MHz and 4.7 V. The H-FETs are more suitable for the power amplifier of cellular telephones     

Realisation of very high transconductance GaAs MESFETs

By using a model which considers velocity overshoot, it is shown that the performance of GaAs MESFETs in enhancement mode depends strongly on the geometrical and electrical characteristics of the access region between source and gate. The sheet resistance of the unrecessed epilayer, and the distance between the source-end of the recessed region and the gate, have to be as small as possible. 300 nm gate length MESFETs with very low values for these parameters were realised with an n-GaAs active layer (6×10¹⁷ cm^-3). These devices exhibit very high microwave transconductances (800 mS/mm) with good cutoff frequencies (up to 55 GHz). This result suggests that very high transconductance MESFETs can be fabricated from not-too-heavily doped active layers provided that the characteristics of the source-gate access region is properly optimised     

Analog image recognition arrays design by using co-fabricated MOSFET and MESFETs on a 0.25?μm SOS process

This paper presents an analog image recognition system with a novel MESFET device fabricated on a fully depleted (FD) CMOS process. An analog image recognition system with a power consumption of 2.4?mW/cell and a settling time of 6.5???s was designed, fabricated and characterized. A CNN is employed to realize a core cell of the proposed image recognition system. While a CNN benefits from its regular structure, it faces challenges due to its power consumption, speed, and size in their CMOS implementations. SOS MESFETs can deal with the challenges associated with CMOS-based CNNs. Advantages of SOS MESFETs associated with nonlinear signal processing include lower power consumption and higher operating speeds compared to similar geometry MOSFETs carrying the same current. SOS MESFET-based analog image recognition systems were fabricated and the transient response is characterized in both simulation using a TOM3 SPICE model extracted from SOS MESFETs and in experiment using image testing lab equipment. Settling times of 3.5 and 6.5???s for one-by-four and one-by-eight arrays, respectively, were achieved with line recognition template. The corresponding power consumption for the two arrays was 9.6 and 19.2?mW, respectively.     

GaAs power MESFETs prepared by metalorganic chemical vapour deposition

GaAs power MESFETs have been developed by using MOCVD wafers. The saturation current of 7.2 mm-wide MESFET chips fabricated on a 6 cm2 wafer has been found to have a standard deviation of 6.8%, which is nearly a half of that observed for MESFETs fabricated on a conventional VPE wafer of the same size. The two-chip device with a gate width of 14.4 mm delivered 4 W at 7.8 GHz with 3 dB gain. The output power of 4 W at 7.8 GHz is the state-of-the-art performance of the GaAs power MESFETs prepared by the MOCVD technique.     

Dual-wavelength laser source monolithically integrated with Y-junction coupler and isolator using quantum-well intermixing

A dual-wavelength laser source monolithically integrated with an isolator and a Y-junction coupler is fabricated by using a new quantum-well intermixing technique. The technique employs a buried Ge layer between the sample surface and the spin-on silica film to control the bandgap tuning in selective areas across a wafer. The integrated isolator can avoid the crosstalk between the two channels of the device. Two distinct lasing wavelengths of 950 and 969 nm are coupled into one single output port through the transparent Y-junction coupler. The two channels have similar threshold current and slope efficiency.     

Very-shallow low-resistivity p+-n junctions for CMOS technology

Shallow p-n junctions 110 nm deep have been fabricated using rapid thermal diffusion from a spin-on oxide source. Surface concentrations greater than 3 × 10²⁰cm^-3are possible, with sheet resistivities less than 100 Ω/sq and a maximum reverse-bias leakage at 5 V of 3 nA.cm^-2. Results from 150-nm junctions are also given and are compared with BF2ion implantation.     

Short-channel effects and drain-induced barrier lowering innanometer-scale GaAs MESFET's

Short-channel effects in GaAs MESFETs are investigated. MESFETs were fabricated with gate lengths in the range of 40 to 300 nm with GaAs and AlGaAs buffer layers. The MESFETs were characterized by DC transconductance, output conductance, and subthreshold measurements. This work focuses on overcoming the short-channel effect of large output conductance by the inclusion of an AlGaAs buffer layer, and identifying the benefit the AlGaAs buffer affords for reducing subthreshold current, including the effect of drain-induced barrier lowering. The design yielded 300-nm gate-length MESFETs with excellent suppression of the major short-channel effects     

New MBE buffer used to eliminate backgating in GaAs MESFETs

The buffer is grown by molecular beam epitaxy (MBE) at low substrate temperatures (150-300°C) using Ga and As₄ beam fluxes. It is highly resistive, optically inactive, and crystalline, and high-quality GaAs active layers can be grown on top of the buffer. MESFETs fabricated in active layers grown on top of this new buffer show improved output resistance and breakdown voltages; the DC and RF characteristics are otherwise comparable to MESFETs fabricated by alternative means and with other buffer layers     

High-Gain SiC MESFETs Using Source-Connected Field Plates

We demonstrate for the first time improvement of radio-frequency (RF) gain of SiC MESFETs by using source-connected field plates (FPs). MESFETs fabricated with this approach show a new record maximum stable gain exceeding 15.7 dB at 3.1 GHz. This is 2.7 dB higher than the baseline devices without FP. RF power output greater than 4W/mm was also achieved showing the potential of these devices for high-power operation.      

High-quality schottky and ohmic contacts in planar 4H-SiC metal semiconductor field-effect transistors and device performance

We have fabricated planar 4H-SiC, metal-semiconductor field-effect transistors (MESFETs) with high-quality metal/SiC contacts. To eliminate potential damage to the gate region caused by etching and simplify the device fabrication process, gate Schottky contacts were formed without any recess gate etching, and an ideality factor of 1.03 was obtained for these gate contacts. The interface state density between the contact metal and SiC was 5.7×10¹² cm⁻²eV⁻¹, which was found from the relationship between the barrier height and the metal work function. These results indicate that the interface was well controlled. Thus, a transconductance of 30 mS/mm was achieved with a 3-μm gate length as the performance figure of these MESFETs with high-quality metal/SiC contacts. Also, a low ohmic contact resistance of 1.2×10⁻⁶ Θcm² was obtained for the source and drain ohmic contacts by using ion implantation.     

Millimeter-wave ion-implanted gradedInxGa1-xAs MESFETs grown by MOCVD

The authors present the fabrication and characterization of ion-implanted graded In_xGa_1-xAs/GaAs MESFETs. The In_xGa_1-xAs layers are grown on GaAs substrates by MOCVD (metal-organic chemical vapor deposition) with InAs concentration graded from 15% at the substrate to 0% at the surface. 0.5-μm gate MESFETs are fabricated on these wafers using silicon ion implantation. In addition to improved Schottky contact, the graded In_xGa _1-xAs MESFET achieves maximum extrinsic transconductance of 460 mS/mm and a current-gain cutoff frequency f_t of 61 GHz, which is the highest ever reported for a 0.5-μm gate MESFET. In comparison, In_0.1Ga_0.9As MESFETs fabricated with the same processing technique show an f_t of 55 GHz     

Airbridged-gate MESFETs fabricated by isotropic reactive ionetching

The authors have designed, fabricated, and characterized 0. 1-μm-gate-length MESFETs in which isotropic BCl₃ reactive ion etching is used to remove material under the gate feed to form an airbridge and isolate the active area. This etching is more controllable than wet etch techniques now used. For comparison, conventional mesa-isolated MESFETs were fabricated on the same wafer. By measuring the RF properties at several bias points, fringing capacitances have been extracted. The parasitic capacitances are smaller in the airbridged-gate configuration     

High-speed GaAs SCFL divider

A single-clocked divide-by-four circuit with a maximum operating frequency of 5.2 GHz has been developed. The circuit was fabricated using 1 ?m-gatelength high-transconductance enhancement-mode GaAs MESFETs with Pt-buried gate structure. The basic building block of the circuit is a source-coupled FET logic (SCFL) master-slave flip-flop with ECL-compatible input and output.     

Improvement of RF performance of GaAs/Si MESFETs using buriedoxygen implantation

A novel buried oxygen implantation (BOI) procedure is described to reduce parasitics and improve RF performance of GaAs/Si MESFETs. Devices fabricated with this procedure show output conductance of less than 8.5 mS/mm which is the lowest reported to date for GaAs/Si MESFETs. These results are particularly important to improve the power performance of GaAs/Si MESFETs