A parallel resonant converter with postregulators

A parallel resonant power converter (PRC) with postregulator(s) power synchronized to the primary switching frequency is investigated for discontinuous-conduction mode operation. It is analyzed with a magnetic amplifier, which blocks the rising edge of the secondary voltage, and with a synchronized buck regulator, which blocks part of the trailing edge of the secondary voltage waveform under the steady-state conditions. As a result, it has been shown that magnetic amplifiers are not suitable for resonant mode power converters, since the step change of the load from low to high during the same switching period as the primary makes the operating conditions worse. However, postregulators that block the trailing edge of the secondary voltage waveform do not adversely affect the operating conditions of PRC and work satisfactorily. As an alternative, a PRC with a magnetic postregulator is presented. An offline 150 W 250 kHz PRC is designed with a magnetic postregulator for a personal computer application, and experimental waveforms are included     

Lumped-element isolator with lower symmetrical configuration of three windings

Ideal isolator conditions are derived using circuit analysis in a lumped-element isolator with three windings at angles of /spl theta/ and /spl phi/. The angle /spl theta/ can be arbitrary; however, /spl phi/ is restricted to lie on the bisector of cross-angle /spl theta/ or the supplementary angle of /spl theta/. We found that the isolator with /spl theta/=/spl phi/=60 [deg] behaves the same as the one with conventional structure with /spl theta/=/spl phi/=120 [deg]. However, the former has a 0/spl deg/ phase shift and the latter a 180/spl deg/ phase shift between the input and output. The theoretical prediction was experimentally confirmed with an 800-MHz-band isolator.     

New high-speed bipolar XOR gate with absolutely symmetrical circuit configuration

A new monolithic integrated exclusive OR gate (XOR) in E/sup 2/CL circuit design is presented. The symmetry with respect to both inputs makes it superior to the standard XOR gates in ECL or E/sup 2/CL for several applications. The circuit was realised using a conservative 2 mu m standard silicon bipolar technology.<>     

New multi-output switching converters with MOSFET-rectifier postregulators

A new multi-output switching power converter is proposed. The new power converter can reduce conduction losses and achieve tight regulation. The small-signal model of the new power converter has also been developed and experimentally verified. Based on the proposed scheme and the analysis of the small-signal model, high-performance and high-efficiency multi-output switching power converters can be achieved     

基于金属包覆波导结构的电光调制器的研究

文章提出了一种基于自由空间耦合技术的电光调制器.入射光直接入射到作为耦合层的上层金属膜表面,通过改变外加电场的场强,控制入射光耦合进导波层的能量,从而改变反射光的强度,实现电光调制.该类调制器具有插入损耗小、响应速度快、稳定性高和成本低廉等诸多优点.与传统的棱镜耦合方式的聚合物电光调制器相比,自由空间耦合技术的引入使此类电光调制器结构更加紧凑、更易于阵列化集成.     

A new configuration of single-phase symmetrical PWM AC choppervoltage controller

With the increased availability of power MOSFETs and insulated gate bipolar transistors, a new generation of simple choppers for AC inductive loads is foreseen. These new power semiconductors ease the use of forced commutations of thyristor switches to improve the supply power factor, even with highly inductive loads. The AC controllers with thyristor technology can be replaced by pulsewidth modulation (PWM) AC chopper controllers which have important advantages. In this paper, a symmetrical PWM AC chopper designed to operate with single-phase inductive loads with a reduced number of controlled switches is described. The operation as a variable voltage source of this converter is evaluated. This includes the conversion characteristics, harmonic generation, harmonic distortion factor, and input power factor. By digital simulation, these characteristics are investigated theoretically, and to correlate the measurements with theory, an experimental setup is presented to confirm the analytical analysis     

Techniques for reduction of required headroom in high-frequencymagamp postregulators

High headroom in a magamp postregulator increases circuit losses, including power transistor losses, saturable reactor core loss, and freewheeling diode snubber loss. Higher headroom also requires the use of higher voltage diodes. The authors describe common causes for large headroom requirement and discuss various techniques to reduce it     

Novel topologies for DC-DC converter with PWM control

Two topologies for the buck converter are presented. The first converter consists of two active switches whereas the second converter, derived from the parent twoswitch converter, consists of only one active switch. The main feature of this new converter is the ability to operate at a constant switching frequency using a simple PWM control. The design of the gate circuit is simplified as there is only one switch. The converter has a good efficiency, as is proved by the experimental results. The operation of the parent two-switch converter, from which the new single-switch converter is derived, is also presented to gain insight into the design of the new converter.     

Measuring ISP topologies with Rocketfuel

To date, realistic ISP topologies have not been accessible to the research community, leaving work that depends on topology on an uncertain footing. In this paper, we present new Internet mapping techniques that have enabled us to measure router-level ISP topologies. Our techniques reduce the number of required traces compared to a brute-force, all-to-all approach by three orders of magnitude without a significant loss in accuracy. They include the use of BGP routing tables to focus the measurements, the elimination of redundant measurements by exploiting properties of IP routing, better alias resolution, and the use of DNS to divide each map into POPs and backbone. We collect maps from ten diverse ISPs using our techniques, and find that our maps are substantially more complete than those of earlier Internet mapping efforts. We also report on properties of these maps, including the size of POPs, distribution of router outdegree, and the interdomain peering structure. As part of this work, we release our maps to the community.     

Current buffer compensation topologies for LDOs with improved transient performance

The goal of internal frequency compensation of a low dropout voltage regulator (LDO) is the selection of a small-value, ESR-independent output capacitor. Cascode compensation formed by a common-gate transistor acting as a current buffer, an optional series resistor, and a compensation capacitor creates a dominant pole and a left-half-plane (LHP) zero, allowing adequate phase margin and stable LDO design. To this end, a 1.21?V output, 100?mA, 0.1?C10???F output capacitor, ESR-independent, low voltage LDO using cascode compensation with replica bias is designed and fabricated in a 0.5???m CMOS process with an area of 0.22?mm². A line regulation of 0.05% V/V, load regulation of 0.001% V/mA and dropout voltage of 220?mV were measured. LDO-specific pole-zero analysis is detailed. In addition to this design, two improved transient response LDO architectures using cascode compensation with split-length transistors are also explored. A Power Good feature is discussed, which enables direct interface between the LDO and a micro-processor.     

Virtual topologies for multicasting with multiple originators in WDM networks

In this paper, we consider the problem of multicasting with multiple originators in WDM optical networks. In this problem, we are given a set S of source nodes and a set D of destination nodes in a network. All source nodes are capable of providing data to any destination node. Our objective is to find a virtual topology in the WDM network which satisfies given constraints on available resources and is optimal with respect to minimizing the maximum hop distance. Although the corresponding decision problem is NP-complete in general, we give polynomial time algorithms for the cases of unidirectional paths and rings.     

Circuit topologies for single-phase voltage-doubler boostrectifiers

A new family of single-phase voltage-doubler PWM (pulse width modulated) boost rectifiers is presented. By examining the switching states of several standard single-phase boost rectifier circuits, three characteristic PWM voltage switching patterns are identified: unipolar PWM; bipolar PWM; and phase-adjusted unipolar PWM. From this analysis, an equivalent family of voltage-doubler rectifiers is derived. When high output voltages are required, voltage-doubler rectifiers are shown to be able to generate AC line currents with the lowest current distortion. The circuits presented are examined using circuit simulators and experimental results     

Mesh routing topologies for multi-FPGA systems

There is currently great interest in using fixed arrays of FPGAs for logic emulators, custom computing devices, and software accelerators. An important part of designing such a system is determining the proper routing topology to use to interconnect the FPGAs. This topology can have a great effect on the area and delay of the resulting system. Crossbar, Hierarchical Crossbar, and Mesh interconnection schemes have all been proposed for use in FPGA-based systems. In this paper, we examine Mesh interconnection schemes, and propose several constructs for more efficient topologies. These reduce interchip delays by more than 60% over the basic four-way Mesh     

Investigation of candidate VRM topologies for futuremicroprocessors

By reducing the power supply voltage, faster, lower power consumption, and high integration density data processing systems can be achieved. The current generation high-speed complementary metal-oxide-semiconductor (CMOS) processors (e.g., Alpha, Pentium, Power PC) are operating at above 300 MHz with 2.5 to 3.3 V output range. Future processors will be designed in the 1.1-1.8 V range, to further enhance their speed-power performance. These new generation microprocessors will present very dynamic loads with high current slew rates during transient. As a result, they will require a special power supply, voltage regulator module (VRM), to provide well-regulated voltage. The VRMs should have high power densities, high efficiencies, and good transient performance. In this paper, the critical technical issues to achieve this target for future generation microprocessors are addressed. A VRM candidate topology, interleaved quasisquare-wave (QSW), is proposed. The design, simulation and experimental results are presented     

Design techniques for voltage-to-time converters with nonlinearity emphasis

This paper provides an in-depth treatment of voltage-to-time converters (VTCs) for time-based signal processing with a nonlinearity emphasis. The need for VTCs in deployment of time-based techniques for high-speed or high-resolution analog-to-digital converters is investigated. It is followed with the classification of VTCs. A detailed treatment of the principle, topology, operation, and design consideration of variable-slope (VS) and constant-slope (CS) VTCs is provided. The nonlinearity of VS-VTCs and that of CS-VTCs are analyzed in detail analytically. It is shown that VS-VTCs is inherently nonlinear while CS-VTCs is intrinsically linear. Factors contributing to the nonlinearity of these VTCs are investigated. VS-VTCs and CS-VTCs studied are designed in TSMC 130 nm 1.2 V CMOS and analyzed using Spectre from Cadence Design Systems with BSIM3.3 device models. A good agreement between simulation and analytical results is obtained. The average gain of the VS-VTC is 4.4 times that of the CS-VTC. The 2nd and 3rd harmonics of the CS-VTC are significantly smaller as compared with those of the VS-VTC at the price of more power consumption.

     

High-performance GaAs switch IC's fabricated using MESFET's withtwo kinds of pinch-off voltages and a symmetrical pattern configuration

GaAs MESFET switch IC's operating at low control voltages of 0/-3 V and +3/0 V have been developed for use in Personal Handy Phones using the 1.9 GHz band. The switch IC's have excellent RF characteristics, and have no need for external circuit installation. The unique points of these IC's are the use of GaAs MESFET's with two kinds of pinch-off voltages and a symmetrical source and drain pattern configuration with respect to the gate. The 0/-3 V IC had low insertion loss of 0.55 dB and 0.65 dB, and high isolation of 31 dB and 24 dB at receiving and transmitting operations, respectively. The +3/0 V IC also had excellent characteristics such as insertion loss of 0.73 dB and 0.95 dB, and isolation of 27 dB and 23 dB, respectively. Both IC's had an output power at 1 dB gain compression point of 25.4 dBm and 3rd order intercept point of more than 46 dBm     

A novel self-routing address scheme for all-optical packet-switched networks with arbitrary topologies

Pure all-optical packet-switched networks in which both header processing and packet routing are carried out in the optical domain overcome the bandwidth bottlenecks of optoelectronic conversions and therefore are expected to meet the needs of next generation high speed networks. Due to the limited capabilities of available optical logic devices, realizations of pure all-optical packet-switched networks in the near future will likely employ routing schemes that minimize the complexity of routing control. In this paper, we propose a novel self-routing scheme that identifies the output ports of the nodes in a network instead of the nodes themselves. The proposed address scheme requires single bit processing only and is applicable to small to medium size pure all-optical packet-switched networks with arbitrary topologies. Unlike traditional self-routing schemes, multiple paths between two nodes can be defined. An hierarchical address structure can be used in the proposed routing scheme to shorten the address.     

Multistage amplifier topologies with nested Gm-Ccompensation

This paper presents a multistage amplifier for low-voltage applications (<2 V). The amplifier consists of simple (noncascode) low gain stages and is stabilized using a nested transconductance-capacitance compensation (NGCC) scheme. The resulting topology is similar to the well known nested Miller compensation (NMC) multistage amplifier, except that the proposed topology contains extra G _m feedforward stages which are used to enhance the amplifier performance. The NGCC simplifies the transfer function of the proposed multistage amplifier which, in turn, simplifies its stability conditions. A comparison between the NGCC and NMC shows that the NGCC has wider bandwidth and is easier to stabilize. A four-stage NGCC amplifier has been fabricated using a 2-μm CMOS process and is tested using a ±1.0 V power supply. A dc gain of 100 dB has been measured. A gain bandwidth product of 1 MHz with 58° of phase margin and power of 1.4 mW can be achieved. The op amp occupies an active area of 0.22 mm². Step response shows that the op amp is stable     

Guaranteed scheduling for switches with configuration overhead

We present three algorithms that provide performance guarantees for scheduling switches, such as optical switches, with configuration overhead. Each algorithm emulates an unconstrained (zero overhead) switch by accumulating a batch of configuration requests and generating a corresponding schedule for a constrained switch. Speedup is required both to cover the configuration overhead of the switch and to compensate for empty slots left by the scheduling algorithm. Scheduling algorithms are characterized by the number of configurations N/sub s/ they require to cover a batch of requests and the speedup required to compensate for empty slots S/sub min/. Initially, all switch reconfiguration is assumed to occur simultaneously. We show that a well-known exact matching algorithm, EXACT, leaves no empty slots (i.e., S/sub min/=1), but requires N/sub s//spl ap/N/sup 2/ configurations for an N-port switch leading to high configuration overhead or large batches and, hence, high delay. We present two new algorithms that reduce the number of configurations required substantially. MIN covers a batch of requests in the minimum possible number of configurations, N/sub s/=N, but at the expense of many empty slots, S/sub min//spl ap/4log/sub 2/N. DOUBLE strikes a balance, requiring twice as many configurations, N/sub s/=2N, while reducing the number of empty slots so that S/sub min/=2. Loosening the restriction on reconfiguration times, the scheduling problem is cast as an open shop. The best known practical scheduling algorithm for open shops, list scheduling (LIST), gives the same emulation requirements as DOUBLE. Therefore, we conclude that our architecture gains no advantages from allowing arbitrary switch reconfiguration. Finally, we show that DOUBLE and LIST offer the lowest required speedup to emulate an unconstrained switch across a wide range of port count and delay.