A model of the stress induced leakage current in gate oxides

A new quantitative model of the stress induced leakage current (SILC) in MOS capacitors with thin oxide layers has been developed by assuming the inelastic trap-assisted tunneling as the conduction mechanism. The oxide band structure has been simplified by replacing the trapezoidal barrier with two rectangular barriers. An excellent agreement between simulations and experiments has been found by adopting a trap distribution Gaussian in space and in energy. Only minor variations of the trap distribution parameters were observed by increasing the injected charge during electrical stress, indicating that oxide neutral defects with similar characteristics are generated at any stage of the stress     

Investigation of stress induced leakage current in CMOS structures with ultra-thin gate dielectrics

Investigation on the stress induced leakage current shows that the SILC degradation rate follows a pure power law with the injection dose which is almost independent of gate bias polarity and stress current intensity. Moreover, it has also been found that the SILC is invariant with the device area, substrate type but could depend on the gate material in the case of P+ polysilicon due to boron-induced defects in the bulk of the oxide.     

Study of stress induced leakage current by using high resolution measurements

A thorough characterization of stress-induced leakage currents (SILCs) for a IOnm-thick oxide, by using the floating-gate technique, is presented. The obtained current is modeled by a volume-limited conduction mechanism. Experimental and model suggest that SILC conduction mechanism is the same in thin as well as in thick oxides.     

Low-level gate current injections in flash memories initiated byminority carrier collection action of floating terminals

An unintentional channel hot carrier injection phenomenon is reported for flash memory cells. The injection occurs near the source metallurgical junction during electrical erase and is caused by subthreshold leakage current between source and floating drains. This mechanism is initiated by a minority carrier population (electrons) which is generated by impact ionization around the source junction and later collected by the floating drains. Subsequently, when the floating gate potential approaches threshold voltage, these collected electrons drift from the drain toward the source. When they reach the source junction depletion region, they experience carrier multiplications and some hot carriers are injected onto the floating gate. The injected carriers can be either hot holes or hot electrons depending on the magnitude of the floating gate potential. This mechanism affects the final threshold voltage distribution of flash memories, especially when the electric field across the tunnel oxide is low     

Temperature dependence of gate induced drain leakage current insilicon CMOS devices

The temperature dependence of the gate induced drain leakage (GIDL) current in CMOS devices is investigated from 20K up to 300K. It is shown that, at sufficiently high electric field, the conventional band-to-band tunnelling GIDL current law is applicable down to near-liquid helium temperatures for both nand p-channel devices. The exponential factor B of the GIDL current law is found to be nearly independent of temperature. Moreover, the decrease of the GIDL current as the temperature is lowered, is shown to originate from the temperature variation of the pre-exponential coefficient A of the GIDL current law     

Stress induced gate–drain leakage current in ultra-thin gate oxide

Ultra-thin gate oxide reliability, in large area MOSFETs, can be monitored by measuring the gate current when the substrate is depleted. When the channel length is scaled down, the tunneling current associated with the source/drain extension region (SDE) to the gate–overlap regions can dominate the gate current. In N-MOSFETs, as a function of the negative gate voltage two components of the gate–drain leakage current should be considered, the first for V_FB < V_G < 0 V and the second for V_G < V_FB. These components are studied in this work before and after voltage stresses. The aim of this work is to see whether this gate–drain current can be used to monitor the oxide degradation above or near the source and/or drain extension region in N-MOSFETs. It is important because the most serious circuit-killing breakdown occurs above or near the drain (or source) extension region. Finally, we show that it is necessary, before explaining the gate LVSILC curves obtained after stresses on short-channel devices, to verify which is the dominate current at low voltage.     

Self-heating and gate leakage current in a guarded MOSFET

Gate leakage current measurements of a guarded MOSFET show that device self-heating has a marked effect on the Schottky emission current. This effect can make the bias conditions for zero gate leakage current very sensitive to changes in drain voltage.     

Role of positive trapped charge in stress-induced leakage current for flash EEPROM devices

The transient behavior of hot hole (HH) stress-induced leakage current (SILC) in tunnel oxides is investigated. The dominant SILC mechanism is positive oxide charge-assisted tunneling (PCAT). The transient effect of SILC is attributed to positive oxide charge detrapping and thus the reduction of PCAT current. A correlation between SILC and stress-induced substrate current is observed. Our study shows that both SILC and stress-induced substrate current have power law time-dependence t/sup -n/ with the power factor n about 0.7 and 1, respectively. Numerical analysis for PCAT current incorporating a trapped charge caused Coulombic potential in the tunneling barrier is performed to evaluate the time- and field-dependence of SILC and the substrate current. Based on our model, the evolution of threshold voltage shift with read-disturb time in a flash EEPROM cell is derived. Finally, the dependence of SILC on oxide thickness is explored. As oxide thickness reduces from 100 /spl Aring/ to 53 /spl Aring/, the dominant SILC mechanism is found to change from PCAT to neutral trap-assisted tunneling (TAT).     

Enhanced gate induced drain leakage current in HfO2 MOSFETs

The substrate current of high-κ dielectric MOSFETs has been studied using dc sweep and transient (down to 100 μs per I-V curve) electrical measurements. These measurements reveal trap-assisted substrate current components in addition to the traditional bell-shaped impact ionization current. By separating the transversal and lateral electric field contributions, the gate induced drain leakage (GIDL) is shown to dominate the substrate current at low gate biases. At high gate biases, tunneling of valence band electrons from the bulk to the gate dominates. The results show that the GIDL current is the result of band-to-band tunneling assisted by traps located at the HfO₂/SiO₂ interface and transition layer, and not the result of oxide charging.     

A Modelisation of the temperature dependence of the Fowler–Nordheim current in EEPROM memories

In this paper, we suggest a new computation method to simulate the temperature behavior of Fowler–Nordheim tunneling current through the oxide of an EEPROM cell based on surface potential evaluation with temperature dependence. The main idea of this paper is to simulate the tunneling current temperature dependence with only Si–SiO₂ barrier height and surface potential dependences with temperature. Parameters are experimentally extracted from large SOS capacitor measurements. So, final results of the programming window have shown comparing to simulations and measurements.     

Enhanced CAD model for gate leakage current in heterostructurefield effect transistors

A simple and accurate circuit model for Heterostructure Field Effect Transistors (HFETs) is proposed to simulate both the gate and the drain current characteristics accounting for hot-electron effects on gate current and the effect of the gate current on the channel current. An analytical equation that describes the effective electron temperature is developed in a simple form. This equation is suitable for implementation in circuit simulators. The model describes both the drain and gate currents at high gate bias voltages. It has been implemented in our circuit simulator AIM-Spice, and good agreement between simulated and measured results is achieved for enhancement-mode HFETs fabricated in different laboratories. The proposed equivalent circuit and model equations are applicable to other compound semiconductor FETs, i.e., GaAs MESFETs     

Use of pt gate metallization to reduce gate leakage current in GaAs MESFETs

The use of wet-chemical removal of native oxide in a sealed nitrogen ambient prior to deposition of metal on GaAs is shown to be an effective method of engineering the Schottky barrier height of the metal contacts. Due to its higher metal work function, a barrier height of 0.98 eV for Pt on n-type GaAs is demonstrated. This is considerably higher than the barrier height of conventionally processed TiPtAu contacts (0.78 eV). MES-FETs fabricated using PtAu bilayer contacts show reverse currents an order of magnitude lower than TiPtAu contacted companion devices, higher reverse breakdown voltages and much lower gate leakage. Utilizing this technology of oxide removal and the PtAu bilayer contact provides a much simpler method of enhancing the barrier height on re-type GaAs than other techniques such as counter-doping the near-surface or inserting an interfacial layer.     

Impact of nonuniform graded dopant profile in polysilicon gate on gate leakage current

In a MOSFET, a nonuniform, graded vertical dopant profile in the polysilicon gate causes a potential drop at the polysilicon/oxide interface. In this paper, the effect of this potential drop on the gate leakage current has been evaluated for the first time. The extent of variations of this affected gate leakage current with gate oxide thickness, gate length, and gate and drain bias conditions have been assessed with device simulation for an nMOS at 0.13 /spl mu/m low-voltage process. The results provide a guideline to the severity of this effect from the point of view of device and circuit operation and standby power consumption.     

A combined gate replacement and input vector control approach for leakage current reduction

Input vector control (IVC) is a popular technique for leakage power reduction. It utilizes the transistor stack effect in CMOS gates by applying a minimum leakage vector (MLV) to the primary inputs of combinational circuits during the standby mode. However, the IVC technique becomes less effective for circuits of large logic depth because the input vector at primary inputs has little impact on leakage of internal gates at high logic levels. In this paper, we propose a technique to overcome this limitation by replacing those internal gates in their worst leakage states by other library gates while maintaining the circuit's correct functionality during the active mode. This modification of the circuit does not require changes of the design flow, but it opens the door for further leakage reduction when the MLV is not effective. We then present a divide-and-conquer approach that integrates gate replacement, an optimal MLV searching algorithm for tree circuits, and a genetic algorithm to connect the tree circuits. Our experimental results on all the MCNC91 benchmark circuits reveal that 1) the gate replacement technique alone can achieve 10% leakage current reduction over the best known IVC methods with no delay penalty and little area increase; 2) the divide-and-conquer approach outperforms the best pure IVC method by 24% and the existing control point insertion method by 12%; and 3) compared with the leakage achieved by optimal MLV in small circuits, the gate replacement heuristic and the divide-and-conquer approach can reduce on average 13% and 17% leakage, respectively.     

On stress induced leakage current in 5 and 3 nm thick oxides

The stress induced leakage current (SILC) in Si/SiO₂ structures with thin gate oxides has a steady-state component which increases drastically when the oxide thickness decreases. It is generally agreed that the SILC is due to electron tunnelling trough stress-induced traps. However, it was observed that the SILC, created by Fowler–Nordheim injection, decays continuously when, after stress, the samples are positively or negatively biased at a low voltage. The decay is irreversible as long as the gate oxide is not biased at a high voltage. The present article adds complementary observations. It shows, first that the above phenomenon is observed in 3.5 nm thick oxides, secondly, that this phenomenon is stable as long as the temperature stays below 200°C, and thirdly, that during the SILC decay, the interface state density does not diminish.     

Hot hole stress induced leakage current (SILC) transient in tunneloxides

The mechanisms and transient characteristics of hot hole stress induced leakage current (SILC) in tunnel oxides are investigated. Positive oxide charge assisted tunneling is found to be a dominant SILC mechanism in a hot hole stressed device. The SILC transient is attributed to oxide hole detrapping and thus annihilation of positive charge assisted tunneling centers. Our characterization shows that the leakage current transient in a 100-Å oxide obeys a power law time dependence f^-n with the power factor n significantly less than one. An analytical model accounting for the observed time dependence is proposed     

Quantum-mechanical effects and gate leakage current of nanoscale n-type FinFETs: A 2d simulation study

This paper simulates a kind of new sub-50 nm n-type double gate MOS nanotransistors by solving coupled Poisson-Schrödinger equations in a self-consistent manner with a finite element method, and presents a systematic simulation-based study on quantum-mechanical effects, gate leakage current of FinFETs. The simulation results indicate that the deviation from the classical model becomes more important as the gate oxide, gate length and Fin channel width becomes thinner and the Fin channel doping increases. Gate tunneling current density reduces with the body thickness decreasing. Excessive scaling increases the gate current below Fin thickness of 5 nm. The gate current can be dramatically reduced beyond 10¹⁷ cm⁻³ with the Fin body doping increasing. In order to understand the influence of electron confinement, quantum mechanical simulation results are also compared with the results from the classical approach. Our simulation results indicate that quantum mechanical simulation is essential for the realistic optimization of the FinFET structure.     

Minimization of MOSFET gate leakage current in buffer amplifier circuits

It is shown that the components of gate leakage current of a MOSFET used in a previously described unity gain buffer amplifier may be reduced to a minimum under static and dynamic conditions. Modified packaging and novel biasing techniques can minimize both extrinsic and intrinsic components of gate leakage current at the input to the amplifier.     

Characteristics of a new EPROM cell structure with a sidewall floating gate

A new EPROM cell with a sidewall floating gate is proposed and evaluated. The cell structure is similar to that of the usual n-channel MOSFET and has good compatibility, in regard to its fabrication process, with future VLSI devices. The new cell does not require such large coupling capacitance between control gate and floating gate, which results in higher density integration with reduced programming voltages as low as 8 V or less. In actual use of the new cell, the roles of source and drain are reversed in the program mode and in the readout mode. It is shown that the apparent programming characteristics depend on the bias conditions in the readout mode. Very good tolerance to unintentional programming is obtained in the read-out mode, and also in the program mode at half selection.     

Impact of gate direct tunneling current on circuit performance: asimulation study

The influence of gate direct tunneling current on ultrathin gate oxide MOS (1.1 nm⩽t_ox⩽1.5 nm, L_g=50-70 nm) circuits has been studied based on detailed simulations. For the gate oxide thickness down to 1.1 nm, gate direct tunneling currents, including the edge direct tunneling (EDT), show only a minor impact on low V_dd static-logic circuits. However, dynamic logic and analog circuits are more significantly influenced by the off-state leakage current for oxide thickness below 1.5 nm, under low-voltage operation. Based on the study, the oxide thicknesses which ensure the International Technological Roadmap for Semiconductors (ITRS) gate leakage limit are outlined both for high-performance and low-power devices