A unified turbo/Viterbi channel decoder for 3GPP mobile wireless in 0.18-/spl mu/m CMOS

A channel decoder chip compliant with the 3GPP mobile wireless standard is described. It supports both data and voice calls simultaneously in a unified turbo/Viterbi decoder architecture. For voice services, the decoder can process over 128 voice channels encoded with rate 1/2 or 1/3, constraint length 9 convolutional codes. For data services, the turbo decoder is capable of processing any mix of rate 1/3, constraint length 4 turbo encoded data streams with an aggregate data rate of up to 2.5 Mb/s with 10 iterations per block (or 4.1 Mb/s with six iterations). The turbo decoder uses the logMAP algorithm with a programmable logsum correction table. It features an interleaver address processor that computes the 3GPP interleaver addresses for all block sizes enabling it to quickly switch context to support different data services for several users. The decoder also contains the 3GPP first channel de-interleaving function and a post-decoder bit error rate estimation unit. The chip is fabricated in a 0.18-/spl mu/m six-layer metal CMOS technology, has an active area of 9 mm/sup 2/, and has a peak clock frequency of 110.8 MHz at 1.8 V (nominal). The power consumption is 306 mW when turbo decoding a 2-Mb/s data stream with ten iterations per block and eight voice calls simultaneously.     

High-speed VLSI architecture for parallel Reed-Solomon decoder

This paper presents high-speed parallel Reed-Solomon (RS) (255,239) decoder architecture using modified Euclidean algorithm for the high-speed multigigabit-per-second fiber optic systems. Pipelining and parallelizing allow inputs to be received at very high fiber-optic rates and outputs to be delivered at correspondingly high rates with minimum delay. A parallel processing architecture results in speed-ups of as much as or more than 10 Gb, since the maximum achievable clock frequency is generally bounded by the critical path of the modified Euclidean algorithm block. The parallel RS decoders have been designed and implemented with the 0.13-/spl mu/m CMOS standard cell technology in a supply voltage of 1.1 V. It is suggested that a parallel RS decoder, which can keep up with optical transmission rates, i.e., 10 Gb/s and beyond, could be implemented. The proposed channel = 4 parallel RS decoder operates at a clock frequency of 770 MHz and has a data processing rate of 26.6 Gb/s.     

A high-speed low-complexity Reed-Solomon decoder for optical communications

This paper presents a high-speed low-complexity Reed-Solomon (RS) decoder architecture using a novel pipelined recursive modified Euclidean (PrME) algorithm block for very high-speed optical communications. The RS decoder features a low-complexity key equation solver using a PrME algorithm block. The recursive structure enables the novel low-complexity PrME algorithm block to be implemented. Pipelining and parallelizing allow the inputs to be received at very high fiber-optic rates, and outputs to be delivered at correspondingly high rates with minimum delay. This paper presents the key ideas applied to the design of an 80-Gb/s RS decoder architecture, especially that for achieving high throughput and reducing complexity. The 80-Gb/s 16-channel RS decoder has been designed and implemented using 0.13-/spl mu/m CMOS technology in a supply voltage of 1.2 V. The proposed RS decoder has a core gate count of 393 K and operates at a clock rate of 625 MHz.     

A Real-Time Video Decoder for Digital HDTV

In this paper, an architecture for real-time digital HDTV video decoding is presented. Our architecture is based on a dual decoding datapath controlled in a fixed schedule with an efficient write-back scheme for anchor pictures. The decoding datapath is synchronized at the block (8 × 8 pixels) level. Unlike other decoding approaches such as the slice bar decoding method and the cross-divide method, our scheme reduces memory access contention problem to achieve real-time HDTV decoding without a high cost in overall decoder buffers, architecture, and bus. In comparison to data-flow approaches, our method eliminates the complexity associated with tagged data operations. Our anchor picture storage is organized to minimize page-breaks during memory accesses. Simulation shows that with a relatively low rate 81 MHz clock, our decoder can decode MPEG-2 MP@HL HDTV in real-time, based on an ATSC video format of 1,920 × 1,080 pixels/frame at 30 frames/s, at a bit rate of 18 to 20 Mbps.     

A coded 8-PSK system for 140 Mb/s information rate transmission over 80 MHz non-linear transponders

A combined 8-PSK modulation and rate 7/9 convolutional coding technique is proposed for 140 Mb/s information rate transmission over the 80 MHz INTELSAT transponders, thus achieving a bandwidth efficiency of 1.75 b/s/Hz of allocated bandwidth. The desired power efficiency is to achieve a bit error rate of 10^?6 at an E_b/N₀ of 11 dB, including modem and codec implementation losses. The proposed system employs an 8-PSK modem operating at a 60 MHz symbol rate (or 180 Mb/s bit rate), as well as a rate 7/9 convolutional encoder and a 16-state Viterbi algorithm decoder operating at 60 MHz. The rate 7/9 code is periodically time varying and is designed to maximize the Euclidean distance between the modulated codeword sequences, thereby achieving a 3 dB asymptotic coding gain relative to the conventional QPSK system over an AWGN channel. This code is also designed to reduce decoder complexity for high-speed operations. The performance of the proposed system over INTELSAT V and VI non-linear transponders was evaluated by Monte Carlo computer simulation. The 180 Mb/s 8 PSK modem, including the automatic frequency control, automatic gain control, carrier recovery and clock recovery circuits, has been implemented and tested. The complete Viterbi decoder is being implemented on five boards, and the critical add-compare-select (ACS) circuit of the high-speed Viterbi algorithm decoder is being implemented with hybrid technology employing 100-K series emitter-coupled logic dies on specially designed ceramic substrates. The ACS circuit operates at a speed exceeding 120 MHz, well over the design goal of 60 MHz. Construction of this codec is almost complete.     

基于SoC平台设计的H.264/AVC CAVLC解码器

提出了一种基于SoC平台的CAVLC解码器.在尽量减少时钟消耗的前提下,此解码器可以解码每个变换块中变换系数的熵编码码流,并将结果按照块扫描顺序并行输出.通过在XILJNX的ISE6.0 FPGA开发软件下仿真及分析表明,在120MHz时钟时可以满足10 Mb/s码率下H.264标准中Level3.0的性能要求.     

Fast-Converging and Low-Power LDPC Decoding: Algorithm,Architecture, and VLSI Implementation

Low-latency and energy-efficient multi-Gbps LDPC decoding requires fast-converging iterative schedules. Hardware decoder architectures based on such schedules can achieve high throughput at low clock speeds, resulting in reduced power consumption and relaxed timing closure requirements for physical VLSI design. In this work, a fast column message-passing (FCMP) schedule for decoding LDPC codes is presented and investigated. FCMP converges in half the number of iterations compared to existing serial decoding schedules, has a significantly lower computational complexity than residual-belief-propagation (RBP)-based schedules, and consumes less power compared to state-of-the-art schedules. An FCMP decoder architecture supporting IEEE 802.11ad (WiGig) LDPC codes is presented. The decoder is fully pipelined to decode two frames with no idle cycles. The architecture is synthesized using the TSMC 40 nm and 65 nm CMOS technology nodes, and operates at a clock-frequency of 200 MHz. The decoder achieves a throughput of 8.4 Gbps, and it consumes 72 mW of power when synthesized using the 40 nm technology node. This results in an energy efficiency of 8.6 pJ/bit, which is the best-reported energy-efficiency in the literature for a WiGig LDPC decoder.

     

A 2-Mb/s 256-state 10-mW rate-1/3 Viterbi decoder

This paper presents a low-power bit-serial Viterbi decoder chip with the code rate r=1/3 and the constraint length K=9 (256 states) for next generation wireless communication applications. The architecture of the add-compare-select (ACS) module is based on the bit-serial arithmetic and implemented with the pass transistor logic circuit. A cluster-based ACS placement and state metric routing topology is described for the 256 bit-serial ACS units, which achieves very high area efficiency. In the trace-back operation, a power efficient trace-back scheme, allowing higher memory read access rate than memory write in a time-multiplexing method, is implemented to reduce the number of iterations required to generate a decoded output. In addition, a low-power application-specific memory suitable for the function of survivor path memory has also been developed. The chip's core, implemented using 0.5-μm CMOS technology, contains approximately 200 K transistors and occupies 2.46 mm by 4.17 mm area. This chip can achieve the decode rate of 20 Mb/s under 3.3 V and 2 Mb/s under 1.8 V. The measured power dissipation at 2 Mb/s under 1.8 V is only about 9.8 mW. The Viterbi decoder presented here can be applied to next generation wide-band code division multiple access (W-CDMA) systems     

Analysis and performance of bidirectional decoding of convolutionalcodes over fading channels

The performance of suboptimal convolutional decoding over fading channels is explored. The suboptimal decoding algorithm used is the bidirectional algorithm. By estimating a “decoder weight spectrum” for the decoder, an “equivalent free distance” may be observed. Furthermore, by using this “decoder weight spectrum”, useful estimations of the error probabilities are obtained and compared to computer-simulation results in the case of very slow and very fast fading. The resultant curves are shown to be very tightly related. Computer-simulation results are also shown for various signal-to-noise ratios, normalized Doppler spreads, and frame length on three typical fading channels: the Rayleigh fading channel with exponential and Bessel autocorrelation functions and the Rician fading channel with exponential autocorrelation function. We show that considerable gains (up to 4 dB) can be obtained with respect to a similar-complexity Viterbi decoder at a frame error probability P_e =10^-3 and a slightly smaller gain (up to 1.8 dB) at a bit error probability P_b=10^-5     

AsAP: An Asynchronous Array of Simple Processors

An array of simple programmable processors is implemented in 0.18 mum CMOS and contains 36 asynchronously clocked independent processors. Each processor occupies 0.66 and is fully functional at a clock rate of 520-540 MHz at 1.8 V and over 600 MHz at 2.0 V. Processors dissipate an average of 32 mW under typical conditions at 1.8 V and 475 MHz, and 2.4 mW at 0.9 V and 116 MHz while executing applications such as a JPEG encoder core and a fully compliant IEEE 802.11 a/g wireless LAN baseband transmitter.     

Design of High‐Speed CAVLC Decoder Architecture for H.264/AVC

In this paper, we propose hardware architecture for a high‐speed context‐adaptive variable length coding (CAVLC) decoder in H.264. In the CAVLC decoder, the codeword length of the current decoding block is used to determine the next input bitstreams (valid bits). Since the computation of valid bits increases the total processing time of CAVLC, we propose two techniques to reduce processing time: one is to reduce the number of decoding steps by introducing a lookup table, and the other is to reduce cycles for calculating the valid bits. The proposed CAVLC decoder can decode 1920×1088 30 fps video in real time at a 30.8 MHz clock.     

A 1 GHz CMOS analog front-end for a generalized PRML read channel

A 1 GHz CMOS analog front-end for general partial response maximum likelihood (GPRML) read channel in hard disk drive application has been implemented in 0.35 /spl mu/m CMOS. A continuous time analog filter fulfills the relaxed equalization for GPRML detection and can save up to 35% power consumption for the whole read channel. An analog DFE-based timing recovery loop is implemented to avoid the extremely long latency in the digital signal processing path (Viterbi decoder). The measured performances is 1.1 dB off simulations at 800 MHz and 1.6 dB off at 1GHz. The chip draws 240 mW from a 3.3 V supply at 800MHz clock and 380 mW from a 3.6 V supply at 1 GHz clock.     

H.264/AVC视频编码标准中CAVLC解码器的设计

提出了一种应用于H.264/AVC的快速低功耗CAVLC解码器设计方法.对较复杂的几个模块进行了算法和结构上的优化,减少了占用的硬件资源,降低了实现复杂性.仿真结果表明:采用该方法设计的解码器可以正确解码每个变换块中的变换系数,且能在一个时钟周期解出一个句法,完全可以满足H.264视频实时解码的要求.     

Design Methodology for a DVB Satellite Receiver ASIC

This contribution describes design methodology and implementation of a single-chip timing and carrier synchronizer and channel decoder for digital video broadcasting over satellite (DVB-S). The device consists of an A /D converter with AGC, timing and carrier synchronizer with matched filter, Viterbi decoder including node synchronization, byte and frame synchronizer, convolutional de-interleaver, Reed Solomon decoder, and a descrambler.The system was designed in accordance with the DVB specifications. It is able to perform Viterbi decoding at data rates up to 56 Mbit /s and to sample the analog input values with up to 88 MHz. The chip allows automatic acquisition of the convolutional code rate and the position of the puncturing mask. The symbol synchronization is performed fully digitally by means of interpolation and controlled decimation. Hence, no external analog clock recovery circuit is needed.For algorithm design, system performance evaluation, co-verification of the building blocks, and functional hardware verification an advanced design methodology and the corresponding tool framework are presented which guarantee both short design time and highly reliable results. The chip has been fabricated in a 0.5 µm CMOS technology with three metal layers. A die photograph is included.     

A two-dimensional product code with robust soft-decision decoding

The performance of a relatively simple two-dimensional (2-D) product code is considered. The row code is a short constraint length convolutional code, and the column code is a high-rate block code. Both the rows and columns are decoded with soft-decision maximum likelihood decoding. The soft output Viterbi algorithm (SOVA) is used to decode the rows. In one case, the same decoder may be used for the rows and the columns. It is shown that, depending on the rate of the row code, reliable signaling is achieved within about 1.0 to 1.5 dB of the R₀ limit. Results are given for a particular impulsive noise channel; it is seen that performance is robust over a wide range of channel conditions     

Low-power Viterbi decoder for CDMA mobile terminals

An efficient state-sequential very large scale integration (VLSI) architecture and low-power design methodologies ranging from the system-level to the layout-level are presented for a large-constraint-length Viterbi decoder for code division multiple access (CDMA) digital cellular/personal communication services (PCS) applications. The low-power design approaches are also applicable to many other systems and algorithms. VLSI implementation issues and prototype fabrication results for a state-sequential Viterbi decoder for convolutional codes of rate 1/2 and constraint-length 9 are also described. The chip's core, consisting of approximately 65 k transistors, occupies 1.9 mm by 3.4 mm in a 0.8-μm triple-layer-metal n-well CMOS technology. The chip's measured total power dissipation is 0.24 mW at a 14.4 kb/s data-rate with 0.9216 MHz clocking at a supply voltage of 1.65 V. The Viterbi decoder presented here is the lowest power and smallest area core in its class, to the best of our knowledge     

A multi-D trellis decoder for A 155 Mb/s concatenated codec

An implementation of a 16 state, rate 8/9 six-dimensional (6-D) 8PSK rotationally invariant trellis decoder for use in a concatenated codec is described. The concatenated codec allows transmission of STM-1 signals (at the 155.52 Mb/s information rate) over a 72 MHz satellite transponder. The inner trellis decoder is used with an outer (255,239) RS block decoder. The trellis decoder operates at 165.93 Mb/s and currently has an implementation loss of only 0.2 dB. The concatenated codec achieves a bit error ratio of 10^?10 at an Eb/N⁰ of 8.2 dB (assuming an ideal modem and AWGN channel). Details are given of many Viterbi decoding ‘tricks’ that were used in order to implement the main functions of the decoder on two 10,000 gate equivalent CMOS programmable gate arrays.     

A Viterbi decoder architecture for a standard-agile and reprogrammable transceiver

This paper presents a Viterbi decoder (VD) architecture for a programmable data transmission system, implemented using a Field Programmable Gate Array (FPGA) device. This VD has been conceived as a building block of a software defined radio (SDR) mobile transceiver, reconfigurable on request and capable to provide agility in choosing between different standards. UMTS and GPRS Viterbi decoding is achieved by choosing different coding rates and constraint lengths, and the possibility to switch, at run time, between them guarantees a high degree of programmability. The architecture has been tested and verified with a Xilinx XC2V2000 FPGA for providing a generalized co-simulation/co-design testbed. The results show that this decoder can sustain an uncoded data rate of about 2 Mbps, with an area occupancy of 46%, due to the efficient resources reuse.     

Frame error rates for convolutional codes on fading channels andthe concept of effective Eb/N0

Estimation of Viterbi decoder performance over channels with time-varying received signal levels is the subject of this paper. This work is motivated by a desire to obtain good estimates of the frame error rate (FER) for convolutional codes with bit-level interleaving over fading channels subject to practical power control algorithms. The convolutional code performance is quantified through the FER and effective E_b/N₀. where the latter is defined as the E_b/N₀ on an additive white Gaussian noise (AWGN) channel that results in the same FER. Given a received vector of (time-varying) E_b/N₀ values, we compute analytic estimates for the probability of frame error and the effective E_b /N₀ for a Viterbi decoder and interleaver combination. In particular, we validate our analysis using the R=1/3 convolutional code and interleaver used on the IS-95 CDMA reverse channel. Comparisons with simulations show that even for E_b/N₀ vectors with very large variations, our proposed estimates are good to within 0.2 dB for the effective E_b/N₀, giving FER estimates within a factor of two-five of the simulations     

CDMA2000系统中通用高速维特比译码器的设计与实现

本文描述了一种可用于 CDMA2 0 0 0通信系统的通用高速维特比译码器基于 FPGA的设计与实现。该维特比译码器具有通用性和高速性 ,它支持可变码率、可变帧长的译码。同时它采用四个 ACS并行运算的结构 ,译码速度可高达 5 88kbit/s,可以方便地运用于第三代移动通信系统和其它许多系统