Isolation of Failing Scan Cells through Convolutional Test Response Compaction

This paper describes a non-recursive fault diagnosis technique for scan-based designs with convolutional test response compaction. The proposed approach allows a time-efficient and accurate identification of failing scan cells using Gauss–Jordan elimination method.

利用奇偶树实现测试响应压缩

为了减少利用奇偶树压缩测试响应时的邦联覆盖损失,提出了一种输出端分组压缩的方法。遇敏感邦联对输出端的影响把电路的输出疝集合分成若干子集,依然再把每个子集中的输出连接到各自的奇偶树,构成一个奇偶树集,从而可以实现对偶敏感故障的检测,进而提高对可检测邦联的覆盖。最后,分析了由于奇偶树的引入带来的故障覆盖率的损失及奇偶树中故障的检测。     

基于边界扫描的非完全BS电路板测试诊断技术

由BS器件和非BS器件组装的非完全BS电路板仍将在今后相当长时间内广泛存在,如何对它们应用边界扫描测试是板级边界扫描测试技术需要研究的关键问题.本文从非完全BS电路板的测试性优化设计入手,举例说明了基于边界扫描的非完全BS电路板测试诊断技术的原理和过程.     

基于扫描链的FPGA可编程逻辑模块测试

随着FPGA规模的不断增大和结构的日益复杂,FPGA的测试也变得越来越困难.由此提出了一种可配置的FPGA芯核扫描链设计,并讨论了基于扫描链的可编程逻辑模块（Configuration Logic Blocks CLB）测试.提出的扫描设计可以通过配置调整扫描链的构成,从而能够处理多个寄存器故障,且在有寄存器故障发生时,重新配置后能继续用于芯片的测试.基于扫描链的CLB测试,以扫描链中的寄存器作为CLB测试的可控制点和可观测点,降低了对连线资源的需求,可以对所有的CLB并行测试,在故障测试的过程中实现故障CLB的定位,与其它方法相比,所需配置次数减少50%以上.     

扫描测试和扫描链的构造

本文首先论述了扫描设计与测试向量自动生成（ATPG）这种测试方法的关键技术，并由此为依据，提出部分扫描设计中，扫描链构造的分层次的三个选取原则。     

Combining Scan Test and Built-in Self Test

For digital chips containing functional logic and embedded memories, these are usually tested separately: Scan test is used for testing functional logic; Memory Built-in Self Test (MBIST) is run for embedded memories. A new approach is proposed to exercise scan test and MBIST in parallel in order to reduce production test time and improve stress tests. It requires only small additional logic and allows to simultaneously run both test modes. In general, the approach can be used to control simultaneously scan test and any Built-in Self Test (BIST) providing a simple pass/fail result.     

X-tolerant Test Data Compaction with Accelerated Shift Registers

Using the timing flexibility of modern automatic test equipment (ATE) test response data can be compacted without the need for additional X-masking logic. In this article the test response is compacted by several multiple input shift registers without feedback (NF-MISR). The shift registers are running on a k-times higher clock frequency than the test clock. For each test clock cycle only one out of the k outputs of each shift register is evaluated by the ATE. The impact of consecutive X values within the scan chains is reduced by a periodic permutation of the NF-MISR inputs. As a result, no additional external control signals or test set dependent control logic is required. The benefits of the proposed method are shown by the example of an implementation on a Verigy ATE. Experiments on three industrial circuits demonstrate the effectiveness of the proposed approach in comparison to a commercial DFT solution.     

结合结构特征基于测试集重排序的故障诊断方法

故障诊断是集成电路领域中的重要研究方向,基于测试激励集方法求解候选故障诊断是目前较为高效的诊断方法,而GTreord是目前具有较高诊断准确性的方法.在对GTreord方法深入研究的基础上,本文依据测试激励与候选故障诊断解之间的结构特征,通过分析电路故障输出响应,提出结合结构特征的测试激励集重排序的候选诊断(Reor-d...     

Scan Latch Design for Test Applications

This JETTA letter describes a new single-latch scan design that uses a single clock for both scan and functional operations. A test mode signal differentiates between normal and test operations. This new design enjoys savings in circuits, pins, test time, and also enjoys the benefits of a high-speed scan capability.     

Scan Test Strategy for Asynchronous-Synchronous Interfaces

In the coming years, the well-known synchronous design style will not be able to keep pace with the increase speed and capabilities of integration of advanced processes. New design paradigms, like core reuse of the already designed synchronous modules and asynchronous designs, are considered in order to cope with the ever increasing complexity. The future SoCs will contain multiple synchronous and asynchronous cores. Asynchronous design will become more and more common among digital designers, while synchronous-asynchronous interactions will emerge as a key issue in the future SoC designs.This paper will present test strategies for 2-phase asynchronous-synchronous interfaces and vice versa. It will be shown how test vectors can be automatically generated using commercially available ATPG tools. The generated ATPG vectors will be able to test all stuck-at-faults within the asynchronous-synchronous interfaces.     

Chiba Scan Delay Fault Testing with Short Test Application Time

Delay fault testing using a scan design facilitating two-pattern testing, called Chiba scan testing, requires a long test application time (TAT) compared with well-known delay fault testing. This paper presents an improved Chiba scan testing with short TAT by providing a test compaction. In addition, it presents a test generation for the Chiba scan testing improved by the proposed compaction. Evaluation shows that, for robust path delay fault testing on ISCAS89/ ADDENDUM benchmark circuits, the TAT of Chiba scan testing with the proposed compaction is, on average, 47% and 21% shorter than that of Chiba scan testing without test compaction and that of enhanced scan testing with the conventional test compaction, respectively. In addition, in many cases, the fault coverage of the proposed testing is higher than that of launch-off-capture (LoC) and launch-off-shift (LoS) testing with the same TAT.     

Multi-Level Bioinspired Microlattice with Broadband Sound-Absorption Capabilities and Deformation-Tolerant Compressive Response

Owing to the omnipresent noise and crash hazards, multifunctional sound-absorbing, and deformation-tolerant materials are highly sought-after for practical engineering design. However, challenges lie with designing such a material. Herein, leveraging the inherent mechanical robustness of the biological cuttlebone, by introducing dissipative pores, a high-strength microlattice is presented which is also sound-absorbing. Its absorption bandwidth and deformation tolerance are further enhanced by introducing another level of bioinspiration, based on geometrical heterogeneities amongst the building cells. A high-fidelity microstructure-based model is developed to predict and optimize properties. Across a broad range of frequencies from 1000 to 6300 Hz, at a low thickness of 21 mm, the optimized microlattice displays a high experimentally measured average absorption coefficient of 0.735 with 68% of the points higher than 0.7. The absorption mechanism attributes to the resonating air frictional loss whilst its broadband characteristics attribute to the multiple resonance modes working in tandem. The heterogeneous architecture also enables the microlattice to deform with a deformation-tolerant plateau behavior not observed in its uniform counterpart, which thereby leads to a 30% improvement in the specific energy absorption. Overall, this work presents an effective approach to the design of sound and energy-absorbing materials by modifying state-of-the-art bioinspired structures.     

Reusing Scan Chains for Test Pattern Decompression

The paper presents a method for testing a system-on-a-chip by using a compressed representation of the patterns on an external tester. The patterns for a certain core under test are decompressed by reusing scan chains of cores idle during that time. The method only requires a few additional gates in the wrapper, while the mission logic is untouched. Storage and bandwidth requirements for the ATE are reduced significantly.     

扫描电路测试功耗综述

随着集成电路制造技术的发展.高集成度使得测试时的功耗成为集成电路设计必须考虑的一个重要因素,低功耗测试也就成为了测试领域一个令人关注的热点.目前,低功耗测试技术的研究还在发展之中,工业生产中低功耗测试方法还没有得到充分的应用.在集成电路中采用扫描结构的可测试性设计方法,能够提高测试覆盖率.缩短测试时间,已在集成电路测试中得到大量应用.基于扫描结构的数字集成电路,学术界已提出了许多方法降低该电路的测试功耗,本文对此方面的研究进行综述.随着测试技术的发展,测试功耗的理论也将日益深入.     

动态向量调整的多扫描链测试数据压缩

 由于多扫描链测试方案能够提高测试进度,更适合大规模集成电路的测试,因此提出了一种应用于多扫描链的测试数据压缩方案.该方案引入循环移位处理模式,动态调整向量,能够保留向量中无关位,增加向量的外延,从而提高向量间的相容性和反向相容性;同时,该方案还能够采用一种有效的参考向量更替技术,进一步提高向量间的相关性,减少编码位数.另外,该方案能够利用已有的移位寄存器,减少不必要的硬件开销.实验结果表明所提方案在保持多扫描链测试优势的前提下能够进一步提高测试数据压缩率,满足确定性测试和混合内建自测试.     

Test Set Compaction Using Relaxed Subsequence Removal

Recent work observed that a subset of states are frequently visited during the simulation of a test set for a sequential circuit. Re-visiting a state implies that a cycle has been traversed in the state diagram. Removal of subsequence responsible for the cycle can lead to static compaction. The size of a cycle is the number of vectors in its subsequence. In this work, we extend the subsequence removal technique to provide significantly higher static compaction for sequential circuits. We show that state relaxation techniques can be used to identify more or larger cycles in a test set. State relaxation creates more opportunities for subsequence removal and hence, results in better compaction. Relaxation of a state is possible since not all memory elements in a finite state machine have to be specified for a state transition. The proposed technique has several advantages: (1) test sets that could not be compacted by existing subsequence removal techniques can now be compacted, (2) the size of cycles in a test set can be significantly increased by state relaxation and removal of the larger sized cycles leads to better compaction, (3) only two fault simulation passes are required as compared to trial and re-trial methods that require multiple fault simulation passes, and (4) significantly higher compaction is achieved in short execution times as compared to known subsequence removal methods. Experiments on ISCAS89 sequential benchmark circuits and several synthesized circuits show that the proposed technique consistently results in significantly higher compaction in short execution times.     

Static Test Compaction for Scan-Based Designs to Reduce Test Application Time

We propose a static compaction procedure to reduce the test application time for full and partial scan synchronous sequential circuits. The procedure accepts as input a set of test subsequences. A test subsequence consists of a sequence of primary input vectors, and a vector to be scanned-in before the input sequence is applied. The procedure uses two operations to reduce the test application time. The first operation combines test subsequences. The second operation reduces the lengths of the combined subsequences (the length of a test subsequence is the length of the input sequence included in it). The reductions in test application time of the proposed procedure are demonstrated through experimental results.     

一种基于边界扫描的FIFO测试方法

针对含先进先出存储器(FIFO)电路板故障检测的问题,提出一种基于边界扫描技术编写Macro对FIFO进行读写数据的测试方法,介绍边界扫描技术测试FIFO的基本原理。通过设计适配板,应用边界扫描测试工具ScanWorks,建立边界扫描链路,编写Macro测试代码,利用JTAG接口进行间接控制,实现对FIFO进行故障检测。给出了测试系统硬件框图、简述了适配板设计要点,提供FIFO电路连接图和软件流程图,并分析FIFO测试的完备性,最后还对FIFO进行了测试验证。     

扫描设计中测试逻辑的研究

本文首先分析了时序元件的不可测因素，介绍了扫描设计前增加测试逻辑的设计方法。实践证明，该方法简便易行，故障覆盖率高达99％。