Low-power fault-tolerant interconnect method based on LCDMA and duplication

High computing capabilities and limited number of input/output pins of modern integrated circuits require an efficient and reliable interconnection architecture. The proposed communication scheme allows a large number of IP cores to send data over a single wire using logic code division multiple access (LCDMA) technique. Reliability is increased by using hardware redundancy, and three LCDMA-based fault tolerant designs are proposed: (a) duplication with logic comparison (DLC), (b) conventional triple modular redundancy (TMR), and (c) triple modular redundancy with sign voter (TSV). With aim to detect a received bit from chip sequence, LCDMA–DLC and LCDMA–TSV designs compare absolute values of the sums, while LCDMA–TMR compares only sign bits of the sums generated at the outputs of decoders. All proposed designs are implemented in FPGA and ASIC technologies. MATLAB simulation results show that increasing the length of spreading codes affects to an increase in reliability. A comparative analysis of the proposed fault tolerant designs in terms of hardware complexity, latency, power consumption and error detecting and correcting capability is conducted. It is shown that LCDMA–DLC design has lower hardware overhead and power consumption, with satisfactory better bit error rate (BER) performance, in comparison to LCDMA–TMR and LCDMA–TSV approach.     

A New Approach to Single Event Effect Tolerance Based on Asynchronous Circuit Technique

Some asynchronous circuit techniques are proposed to provide a new approach to Single Event Effect (SEE) tolerance in synchronous circuits. Two structures, Double Modular Redundancy (DMR) and Temporal Spatial Triple Modular Redundancy with Dual Clock Triggered Register (TSTMR-D), are presented. Three SEE tolerant 8051 cores with DMR, TSTMR-D and traditional Triple Modular Redundancy (TMR) are implemented in SMIC 0.35 μm process. The results of fault injection experiments indicate that DMR has a relatively low overhead on both area and latency than TMR, while tolerates SEU in sequential logic. TSTMR-D provides tolerance for both SEU and SET with reasonable area and latency overhead.     

TMR voting in the presence of crosstalk faults at the voter inputs

In high reliability systems, the effectiveness of fault tolerant techniques, such as Triple-Modular-Redundancy (TMR), must be validated with respect to the faults that are likely in the current technology. In todays' Integrated Circuits (IC), this is the case of crosstalks, whose importance is growing because of device & interconnect scaling. This paper analyzes the problem of crosstalk faults at the inputs of voters in TMR systems. In particular, possible problems are illustrated, and it is shown that such crosstalk may invalidate the reliability of both voting, and diagnosing operations. The problem is analyzed from a probabilistic point of view. Its occurrence is estimated by using a set of TMR systems obtained with combinational benchmarks as functional modules. The possible problems of such operations are discussed in the presence of crosstalk faults. It is shown that crosstalk may invalidate the reliability of both voting, and diagnosis operations. A probabilistic model of the voting & diagnosis operations in the presence of crosstalk has been developed. Finally, such a model has been used to estimate the probability of voting & diagnosis failures in a set of TMR systems obtained by using combinational benchmarks as functional modules. We have shown that the presence of crosstalk faults at voter inputs may impair both the voting, and the diagnosis mechanisms. This problem has been quantified by applying a probabilistic model of crosstalk fault effects on voting and diagnosis to a set of benchmark circuits. Results show that crosstalk may create a reliability problem for TMR systems. Such a problem can be solved by using on-line testing or design for testability providing additional controllability & observability to the replicated functional units.     

Classification of Defective Analog Integrated Circuits Using Artificial Neural Networks

This paper presents a new approach for detecting defects in analog integrated circuits using the feed-forward neural network trained by the resilient error back-propagation method. A feed-forward neural network has been used for detecting catastrophic faults randomly injected in a simple analog CMOS circuit by classification the differences observed in supply current responses of good and faulty circuit. The experimental classification was performed for time and frequency domain, followed by a comparison of results achieved in both domains. It was shown that neural networks might be very efficient and versatile approach for test of analog circuits since an arbitrary fault class or circuit's parameter can be analyzed. Considered defect types and their successful detection by the neural network; and a possible off-chip hardware implementation of the proposed technique are discussed as well. Moreover, optimized hardware architecture of the selected neural network type was designed using VHDL for FPGA realization.     

Design of a novel fault-tolerant voter circuit for TMR implementation to improve reliability in digital circuits

Due to the shrinking of feature size and significant reduction in noise margins, nanoscale circuits have become more susceptible to manufacturing defects, interference from radiation and noise-related transient faults. Many of these faults are not permanent in nature but their occurrence can result in malfunctioning of circuits, either due to complexity of digital circuits or due to interaction with software. A fault-tolerant scheme such as triple-modular redundancy (TMR) is being implemented increasingly in digital systems. One of the drawbacks of this scheme is that the reliability of the voter circuit is assumed to be very high, which may not be true. Most of the implementation of digital circuits is in the form of integrated circuit; so all the circuit elements are fabricated with same technology and hence reliability of all the components is usually same. In this paper we are presenting a novel fault-tolerant voter circuit which itself can tolerate a fault and give error free output by improving the overall system’s reliability.     

Noise in interconecction lines for submicrometer CMOS integrated circuits

The growing use of high performance portable systems is the main driving force for the significant advance in the technology of VLSI-CMOS integrated circuits. This advance has been carried out through scaling the transistor and interconnection sizes. However, as the transistor's size and interconnections are getting smaller, the signal integrity is becoming a critical issue. Therefore it is required to develop noise tolerant design circuit techniques in order to enhance the noise tolerance. In addition, these techniques should have a minimum impact on the circuit performance. In this paper, the noise immunity of dynamic logical circuits as the technology scales down is analyzed by using a reliable scaling scenario, and a new noise tolerant design technique is proposed. Prototype circuits implementing the proposed technique have been designed and fabricated. A one-bit carry look-ahead adder was designed using 0.35 mm CMOS-AMS technology. The experimental results show that the design technique here presented, results in an improvement of the ANTE by a factor of 3.4X when compared with the conventional TSPC, and an improvement by a factor of 1.7X when compared with the best noise tolerant technique currently published.     

Enhanced architectures for soft error detection and correction in combinational and sequential circuits

In this paper two new methods for the design of fault-tolerant pipelined sequential and combinational circuits, called Error Detection and Partial Error Correction (EDPEC) and Full Error Detection and Correction (FEDC), are described. The proposed methods are based on an Error Detection Logic (EDC) in the combinational circuit part combined with fault tolerant memory elements implemented using fault tolerant master–slave flip-flops. If a transient error, due to a transient fault in the combinational circuit part is detected by the EDC, the error signal controls the latching stage of the flip-flops such that the previous correct state of the register stage is retained until the transient error disappears. The system can continue to work in its previous correct state and no additional recovery procedure (with typically reduced clock frequency) is necessary. The target applications are dataflow processing blocks, for which software-based recovery methods cannot be easily applied. The presented architectures address both single events as well as timing faults of arbitrarily long duration. An example of this architecture is developed and described, based on the carry look-ahead adder. The timing conditions are carefully investigated and simulated up to the layout level. The enhancement of the baseline architecture is demonstrated with respect to the achieved fault tolerance for the single event and timing faults. It is observed that the number of uncorrected single events is reduced by the EDPEC architecture by 2.36 times compared with previous solution. The FEDC architecture further reduces the number of uncorrected events to zero and outperforms the Triple Modular Redundancy (TMR) with respect to correction of timing faults. The power overhead of both new architectures is about 26–28% lower than the TMR.     

Genetic-Algorithm-Based Method for Optimal Analog Test Points Selection

A new approach to an optimal analog test points selection is proposed. The described method uses ambiguity set concept and evolutionary computations to determine the optimal set of analog test points. After a brief introduction to analog testing and genetic algorithms, the proposed strategy is explained. The presented evolutionary approach is illustrated by a practical example of analog circuit and by a series of hypothetical circuits. The efficiency of the technique is compared with a method based on entropy index, and the obtained results are discussed     

NBTI degradation and its impact for analog circuit reliability

A methodology to quantify the degradation at circuit level due to negative bias temperature instability (NBTI) has been proposed in this work. Using this approach, a variety of analog/mixed-signal circuits are simulated, and their degradation is analyzed. It has been shown that the degradation in circuit performance is mainly dependent on the circuit configuration and its application rather than the absolute value of degradation at the device level. In circuits such as digital-to-analog converters, NBTI can pose a serious reliability concern, as even a small variation in bias currents can cause significant gain errors.     

Soft Fault Diagnosis in Analog Circuits Based on Bispectral Models

Aiming at the problem to locate soft faults in analog circuits, a new approach based on bispectral models is proposed. First, the Volterra kernels of the circuit under test (CUT) are calculated. Then, the Volterra kernels are used to construct bispectral models. By comparison with the fault features of the constructed models, soft faults of linear and weak nonlinear components in the analog circuit are identified and the faults are located. Simulations and experiments show the effectiveness of the proposed method in analog circuits.,     

Test Generation for Mixed-Signal Devices Using Signal Flow Graphs

We describe a new reverse simulation approach to analog and mixed-signal circuit test generation that parallels digital test generation. We invert the analog circuit signal flow graph, reverse simulate it with good and bad machine outputs, and obtain test waveforms and component tolerances, given circuit output tolerances specified by the functional test needs of the designer. The inverted graph allows backtracing to justify analog outputs with analog input sinusoids. Mixed-signal circuits can be tested using this approach, and we present test generation results for two mixed-signal circuits and four analog circuits, one being a multiple-input, multiple-output circuit. This analog backtrace method can generate tests for second-order analog circuits and certain non-linear circuits. These cannot be handled by existing methods, which lack a fault model and a backtrace method. Our proposed method also defines the necessary tolerances on circuit structural components, in order to keep the output circuit signal within the envelope specified by the designer. This avoids the problem of overspecifying analog circuit component tolerances, and reduces cost. We prove that our parametric fault tests also detect all catastrophic faults. Unlike prior methods, ours is a structural, rather than functional, analog test generation method.     

An Analog Programmable Multidimensional Radial Basis Function Based Classifier

A compact analog programmable multidimensional radial basis function (RBF)-based classifier is demonstrated. The probability distribution of each feature in the templates is modeled by a Gaussian function that is approximately realized by the bell-shaped transfer characteristics of a proposed floating-gate circuit, which we term a floating-gate bump circuit. The maximum likelihood, the mean, and the variance of the distribution are stored in floating-gate transistors and are independently programmable. By cascading these floating-gate bump circuits, the overall transfer characteristics approximate a multivariate Gaussian function with a diagonal covariance matrix. An array of these circuits constitute a compact multidimensional RBF-based classifier that can easily implement a Gaussian mixture model. When followed by a winner-take-all circuit, the RBF-based classifier forms an analog vector quantizer. We use receiver operating characteristic curves and equal error rate to evaluate the performance of our RBF-based classifier as well as a resultant analog vector quantizer. We show that the classifier performance is comparable to that of digital counterparts. The proposed approach can be at least two orders of magnitude more power efficient than the digital microprocessors at the same task.     

高效容错可逆的汉明码编码和检测电路

为了检验传输过程中数据的可靠性,设计了容错可逆的汉明码电路。提出了一种新型的可逆逻辑门（FVG）,它是一种四变量奇偶保持门能容错,并且完成了FVG门等价的量子实现。利用FVG 门和现有的容错可逆门,实现了汉明码编码电路和检测电路。以(7,4)汉明码设计为实例,根据量子代价和延迟对其进行性能评估,结果证明该电路比现有电路的性能提高10% ? 20%,仿真实验结果显示,电路逻辑结构正确,性能可靠。     

An effective thermal circuit model for electro-thermal simulation of SOI analog circuits

A physics-based thermal circuit model is developed for electro-thermal simulation of SOI analog circuits. The circuit model integrates a non-isothermal device thermal circuit with interconnect thermal networks and is validated with high accuracy against finite element simulations in different layout structures. The non-isothermal circuit model is implemented in BSIMSOI to account for self-heating effect (SHE) in a Spice simulator, and applied to electro-thermal simulation of an SOI cascode current mirror constructed using different layouts. Effects of layout design on electric and thermal behaviors are investigated in detail. Influences of BOX thickness are also examined. It has been shown that the proposed non-isothermal approach is able to effectively account for influences of layout design, self-heating, high temperature gradients along the islands, interconnect temperature distributions, thermal coupling, and heat losses via BOX and interconnects, etc., in SOI current mirror structures. The model provides basic concepts and thermal circuits that can be extended to develop an effective model for electro-thermal simulation of SOI analog ICs.     

New Gate-Bias Voltage-Generating Technique With Threshold-Voltage Compensation for On-Glass Analog Circuits in LTPS Process

A new proposed gate-bias voltage-generating technique with threshold-voltage compensation for analog circuits in the low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) is proposed. The new proposed gate-bias voltage-generating circuit with threshold-voltage compensation has been successfully verified in an 8-mum LTPS process. The experimental results have shown that the impact of TFT threshold-voltage variation on the biasing circuit can be reduced from 30% to 5% under a biasing voltage of 3 V. The new proposed gate-bias voltage-generating technique with threshold-voltage compensation enables the analog circuits to be integrated and implemented by the LTPS process on glass substrate for an active matrix LCD panel.     

A Novel Approach for Analog Circuit Fault Prognostics Based on Improved RVM

In order to estimate the remaining useful performance (RUP) of analog circuits precisely in real time, an analog circuit fault prognostics framework is proposed in the paper. Output voltages are extracted from circuit responses as features to calculate cosine distance which can reflect the health condition of analog circuits. Relevance vector machine (RVM) which has been improved by particle swarm optimization (PSO) algorithm is applied to estimate the RUP. Twelve case studies involving bandpass filter, highpass filter and nonlinear circuit have validated the predict performance of the approach. Simulation results demonstrate that the proposed approach has higher prediction precision.     

Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems

This paper presents the design, layout, and testability analysis of delay-insensitive circuits on cellular arrays for nanocomputing system design. In delay-insensitive circuits the delay on a signal path does not affect the correctness of circuit behavior. The combination of delay-insensitive circuit style and cellular arrays is a useful step to implement nanocomputing systems. In the approach proposed in this paper the circuit expressions corresponding to a design are first converted into Reed–Muller forms and then implemented using delay-insensitive Reed–Muller cells. The design and layout of the Reed–Muller cell using primitives has been described in detail. The effects of stuck-at faults in both delay-insensitive primitives and gates have been analyzed. Since circuits implemented in Reed–Muller forms constructed by the Reed–Muller cells can be easily tested offline, the proposed approach for delay-insensitive circuit design improves a circuit’s testability. Potential physical implementation of cellular arrays and its area overhead are also discussed.     

一种高性能低功耗直接数字频率合成器的设计

文章基于分段线性近似算法提出分段泰勒二阶近似算法，从频谱纯度分析了该算法的优越性，讨论了系数位数和分段数的选取，最后结合硬件优化的系统结构，设计实现了SFDR达102．3dB的数字频率合成器。综合结果表明，该算法实现的系统面积上要比分段线性近似算法的系统小20％，功耗上也小39．5％。与现有的其他数字频率合成器比较表明，在设计高频谱性能DDFS方面，其在功耗和面积上都具有较大优势。     

Analog circuit sizing using local biasing

The analog circuit design approach based on local biasing is shown to be very attractive as it removes the nonlinearity in the biasing procedure. Based on this design approach, we offer a new technique for the sizing of analog integrated circuits. The proposed technique is based on the relations that exist between linear elements of a cut-set or a loop when the voltages and currents in the remaining elements are held fixed. These relations enable the designer to fix a circuit variable (biasing current or voltage of a transistor) in exchange for a set of interrelated element values that can be independently changed. The proposed procedure allows us to directly change the element values or the DC parameter values for the active loads without being concerned about the DC biasing. Therefore, the circuit designer is able to manage tradeoffs in the design by comparing multiple solutions that meet the desired criteria. Moreover, multiple circuit simulations are not necessary in the case when any of the calculated element values is not realistic or workable.