Control loop design for two-stage DC-DC converters with low voltage/high current output

This work presents a general analysis framework for control loop design of two-stage converters. The results yield a thorough explanation of various loop design approaches. A three-loop method to extend the system bandwidth is proposed. The new control design algorithm is applied to a 48 V/3.3 V two-stage converter. Experiments verify the effectiveness of the control loop design approach.     

微型天线伺服系统保主导极点配置控制器设计

给出了一种微型天线伺服系统保主导极点配置PID控制器设计方法.首先,针对伺服系统的动态方框图模型,将其划分为电流环、速度环和位置环3个设计环节.然后,通过引入前置滤波器,根据主导极点配置PID控制器设计方法,设计了每个环节的控制器参数,使之满足期望的性能指标要求.仿真结果表明,所设计的伺服控制器能够保证系统对给定位置信...     

Experimental validation of FastSLAM algorithm integrated with a linear features based map

In this paper the Simultaneous Localization And Mapping (SLAM) problem in unknown indoor environments is addressed. A probabilistic approach integrating FastSLAM algorithm and a line feature map is developed and validated. Experimental validation is performed by a smart wheelchair equipped with proprioceptive and exteroceptive sensors in an office like environment where loop closing is achieved without any dedicated algorithm. Geometric hypotheses of orthogonal line features are considered to enhance the performance of the algorithm in the considered environment. The proposed approach results in a computationally efficient solution to the SLAM problem and the high quality sensor measurements allow to maintain a good localization of the mobile base and a compact representation of the environment.     

基于形式演算和不变式验证的可信算法程序构造

The paper presents a formal and practical approach to dependable algorithm development. First, starting from a formal specification based on the Eindhoven quantifier notation, a problem is regularly reduced to subproblems with less complexity by using a concise set of calculation rules, the result of which establishes a recurrence based algorithm. Second, a loop invariant is derived from the problem specification and recurrence, which certifies the transformation from the recurrence based algorithm to one or more iterative programs. We demonstrate that our approach covers a number of classical algorithm design tactics, develops algorithmic programs together with their proof of correctness, and thus contributes fundamentally to the dependability of computer software.     

面向移动应用的语音编解码开环基音搜索方法

基音周期搜索的准确性将直接影响到语音编码器的编码质量和效率。本文根据AMR—WB＋标准中基音周期搜索算法会发生检测基音倍频和半频错误,提出了开环基音搜索算法。该算法以白相关函数为基础,利用基音周期的平滑性,引入基音周期全局参考作为基音周期判断的辅助条件,有效解决了基音周期加倍的问题并在基音周期预测中体现基音周期的平滑性,实验结果表明本文算法性能优于AMR—WB＋中的算法性能。该算法已应用到AVS—P10移动音频编解码框架中。     

雷达目标角度跟踪环路滤波器设计新方法

角度跟踪环路在机载雷达对目标的距离、速度、角度3维联合跟踪中起着至关重要的作用。该文分析指出传统采用卡尔曼滤波算法形成角度跟踪环路对机动目标角度进行跟踪时跟踪精度低,角跟踪误差收敛速度慢的缺点,提出弯曲度检测跟踪环路滤波器(Bend Degree Tracking Loop Filter, BDTLF)设计方法,其利用弯曲度检测角度曲线拐点,自适应地调节环路滤波器环路等效噪声带宽,并以此来控制角度跟踪环路。此算法加快了角跟踪误差的收敛速度,减轻了拐点处的角度滤波扰动,保持了滤波性能的连续性。计算机仿真结果验证了该文方法相比于卡尔曼滤波算法、粒子滤波算法、-- 滤波算法及恒定系数环路滤波器方法,对弱机动目标角度跟踪具有更加出色的性能。     

有源多线圈耦合网络网孔方程的直接建立算法

本文在提出了用回路描述电路元件的拓扑结构以后,给出了具有受控源和多线圈耦合的平面网络网孔方程的直接建立算法。网络方程的个数等于网络的网孔数。本文方法得到的网络方程在此类网络中比改进节点法方程数少,与一般节点法相比,方程建立的过程简单明了,只需对各元件的拓扑结构和参数进行检索即可。     

A cognitive model‐based approach for autonomic fault management in OpenFlow networks

Autonomic network management is an approach to the management of complex networks and services that incorporates the detection, diagnosis and reconfiguration, as well as optimization, of their performance. A control loop is fundamental as it facilitates the capture of the current state of the networks and the reconfiguration of network elements without human intervention. For new networking architectures such as software‐defined networking and OpenFlow networks, in which the control plane is moved onto a centralized controller, an efficient control loop and decision making are more crucial. In this paper, we propose a cognitive control loop based on a cognitive model for efficient problem resolving and accurate decision making. In contrast to existing control loops, the proposed control loop provides reactive, deliberative and reflective loops for managing systems based on analysis of current status. In order to validate the proposed control loop, we applied it to fault management in OpenFlow networks and found that the protection mechanism provides fast recovery from single failures in OpenFlow networks, but it cannot cover multiple‐failure cases. We therefore also propose a fast flow setup (FFS) algorithm for our control loop to manage multiple‐failure scenarios. The proposed control loop adaptively uses protection and FFS based on analysis of failure situations. We evaluate the proposed control loop and the FFS algorithm by conducting failure recovery experiments and comparing its recovery time to those of existing methods. Copyright © 2013 John Wiley & Sons, Ltd.     

一种低复杂度GPS载波跟踪环路设计

 GPS接收机载波跟踪环路的鉴别器和滤波器设计决定了跟踪环路的性能,也在很大程度上决定了GPS接收机的性能.本文在分析了传统锁相环和锁频环鉴别器算法的基础上,提出了一种锁相锁频环共用四象限反正切函数单元的鉴别器算法;同时,在研究了基于双线性Z变换积分器与矩形波数字积分器的滤波算法基础上,提出了一种基于矩形波数字积分器的锁频环辅助锁相环的滤波器算法.综合这两种新算法给出一种低复杂度的GPS接收机锁相锁频环设计方法.通过理论分析与仿真实验,证实该GPS载波跟踪环路设计不但具有良好的跟踪性能,且与传统设计方案相比具有运算量小,复杂度低,占用资源少等优点,更易于工程实现.     

Threshold reduction for demodulating a BPSK suppressed-carrier signal (Corresp.)

If a Costas loop is forced to have a relatively wide bandwidth, for example, to track phase variation due to platform motion, binary phase-shift keying (BPSK) demodulator performance is significantly degraded. However, if the data bits were known, the Costas loop would become equivalent to a phase-locked loop, which has approximately a 6-dB lower tracking threshold for the same loop bandwidth. A delayed-bit estimation algorithm with a recursive structure similar to the Viterbi algorithm is described. The memory in the tracking loop is exploited to correct preliminary bit decisions, as a means of realizing most of this theoretical threshold reduction. Experimental results for a practical digital implementation of the new algorithm for a 50-bit/s data rate and a 20-Hz loop noise bandwidth show a 4-dB improvement in demodulator threshold.     

Steady-State and Dynamic Study of Active Power Filter With Efficient FPGA-Based Control Algorithm

A new approach using field-programmable gate array (FPGA) to implement a fully digital control algorithm of active power filter (APF) is proposed in this paper. This FPGA-based controller integrates the whole signal-processing function of an APF, including synchronous-reference-frame transform, low-pass filter, three-phase phase-locked loop, inverter-current controller, etc. By case studies on the principle, performance, and architecture, these control blocks are implemented in real-time and synthesized into a medium-scale FPGA chip by adopting some useful digital-signal-processing techniques, such as pipelining, folding and strength reduction, with respect to minimization of hardware resource and enhancement of operating frequency. As a result, the whole algorithm needs around 5000 logic elements and can run at synchronous system-clock rates of up to 65 MHz. Experimental results on a laboratory prototype are given to demonstrate performance of the proposed approach during steady-state and dynamic operations.     

Neural-network-based delivery time estimates for prioritized 300-mm automatic material handling operations

This paper deals with lot delivery estimates in a 300-mm automatic material handling system (AMHS), which is composed of several intrabay loops. We adopt a neural network approach to estimate the delivery times for both priority and regular lots. A network model is developed for each intrabay loop. Inputs to the proposed neural network model are the combination of transport requirements, automatic material handling resources, and ratios of priority lots against regular ones. A discrete-event simulation model based on the AMHS in a local 300-mm fab is built. Its outputs are adopted for training the neural network model with the back propagation method. The outputs of the neural network model are the expected delivery times of priority and regular lots in the loop, respectively. For a lot to be transported, its expected delivery time along a potential delivery path is estimated by the summation of all the loop delivery times along the path. A shortest path algorithm is used to find the path with the shortest delivery time among all the possible delivery paths. Numerical experiments based on realistic data from a 300-mm fab indicate that this neural network approach is sound and effective for the prediction of average delivery times. Both the delivery times for priority and regular lots get improved. Specially, for the cases of regular lots, our approach dynamically routes the lots according to the traffic conditions so that the potential blockings in busy loops can be avoided. This neural network approach is applicable to implementing a transport time estimator in dynamic lot dispatching and fab scheduling functions in realizing fully automated 300-mm manufacturing.     

CORDIC算法在跟踪环中的应用与FPGA实现

主要介绍了CORDIC算法在跟踪环鉴别器中的应用,包括码跟踪环、锁频环和锁相环鉴别器,并进行了FPGA实现。在设计中,采用统一CORDIC算法优化方法减少硬件开销,用非流水方式在一个CORDIC运算基本单元中实现了码跟踪环、锁频环和锁相环三种鉴别器。同时对CORDIC运算的精度和位宽进行分析,在保证环路功能的情况下尽量减少硬件资源的使用。在Virtex5 lx220上测试使用了该鉴别器的GPS跟踪环,取得了满意的跟踪效果。     

An efficient bit-loading algorithm for DMT applications

This letter describes an efficient bit allocation algorithm for digital subscriber loop modems that use discrete multi-tone technology. The algorithm computes the optimum bit allocation profile within all constraints and requires fewer computations than the conventional “water-filling” approach. Conventional algorithms are unable to assign data bits to higher frequency bins over long loops with high level of interference due to the power spectrum mask limitation, even if the total power budget is not expended. We propose a novel scheme to distribute data over multiple bins at correspondingly reduced power in these, otherwise unpopulated bins     

基于自适应锁相环的高动态GPS信号载波跟踪算法

提出了一种基于四维卡尔曼滤波的自适应锁相环算法,并将该算法用于高动态GPS信号的载波跟踪.详细推导了卡尔曼滤波与数字锁相环之间的等效性,并给出了相应的环路更新步骤.仿真结果表明,该算法相对于采用固定增益数字锁相环的算法明显地降低了载波跟踪过程的均方根频率误差,提高了接收机的测速精度.     

An adaptive phase alignment algorithm for cartesian feedback loops [Applications corner]

An adaptive algorithm to correct phase misalignments in Cartesian feedback linearization loops for power amplifiers has been presented. It yields an error smaller than 0.035 rad between forward and feedback loop signals once convergence is reached. Because this algorithm enables a feedback system to process forward and feedback samples belonging to almost the same algorithm iteration, it is suitable to improve the performance not only of power amplifiers but also any other digital feedback system for communications systems and circuits such as all digital phase locked loops. Synchronizing forward and feedback paths of Cartesian feedback loops takes a small period of time after the system starts up. The phase alignment algorithm needs to converge before the feedback Cartesian loop can start its ideal behavior. However, once the steady state is reached, both paths can be considered synchronized, and the Cartesian feedback loop will only depend on the loop parameters (open-loop gain, loop bandwidth, etc.). It means that the linearization process will also depend only on these parameters since the misalignment effect disappears. Therefore, this algorithm relieves the power amplifier linearizer circuit design of any task required for solving phase misalignment effects inherent to Cartesian feedback systems. Furthermore, when a feedback Cartesian loop has to be designed, the designer can consider that forward and feedback paths are synchronized, since the phase alignment algorithm will do this task. This will reduce the simulation complexity. Then, all efforts are applied to determining the suitable loop parameters that will make the linearization process more efficient.     

Observer-based cascade control of a 6-DOF parallel hydraulic manipulator in joint space coordinate

This paper addresses the joint space control problem of a 6-DOF (degree of freedom) parallel hydraulic manipulator. High precision motion control of a six-degree parallel manipulator is hardly achieved due to the existence of uncertain payload and other disturbance such as coupling force. A disturbance observer for this parallel manipulator is first constructed to estimate and compensate the unknown disturbance. A cascade control algorithm is then applied to separate the hydraulic dynamics from the mechanical part, which can mask the hydraulic dynamics with an inner loop. With such a control structure, known control design methods within the area of manipulator control can be directly used in the outer loop. In this approach, the complex dynamics and direct kinematics of the parallel manipulator are not required and acceleration feedback is also avoided. Experimental results are presented to show the effectiveness of the proposed scheme.     

一种简单的自适应快收敛LSP环路预防算法

本文首先分析了基于ATM的MPLS网络必须首先解决的环路控制问题，在总结现有环路预防方法的基础上，通过分析环路预防所要达到的最终目标和目标实现过程中的约束条件，导出了在不同条件下使用不同策略的自适应快收敛LSP环路预防新方法，该算法能够“记忆”并充分利用过去环路预防中的经验，结合不同的网络资源状况自适应调整检测量，仿真结果表明，该方法达到了预期目标，且实施简单。     

CORDIC算法在跟踪环中的应用与FPGA实现

主要介绍了坐标旋转数字计算（CORDIC）算法在跟踪环鉴别器中的应用,包括码跟踪环、锁频环和锁相环鉴别器,并进行了FPGA实现。在设计中,采用统一CORDIC算法优化方法减少硬件开销,用非流水方式在一个CORDIC运算基本单元中实现了码跟踪环、锁频环和锁相环三种鉴别器。同时对CORDIC运算的精度和位宽进行分析,在保证环路功能的情况下尽量减少硬件资源的使用。在Virtex5lx220上测试使用了该鉴别器的GPS跟踪环,取得了满意的跟踪效果。     

PHIDEO: High-level synthesis for high throughput applications

This paper describes a new approach to high-level synthesis for high throughput applications. Such applications are typically found in real-time video systems such as HDTV. The method is capable of dealing with hierarchical flow graphs containing loops with manifest boundaries and linear index expressions. The algorithm is based on the model of periodic operations which allows optimizations across loop boundaries. Processing units and storage units are minimized simultaneously. The algorithm is implemented in thePHIDEO system. The major parts of this system are the processing unit synthesis, the scheduler and the memory synthesis including address generation.