1.8 GHz class E power amplifier for wireless communications

The authors present a 1.8 GHz class E power amplifier for wireless communications. A fully integrated class E power amplifier module was designed, fabricated and tested. The circuit was implemented in a self-aligned-gate, depletion mode 0.8 μm GaAs MESFET process. The amplifier delivers 23 dBm of power to the 50Ω load, with a power added efficiency of 57% at a supply voltage of 2.4 V     

EER architecture specifications for OFDM transmitter using a class E amplifier

This letter presents envelope elimination and restoration (EER) architecture specifications in the case of orthogonal frequency division multiplex C band transmission. A key point is the recombination of envelope and phase information by supply modulation of the power amplifier (PA). Imperfections, such as time mismatch and phase noise can reduce the performances of the transmission. Compression and conversion effects when supply modulating the PA are introduced in this letter with the simulation of a class E power amplifier. This amplifier was designed under HP-ADS using a nonlinear MESFET model. Results are reported in terms of error vector measurement and spectrum for two different numbers of sub-carriers 32 and 128 in 16-QAM and 64-QAM cases.     

The class BD high-efficiency RF power amplifier

Class B and class D operation of the same RF power amplifier circuit is not normally possible because of constraints imposed by the tuned output circuit and DC power input circuit. The use of square-wave drive in a current switching class D RF amplifier circuit allows the amplifier to move gradually from current source to current switch operation. This amplifier, called class BD, has a linear transfer characteristic (drive envelope to output envelope) and an efficiency 1.23 times that of a class B RF amplifier with the same peak output. The addition of a resistive AC current path to ground in the DC power input circuit of the class BD RF amplifier allows operation with sinewave driving waveforms. While this lowers the efficiency at the peak output, it can raise it at lower outputs, making possible a factor of 1.57 improvement in efficiency in the amplification of signals with large peak-to-average ratios. The class BD RF amplifier may therefore be used as a broad-band replacement for a Doherty-type amplifier.     

A 1.75-GHz polar modulated CMOS RF power amplifier for GSM-EDGE

This work presents a fully integrated linearized CMOS RF amplifier, integrated in a 0.18-/spl mu/m CMOS process. The amplifier is implemented on a single chip, requiring no external matching or tuning networks. Peak output power is 27 dBm with a power-added efficiency (PAE) of 34%. The amplitude modulator, implemented on the same chip as the RF amplifier, modulates the supply voltage of the RF amplifier. This results in a power efficient amplification of nonconstant envelope RF signals. The RF power amplifier and amplitude modulator are optimized for the amplification of EDGE signals. The EDGE spectral mask and EVM requirements are met over a wide power range. The maximum EDGE output power is 23.8 dBm and meets the class E3 power requirement of 22 dBm. The corresponding output spectrum at 400 and 600 kHz frequency offset is -59 dB and -70 dB. The EVM has an RMS value of 1.60% and a peak value of 5.87%.     

声呐发射机中D类功率放大器的设计

声呐发射机的主要作用是产生具有特定形式的大功率电信号,经过匹配网络(提高发射机输出效率)后再通过换能器将电信号转换为声信号.发射机一般包括信号产生器、功率放大器和发射换能器.详细介绍了一种基于MOSFET的半桥式D类功率放大器设计的步骤和方法,并给出了水声换能器假负载的实验波形,信号畸变与失真较小.根据测试结果证明输出50 kHz左右PWM波时效率达到80％,符合声呐发射机高效率、小体积的设计要求.     

Phase-correcting feedback system for class E power amplifier

A phase-correcting feedback system which reduces the AM-to-PM distortion of Class E power amplifiers for wireless communication is presented in this paper. It comprises a novel limiting amplifier, a phase detector, and a phase shifter all operating at 835 MHz. The phase-correcting feedback together with a Class E power amplifier were fabricated in a 0.8-μm GaAs MESFET process. The limiting amplifier has a phase error less than 2.5°. The phase detector and phase shifter have a sensitivity of 10 mV/degree and 80°/V, respectively. The Class E power amplifier delivers 26.5 dBm to the load with a power added efficiency of 67%. The phase correcting feedback system reduces the 30° phase distortion of the Class E amplifier down to 4°, and its total power dissipation is 21.5 mW     

E类功率放大器研究与应用

分析了E类功率放大器的工作原理,并基于此设计出一种高效高频E类功放,作为无线电能传输系统中发射级的前端驱动电路。运用LTspice仿真软件,对其基本原理电路进行实验分析。为进一步提升输出功率和传输效率,电路还加入了阻抗匹配。仿真结果表明,此电路可实现在6.78 MHz下以85%左右的高效率进行10~30W的功率传输,整体电路结构简单,有实用价值。     

Junction-gate FET RF power amplifier

A junction-gate power field-effect transistor of recent design has been found to yield greater than 25 watts CW at 30 MHz in two modes of circuit configuration. In this investigation, favorable characteristics are explored for potential device utility as a high-reliability low-distortion RF power amplifier.     

UHF power amplifier of class E with a series forming circuit

The E-class mode of a power amplifier with a series (to the switch) forming circuit is investigated. An analysis of such an amplifier model is given. Formulas for the equivalent circuit elements are obtained. The load impedances of its switches on a fundamental frequency and on its harmonics are determined for the considered amplifier and for the device which forms a dual pair with it. The fundamental frequency compensation possibility for the capacitive part on the transistor switch output impedance is demonstrated. With the help of the described approach, the amplifier is developed for a frequency of 915 MHz with a drain efficiency of about 73.2% (PAE is about 71%) and the output power is about 7.32 W.     

高效率E类射频功率放大器

研究了E类RF放大器的电路结构、工作原理、存在问题以及解决的方法--差分和交叉耦合反馈结构,最后给出了E类放大器的实例.由于具有低成本、高集成度、多功用等优点,MOS工艺在射频功率放大方面有很大的发展潜力.在本文中,用0.6 u m CMOS工艺实现了E类放大器的设计.     

中波广播发射机功放问题处理与发射机维护研究

传统广播发射机存在着功能不足、耗电较大等缺陷,随着科技的发展,数字调幅中波发射机取得了较大的发展,取代了传统广播发射机。但中波广播发射机的功放问题,会影响了广播节目的播出质量。文章围绕中波广播发射机功放问题进行分析,并总结了发射机的维护技巧。     

移动终端射频功放的动态电源管理与控制

本文研究WCDMA移动终端射频功放供电效率问题.分析了射频功放特性和电池放电特性,给出了考虑射频输出功率分布的动态电源管理方案和控制算法,分析结果表明:与常规的电池直接供电方案相比较,按照移动终端在城市的发射功率分布模型,新方案射频功放所需的平均功率降低了3.5倍,可以大大延长手机通话和待机时间.     

Thin-film silicon-on-sapphire LDMOS structures for RF power amplifier applications

This work is addressed to the investigation of the electro-thermal performance of RF-LDMOS transistors integrated in TF-SOI, TF-SOS and thinned TF-SOS substrates by means of numerical simulations. Reported experimental trap density, carrier mobility and capture cross-section values have been used together with sapphire datasheet thermal properties, in order to provide accurate simulation results. It is found that subthreshold characteristics are the same for all the analysed substrates while blocking-state, on-state and power dissipation process depends on the substrate type.     

CMOS RF power amplifier with reconfigurable transformer

A CMOS RF power amplifier that can change the output transformer ratio is presented. The CMOS power amplifier is fully integrated in a 0.13 /spl mu/m process and has a power added efficiency (PAE) of 38% at 2.1 GHz and an output power of 30.7 dBm with 3.0 V supply voltage. The PAE at an output power of 16 dBm was increased by 40% by altering the transformer ratio.     

Design of high-efficiency RF Class-D power amplifier

In this paper, the losses in a Class-D RF switching power amplifier and their frequency dependence are described. The losses analyzed are the switching, conduction, and gate drive losses. A 300 W, 13.56 MHz, Class-D circuit is designed in the traditional manner to illustrate the magnitude of the different types of loss. A circuit using the ZVS equations developed in this paper is designed. An experimental circuit is built using standard IRF540 devices in TO220 packages. That circuit does not meet its performance goals because of the package inductance. A new low inductance half-bridge package is introduced to solve this problem. Techniques for circuit layout and power measurements for RF applications are also presented in the experimental section. A low loss gate drive circuit is also presented using a Class-E circuit to provide the drive power. The experimental results confirm the accuracy of the design equations derived in this paper     

Optimum design of a predistortion RF power amplifier for multicarrier WCDMA applications

This paper provides a design guide for optimum design of an RF power amplifier with a predistortion linearizer. For a two-tone signal, three performance degradation factors, higher order terms, amplitude, and phase mismatches are analyzed quantitatively. The results are implemented to the design of optimized predistortion power amplifier for a WCDMA signal application. For the experiments, a 2.4-GHz class-AB power amplifier is fabricated using an LDMOSFET with a 30-W peak envelope power. A simple third-order predistorter is used to measure the relative phases of the harmonics, as well as to linearize the amplifier. The performance of the optimized predistortion power amplifier is excellent for an IS-95 code-division-multiple-access signal. Finally, a method for reducing the memory effects of the amplifier is devised to get a good cancellation performance for a wide-band signal, and the performance degradation caused by the memory effects is analyzed. For a forward-link four-carrier WCDMA signal, the predistortion power amplifier delivers an adjacent channel leakage ratio of -46 dBc at a 4-W average output power with a cancellation of 13.4 dB.     

Parasitic-aware design and optimization of a CMOS RF power amplifier

Implementation of fully integrated CMOS RF power amplifiers is a challenge owing to the low breakdown voltage of aggressively scaled CMOS transistors and parasitic effects associated with on-chip passive components. To address this problem, a parasitic-aware design and optimization paradigm and novel power amplifier circuit design techniques are proposed. The parasitic-aware synthesis described herein employs a simulated annealing algorithm that includes an adaptive tunneling mechanism and post-optimization sensitivity analysis (i.e., design centering) with respect to process, voltage, and temperature variations. Several design techniques are introduced including a self-biased power-amplifier configuration and a digitally controlled conduction angle topology. The techniques are validated via the design of a fully differential nonlinear three-stage 900-MHz GSM power amplifier integrated in 2 mm/sup 2/ in 250-nm CMOS that outputs 2 W (1.5 W) with 30% (43%) drain efficiency from a single 3.0-V (2.5-V) power supply.     

Analysis of the feedback envelope tracking linear class E power amplifier

Feedback envelope tracking amplifier is one technology to realize linear amplification for nonlinear class E power amplifier. In this paper, the basic architecture and frequency response of the feedback envelope tracking amplifier are analyzed in detail. And the analysis shows that the feedback envelope tracking loop can be implemented to satisfy the system’s specifications of linearity and stability, if the bandwidth and the other design parameters are properly selected. The limited bandwidth and different time delay between the envelope path and the phase path can cause intermodulation distortions which deteriorate the linearity of the feedback envelope tracking amplifier, the model for the intermodulation distortions of the feedback envelope tracking class E power amplifier is analyzed compared to the envelope elimination and restoration transmitter. In order to evaluate the broadband performance of the feedback envelope tracking class E power amplifier, the error vector magnitude (EVM) specification is also analyzed, and the simulation results on EVM for WCDMA signal is given.     

Effects of circuit variations on the class E tuned power amplifier

The operation of the class E tuned power amplifier may be described by a set of equations based on Fourier component analysis. Previous publications have derived an optimum operating mode in which the collector efficiency of an idealized circuit is 100 percent. Since real amplifiers are made from nonideal components and are subject to nonideal loads, it is necessary to determine the effects of deviations from the ideal. The effects of variations in component values and duty cycle are determined from the basic equations. Numerical results of variations in load reactance, shunt capacitance, load resistance, frequency, and duty cycle are presented. The amplifier was found to be quite tolerant of reasonable circuit variations. With proper output filtering, the amplifier can be operated over nearly an octave bandwidth with less than a 5 percent reduction in efficiency.