Performance Analysis of Linear Algebraic Functions Using Reconfigurable Computing

This paper introduces a new mapping of geometrical transformation on the MorphoSys (M1) reconfigurable computing (RC) system. New mapping techniques for some linear algebraic functions are recalled. A new mapping for geometrical transformation operations is introduced and their performance on the M1 system is evaluated. The translation and scaling transformation addressed in this mapping employ some vector–vector and vector–scalar operations [6 and 7]. A performance analysis study of the M1 RC system is also presented to evaluate the efficiency of the algorithm execution. Numerical examples were simulated to validate our results, using the MorphoSys mULATE program, which emulates M1 operations.     

一种可重配置系统的模型

University of California，Irvine设计的MorphoSys M1作为粗粒度可重配置系统中一个比较有代表性的系统，对于很多多媒体应用都获得了很好的加速比，但是它在设计上的一些不足造成运算功能单元没有被充分利用,从而对其整体性能的进一步提升有较大影响．针对MorphoSys M1的不足，结合可重配置系统的研究现状和一些多媒体应用的特点，提出了一种新的可重配置系统的模型．实验数据显示，对于许多多媒体应用和加解密算法，改进后的模型相对于MorphoSys M1至少可以获得16％的加速比．     

EPCglobal C1 Gen2标准中CRC算法的实现

介绍CRC的基本原理和EPCglobal C1 Gen2标准使用的CRC-5算法和CRC-16算法。推导8 bit字节型查找表算法和查找表的产生方法,给出CRC-5和CRC-16的硬件实现原理图和软件实现伪代码。用Gen2标准的Query命令和Select命令测试CRC-5和CRC-16的软件实现方法,结果验证了2种算法的正确性。     

MorphoSys reconfigurable hardware for?cryptography:?the?twofish?case

This paper presents the mapping and performance analysis of the Twofish algorithm on MorphoSys. MorphoSys is a reconfigurable architecture that can provide high performance compared to custom hardware and yet preserves a level of flexibility compared to general-purpose processors. With today’s high demand for secure data transfer mediums including wired and wireless networks, there is a growing demand for real-time implementation of cryptographic algorithms. The choice of the Twofish algorithm, one of the five AES finalists, is because it is computationally intensive algorithm. It requires lookup tables, logical and arithmetic computations that stipulate high flexibility and performance. So it is a perfect algorithm to be mapped in order to evaluate such hardware.     

基于FPGA的CRC编解码算法研究

为抵抗复杂传输环境对通信数据造成的影响,对循环冗余校验码CRC这一通信系统中常用的差错控制技术展开研究,设计一套算法在软硬件层面深入挖掘CRC的潜力。在简介循环冗余校验基本原理的基础上,以国际标准CRC-16为研究对象,分析编码和解码过程,在Quartus II上开发平台,运用Verilog硬件描述语言实现CRC的编码与解码。采用Modelsim软件进行仿真验证,结果表明所设计算法的正确性。算法基于可编程硬件技术实现CRC编码与解码,具有运行速度快、容易迁移的优点。     

流水线配置技术在可重构处理器中的应用

提出一种应用于可重构处理器中的流水线配置技术,能够有效减低配置时间,提高应用程序的执行速度。可重构处理器包括通用处理器和一个粗颗粒度的可重构阵列。可重构阵列将处理应用中占据大量执行时间的循环,这些循环将被分解为不同的行在阵列上以流水线的方式执行。该技术在FPGA验证系统上得到了验证。验证的应用包括H.264基准中的整数离散余弦变换和运动估计。相比传统的可重构处理器PipeRench, MorphoSys以及TI的DSP TMS320DM642有大约3.5倍的性能提升。     

Computational experiences with some transitive closure algorithms

The paper contains results of computational experiences with the following algorithms for finding the transitive closure of a digraph: (i) Warshall's algorithm [17], (ii) Purdom's algorithm [13], (iii) the modification of Yen's algorithm [14], and (iv) the new algorithms for finding the transitive closure [3, 4]. The tested digraphs were generated at random. The enclosed references contain all papers known to the authors concerning transitive closure algorithms.     

Interval type-2 fuzzy membership function generation methods for pattern recognition

Type-2 fuzzy sets (T2 FSs) have been shown to manage uncertainty more effectively than T1 fuzzy sets (T1 FSs) in several areas of engineering [4], [6], [7], [8], [9], [10], [11], [12], [15], [16], [17], [18], [21], [22], [23], [24], [25], [26], [27] and [30]. However, computing with T2 FSs can require undesirably large amount of computations since it involves numerous embedded T2 FSs. To reduce the complexity, interval type-2 fuzzy sets (IT2 FSs) can be used, since the secondary memberships are all equal to one [21]. In this paper, three novel interval type-2 fuzzy membership function (IT2 FMF) generation methods are proposed. The methods are based on heuristics, histograms, and interval type-2 fuzzy C-means. The performance of the methods is evaluated by applying them to back-propagation neural networks (BPNNs). Experimental results for several data sets are given to show the effectiveness of the proposed membership assignments.     

Interactive scheduling for mobile multimedia service in M2M environment

Computational load of motion estimation in advanced video coding (AVC) standard is significantly high and its more true for HDTV sequences. In this paper, video processing algorithm is mapped onto a learning method to improve machine to machine (M2M) architecture, namely, the parallel reconfigurable computing (PRC) architecture, which consists of multiple units, First, we construct a directed acyclic graph (DAG) to represent the video coding algorithms comprising motion estimation. In the future trillions of devices are connected (M2M) together to provide services and that time power management would be a challenge. Computation aware scheme for different machine is reduced by dynamically scheduling usage of multi-core processing environment for video sequence depending up complexity of the video. And different video coding algorithm is selected depending upon the nature of the video. Simulation results show the effectiveness of the proposed method.     

面向可重构系统的eCos拓展

针对可重构系统中任务模型灵活性差、硬件任务重构延时长、FPGA资源利用率低等问题,提出了将应用程序划分为软件任务和混合任务的划分模式,并在eCos的基础上,通过重构控制机制、混合任务管理机制、通信机制三方面的拓展,设计了支持可重构系统的嵌入式操作系统框架eCos4RC。仿真结果表明,eCos4RC实现了对混合任务的有效管理,在兼容eCos多线程机制的同时提高了应用程序执行速度和可重构资源利用率,为可重构计算平台提供了良好的运行环境支持。     

Permutation Routing on Reconfigurable Meshes

In this paper we present efficient algorithms for packet routing on the reconfigurable linear array and the reconfigurable two-dimensional mesh. We introduce algorithms that are efficient in the worst case and algorithms that are better on average. The time bounds presented are better than those achievable on the conventional mesh and previously known algorithms. We present two variants of the reconfigurable mesh. In the first model, M _r , the processors are attached to a reconfigurable bus, the individual edge connections being bidirectional. In the second model, M _mr , the processors are attached to two unidirectional buses. In this paper we present lower bounds and nearly matching upper bounds for packet routing on these two models. As a consequence, we solve two of the open problems mentioned in [9]. Received August 17, 1998; revised November 3, 1999.     

Optimal algorithms for the channel-assignment problem on a reconfigurable array of processors with wider bus networks

The computation model on which the algorithms are developed is the reconfigurable array of processors with wider bus networks (abbreviated to RAPWBN). The main difference between the RAPWBN model and other existing reconfigurable parallel processing systems is that the bus width of each network is bounded within the range [2,[/spl radic/(N)]]. Such a strategy not only saves the silicon area of the chip as well as increases the computational power enormously, but the strategy also allows the execution speed of the proposed algorithms to be tuned by the bus bandwidth. To demonstrate the computational power of the RAPWBN, the channel-assignment problem is derived in this paper. For the channel-assignment problem with N pairs of components, we first design an O(T + [N//spl omega/]) time parallel algorithm using 2N processors with a 2N-row by 2N-column bus network, where the bus width of each bus network is /spl omega/-bit for 2 /spl les/ /spl omega/ /spl les/ [/spl radic/N] and T = [log/sub /spl omega//N] + 1. By tuning the bus bandwidth to the natural log N-bit and the extended N/sup 1/c/-bit (N/sup 1/c/ > log N) for any constant c and c /spl ges/ 1, two more results which run in O(log N/log log N) and O(1) time, respectively, are also derived. When compared to the algorithms proposed by Olariu et al. [17] and Lin [14], it is shown that our algorithm runs in the equivalent time complexity while significantly reducing the number of processors to O(N).     

Prufer编解码的最优算法

讨论标号树的Prufer编码的编解码算法.文献中常见的Prufer编解码算法需要O(n log n)时间.文献[1,2,4,9]提出了Prufer编解码的线性时间算法.这些算法都用到了整数排序算法,利用待排序整数的取值特殊性,得到线性时间整数排序算法.由此将Prufer编解码问题的计算归结为整数排序问题.本文从更直接的角度考察Prufer编解码问题,从简单算法出发,挖掘问题的本质特征,逐步简化,得到Prufer编码的一个非常简单实用的线性时间最优编解码算法.本文采用的解决问题的方法也具有一定的技巧,可供解决类似问题时借鉴.     

Stochastic adaptive control and prediction based on a modified least squares--The general delay-colored noise case

In [1], global convergence for a stochastic adaptive control based on modified least-squares algorithms has been established. However, the proof of Lemma 3.4 in [1] is questionable. A similar question existed in the proof ofdelta(t - d) rightarrow 0in [2]. Without using this conclusion, the present note attempts to establish global convergence for a discrete-time stochastic adaptive control and prediction based on slightly modified least-squares algorithms for linear time-invariant discrete-time systems having general delay and colored noise.     

On the Moser- and super-reduction algorithms of systems of linear differential equations and their complexity

The notion of irreducible forms of systems of linear differential equations with formal power series coefficients as defined by Moser [Moser, J., 1960. The order of a singularity in Fuchs’ theory. Math. Z. 379–398] and its generalisation, the super-irreducible forms introduced in Hilali and Wazner [Hilali, A., Wazner, A., 1987. Formes super-irréductibles des systèmes différentiels linéaires. Numer. Math. 50, 429–449], are important concepts in the context of the symbolic resolution of systems of linear differential equations [Barkatou, M., 1997. An algorithm to compute the exponential part of a formal fundamental matrix solution of a linear differential system. Journal of App. Alg. in Eng. Comm. and Comp. 8 (1), 1–23; Pflügel, E., 1998. Résolution symbolique des systèmes différentiels linéaires. Ph.D. Thesis, LMC-IMAG; Pflügel, E., 2000. Effective formal reduction of linear differential systems. Appl. Alg. Eng. Comm. Comp., 10 (2) 153–187]. In this paper, we reduce the task of computing a super-irreducible form to that of computing one or several Moser-irreducible forms, using a block-reduction algorithm. This algorithm works on the system directly without converting it to more general types of systems as needed in our previous paper [Barkatou, M., Pflügel, E., 2007. Computing super-irreducible forms of systems of linear differential equations via Moser-reduction: A new approach. In: Proceedings of ISSAC’07. ACM Press, Waterloo, Canada, pp. 1–8]. We perform a cost analysis of our algorithm in order to give the complexity of the super-reduction in terms of the dimension and the Poincaré-rank of the input system. We compare our method with previous algorithms and show that, for systems of big size, the direct block-reduction method is more efficient.     

声码器中一种四级可重构ALU的研究与设计

在面向语音编解码算法实现的高性能声码器设计中,支持可变长VLIW指令集的ALU单元是实现其设计目标的重要环节.本文提出一种四级可重构的ALU设计,以前缀算法加法器为核心,并通过操作数和资源的重构,能在单周期内完成81种复合算术逻辑运算,同时将其控制编码压缩了58.93%以适应指令集的宽度约束,高效实现了算法中潜在的高并行性,很好的满足了运算密集型的算法应用需求.     

An optimal and processor efficient parallel sorting algorithm on a linear array with a reconfigurable pipelined bus system

Optical interconnections attract many engineers and scientists’ attention due to their potential for gigahertz transfer rates and concurrent access to the bus in a pipelined fashion. These unique characteristics of optical interconnections give us the opportunity to reconsider traditional algorithms designed for ideal parallel computing models, such as PRAMs. Since the PRAM model is far from practice, not all algorithms designed on this model can be implemented on a realistic parallel computing system. From this point of view, we study Cole’s pipelined merge sort [Cole R. Parallel merge sort. SIAM J Comput 1988;14:770–85] on the CREW PRAM and extend it in an innovative way to an optical interconnection model, the LARPBS (Linear Array with Reconfigurable Pipelined Bus System) model [Pan Y, Li K. Linear array with a reconfigurable pipelined bus system—concepts and applications. J Inform Sci 1998;106;237–58]. Although Cole’s algorithm is optimal, communication details have not been provided due to the fact that it is designed for a PRAM. We close this gap in our sorting algorithm on the LARPBS model and obtain an O(log N)-time optimal sorting algorithm using O(N) processors. This is a substantial improvement over the previous best sorting algorithm on the LARPBS model that runs in O(log N log log N) worst-case time using N processors [Datta A, Soundaralakshmi S, Owens R. Fast sorting algorithms on a linear array with a reconfigurable pipelined bus system. IEEE Trans Parallel Distribut Syst 2002;13(3):212–22]. Our solution allows efficiently assign and reuse processors. We also discover two new properties of Cole’s sorting algorithm that are presented as lemmas in this paper.     

WLAN安全分析与解决方法

IEEE802.11协议在MAC层引入基于WEP算法的安全机制,WEP通过在RC4密码系统中采用CRC-32循环冗余校验的方式实现完整性验证。该文先分析了这种机制的若干缺点,然后重点介绍了802.11i和WAPI,说明后两者是如何弥补上述机制不足之处的。     

几何外形特性描述的角度编码方法

本文分析外形曲线的几何性质及数字特征的角度编码描述及其解析计算.文中给出了 何外形曲线的周长;方向宽度;封闭曲线所围成的区域面积、矩及距离的解析计算公式;证 明了曲线封闭的充分必要条件;阐明了角点特征的检测方法;讨论了将二维形状分析转化为 波形分析的角度编码方法.从而给出了一系列与Freeman方向编码理论相平行的理论结 果[3-6].这些结果对于计算机视觉系统实施形状分析具有应用价值.     

Computer simulation of heuristic reinforcement-learning systems for nuclear power plant load changes control

This paper describes two ideas and sample simulation results of a heuristic reinforcement-learning system and its application to the problem of digital computer control of a simple nuclear plant model. The idea of the system is interconnection between the well known reactor control heuristic rules [8,9], and the reinforcement learning algorithms [4,5]. The control signal is proposed as a vector depending on complex physical properties of the plant. Such an approach is far more flexible than deterministic or stochastic techniques when dealing with unknown processes and novel control situations.