一种改进的集成电路模块有效布局算法

改进了一种求解集成电路模块布局问题的启发式算法。以边界矩形周长最小为目标,设计了模块的优先序列,并在布局过程中动态调整,重新设计布局优先度,并简化模块的占边动作,重写占角动作,对模块布局放置的多个可能位置进行比较,并将其放置在优先度最高的适当区域。经实例测试,结果表明该算法简洁高效,面积利用率有较大提高。     

An augmented Lagrangian method for VLSI global placement

By ignoring some cell overlaps, global placement computes the best position for each cell to minimize the wirelength. It is an important stage in very large scale integration (VLSI) physical design, since circuit performance heavily depends on the placement results. In this paper, we propose an augmented Lagrangian method to solve the VLSI global placement problem. In the proposed method, a cautious dynamic density weight strategy is used to balance the wirelength objective and the density constraints, and an adaptive step size is used to obtain a trade-off between runtime and solution quality. The proposed method is tested on the IBM mixed-size benchmarks and the International Symposium on Physical Design 2006 placement contest benchmarks. Experimental results show that our global placement method outperforms the state-of-the-art placement approaches in terms of solution quality on most of the benchmarks.     

双阈值VLSI低测试功耗方法研究*

提出一种测试功耗优化的新方法,它通过阈值门电路调节和漏电流优化两种方法相结合来降低静态功耗。通过算法寻找电路的关键路径,去除伪路径,然后在关键电路上设置低阈值门电路,在非关键电路上设置高阈值门电路（不违反时序约束的前提下）,利用测试向量的无关位特性来调整测试向量和测试架构,达到降低漏电流的目的。通过以上两种途径,整体上达到功耗优化的结果,实验结果证实了本方法的有效性。     

CNB: A critical-network-based timing optimization method for standard cell global routing

A novel method, named critical-network-based (CNB),for timing optimization in global routing is presented in this paper.The essence of this method is different from that of the typical existing ones,named nets-based (NB) and critical-path-based (CPB).The main contribution of this paper is that the CNB delay reduction method is more efficient than the typical existing ones.This new method makes it possible to reduce the delay in an overall survey.Based on CNB,a timing optimization algorithm for global routing is implemented and tested on Microelectronics Center of North Carolina (MCNC) benchmarks in this paper.The experimental results axe compared between this algorithm and the existing ones.The experimental results show that this algorithm is able to control the delay efficiently.     

The evolution of standard cell libraries for future technology nodes

Evolvable Hardware has been a discipline for over 15 years. Its application has ranged from simple circuit design to antenna design. However, research in the field has often been criticised for not addressing real world problems. Intrinsic variability has been recognised as one of the major challenges facing the semiconductor industry. This paper describes an approach that optimises designs within a standard cell library by altering the transistor dimensions. The proposed approach uses a Multi-objective Genetic Algorithm to optimise the device widths within a standard cell. The designs are analysed using statistically enhanced transistor models (based on 3D-atomistic simulations) and statistical Spice simulations. The goal is to extract high-speed and low-power designs, which are more tolerant to the random fluctuations present in current and future technology nodes. The results show improvements in both the speed and power of the optimised standard cells and that the impact of threshold voltage variation is reduced.     

VLSI architecture for low latency radix-4 CORDIC

The CORDIC algorithm, originally proposed using nonredundant radix-2 arithmetic, has been refined in terms of throughput and latency with the introduction of redundant arithmetic and higher radix techniques. In this paper, we propose a pipelined architecture using signed digit arithmetic for the VLSI efficient implementation of rotational radix-4 CORDIC algorithm, eliminating z path completely. A detailed comparison of the proposed architecture with the available radix-2 architectures shows the latency and hardware improvement. The proposed architecture achieves latency improvement over the previously proposed radix-4 architecture with a relatively small hardware overhead. The proposed architecture for 16-bit precision was implemented using VHDL and extensive simulations have been performed to validate the results. The functionally simulated net list has been synthesized for 16-bit precision with 90 nm CMOS technology library and the area-time measures are provided. This architecture was also implemented using Xilinx ISE9.1 software and a Virtex device.     

VLSI标准单元布局问题的增强型混合遗传模拟退火算法

提出有效处理百万个VLSI标准单元布局问题的混合遗传模拟退火算法.首先采用小规模种群、动态更新种群和交叉局部化策略,并协调全局与局部搜索,使遗传算法可处理超大规模标准单元布局问题.然后为进一步提高算法进化效率和布局结果质量,将爬山和模拟退火方法引入遗传算法框架及其算子内部流程,设计高效的线网-循环交叉算子和局部搜索算法.标准单元阵列布局侧重使用爬山法,非阵列布局侧重使用模拟退火方法.Peko suite3、Peko suite4和ISPD04标准测试电路的实验结果表明,该算法可在合理运行时间内有效提高布局结果质量.     

Databases and cell-selection algorithms for VLSI cell libraries

The issues that must be addressed before commercial database management systems can be used to manage VLSI CAD data are defined. A survey is presented of approaches addressing four of the defined issues: design hierarchies and multilevel representations, design alternatives and version control, common interface between cell libraries and efficient cell selection based on given design constraints. A frame-based model is considered as a case study of the special-purpose design database management system approach. This framework for capturing design data is based on semantic networks. It is well suited for application-specific ICs, yet general enough for other CAD/CAM environments. Benchmark results for the selection algorithms that run on top of the frame-based database system are presented     

一种用于FPGA布局的模拟退火算法

在本篇论文中,我们介绍了在标准对称阵列(隔离岛状)现场可编程逻辑阵列结构下的一种有效的布局方法,模拟退火算法。实验结果显示,相比普通的布局算法,模拟退火算法在布局时间上减少了20%。     

Certain investigations in achieving low power dissipation for SRAM cell

The modern semiconductor industry is evolving quite rapidly. Portable and mobile devices are becoming smaller every day and there is also a growing demand for longer battery power. With these demands it is important for researchers to focus on the leakage power in stand-by mode. The SRAM was designed to accurately communicate with CPU, DSP, processor and low-power applications, such as battery-life handheld devices. For some days now, the design engineer focuses mainly on the production of large-capacity memories, high bandwidth and low energy consuming memories. Memory is an integral part of most of these systems and is also diminished as the scale of the system reduces. Low power and processing architecture at high speed is therefore a major concern. The durability of random static access memory cells (SRAM) is another critical factor. This Paper Describes the SRAM architecture designed for the reduction of power consumption or power leakages using sleep transistor and MTCMOS (Multi-Threshold Complementary Metal Oxide Semiconductor) techniques. This helps in the reduction of the CMOS transistor leakages. This paper incorporates multiple threshold strategies to give the proposed high speed, increased reliability and low leakage current of the updated 8T SRAM cell in stand-by memory cell mode. Based on the parameters like power dissipation at a different temperature, read voltage, write voltage, read delay, write delay, compared to the previously designed SRAM architecture of 6T, 7T, 8T and 13T we get low power consumption in our designed 8T SRAM architecture. The simulations are conducted with the UMC 55 nm technology Cadence Virtuoso method.     

基于GA-SA混合算法的VLSI门阵列布局设计

布局是VLSI布图设计中的关键环节，通常采用随机优化算法。该文采用遗传算法(GA)与模拟退火法(SA)相结合的搜索算法实现VLSI门阵列模式布局，利用遗传算法进行全局搜索，模拟退火法进行局部搜索。进化过程中采用精英保留策略，并对进化结果进行有选择的模拟退火操作，这样既加强了局部搜索能力又防止陷入局部最优。在复合布局目标函数中引入对最长线网的惩罚，其收敛速度比以总线长度为单一目标函数的要快。在交叉操作中，对交叉位置的选择采用了一种新的策略，增加了交叉的有效性。实验表明，此算法与简单遗传算法相比，有效地提高了全局搜索能力。     

JPEG2000中二维小波变换的高速VLSI设计与实现

提出了一种基于9/7小波的二维小波变换器的硬件设计方案.通过优化算法以及采用行列变换并行处理的方式,提高了变换器的数据吞吐量.该方案采用了流水线技术,较大地提高了硬件效率.综合结果表明,该方案的系统时钟可达到110 MHz,且具有高速、高吞吐量、片内存储器小等优点.     

一种改进的VLSI电路有效布局算法

采用重心矩形约束[1]进行VLSI布局会出现以下问题：(1)布局边界的浪费,出现不可利用的小区域;(2)放置模块时可能会出现模块放置在实际有效区域内却因为重心约束成为非法放置。为了解决该问题,本文提出了一种改进文献[1]的VLSI布局启发式算法：通过设计模块的优先顺序进行合理布局,并辅助于边界矩形来解决重心矩形约束出现的问题;对模块布局放置的多个可能位置进行比较,并将其放置在优先度最高的适当区域。用Banchmark（ami33,ami49）和文献[1]的数据进行测试,结果表明新算法：（1）算法简洁高效,运行时间短;（2）布局结果明显好于文献[1]。     

基于低阈值单元的高性能低功耗设计方法

在高性能IC设计中对高低两种阈值电压技术进行比较,利用低阈值电压降低动态功耗的手段实现降低总功耗的目标,并分析出了两种阈值电压低功耗设计各自适应的电路类型。首先对40nm工艺中标准单元的内部功耗、时序、尺寸进行分析。接着在相同延时下对高阈值和低阈值两种标准单元所设计的反相器链时序电路的功耗进行对比分析。最后基于Benchmark和AES两种类型电路,分别采用高阈值和低阈值进行综合,对比得出在相同时钟周期下更低功耗的设计所对应的阈值电压设计方式。结果显示,在相同的时钟频率下,对动态功耗占据总功耗比例极大的电路使用低阈值设计得到的功耗更低。同样,在动态功耗比例不是极大的电路中,当低阈值综合的slack为正时,以及当高阈值综合的slack为负、低阈值的slack为0时,用低阈值设计功耗更低;而当高阈值、低阈值综合的slack都为0时,用高阈值设计功耗更低。     

Lateral phase change random access memory cell design for low power operation

In this paper, we present a novel lateral cell design for phase change random access memory (PCRAM) that features an improved thermal management to efficiently reduce the current consumption during reset operation. Simulation, fabrication and electrical characterization results of the lateral concept are presented.     

A low loss and power efficient micro-electro-thermally actuated RF MEMS switch for low power and low loss applications

Microsystem Technologies - A novel laterally and micro-electro-thermally actuated RF MEMS switch is presented in this paper. Despite many RF MEMS switches requiring continuous actuation voltage to...     

Clock and power gating with timing closure

Assuming that delay is linearly dependent on local power supply voltage, the authors show how to set up an analysis to determine the effect of power supply variations on delay. This analysis can drive the introduction of clock gating, an increasingly popular technique for reducing dynamic power dissipation.     

A novel architecture design for VLSI implementation of integer DCT in HEVC standard

This paper presents novel hardware of a unified architecture to compute the 4?×?4, 8?×?8, 16?×?16 and 32?×?32 efficient two dimensional (2-D) integer DCT using one block 1-D DCT for the HEVC standard with less complexity and material design. As HEVC large transforms suffer from the huge number of computations especially multiplications, this paper presents a proposition of a modified algorithm reducing the computational complexity. The goal is to ensure the maximum circuit reuse during the computation while keeping the same quality of encoded videos. The hardware architecture is described in VHDL language and synthesized on Altera FPGA. The hardware architecture throughput reaches a processing rate up to 52 million of pixels per second at 90 MHz frequency clock. An IP core is presented using the embedded video system on a programmable chip (SoPC) for implementation and validation of the proposed design. Finally, the proposed architecture has significant advantages in terms of hardware cost and improved performance compared to related work existing in the literature. This architecture can be used in ultra-high definition real-time TV coding (UHD) applications.

     

低功耗并行的二维离散小波变换的VLSI结构

提出了一种基于提升算法的低功耗并行的二维离散小波变换的VLSI结构。提出结构的同时进行行和列方向的处理,不需要额外的缓存来存储用于列变换的中间变换系数。通过分时复用关键的运算功能模块,该结构同时可以对两行数据进行处理,硬件的利用率达到100%。边界对称扩展通过嵌入式电路实现,大大降低了需要的片上存储器的数量以及对片外存储器的访问,有效地降低了系统的功耗。