基于数字多用表自动检定校准系统的研究

由于数字多用表型号众多、量程宽、每一个量程及校准点的技术指标各不相同,造成校准过程耗时长,数据处理繁琐等问题.为了降低数字多用表校准过程中人为失误几率,同时提高数字多用表校准工作的效率.本文设计开发出了性能稳定、实用性强的数字多用表自动校准系统.     

数字多用表自动校准系统的分析与设计

由于数字多用表型号众多、量程宽、每一个量程及校准点的技术指标各不相同,造成校准过程耗时长,数据处理繁琐等问题.为了减少数字多用表校准过程中出现的失误几率,有效提高校准数字多用表的工作效率及质量.本文分别从数字多用表自动校准系统的主体结构、硬件架构和软件设计等多方面进行论述,设计开发出性能稳定、实用性强的数字多用表自动校准系统.     

数字多用表自动化校准系统

仪器计量校准是恢复、保持设备性能指标,保证测量准确可靠的技术手段,所以需要在国家授权的计量校准机构定期的进行校准.但是随着计算机技术、大规模集成电路技术和通信技术的飞速发展,仪器技术领域发生了巨大的变化,从最初的模拟仪器发展到现在的数字化仪器、嵌入式仪器和智能仪器.     

数字多用表校准系统设计研究

数字多用表作为一种计量器材,多用于电学行业之中,数学多用表计量能力的高低也会直接影响到生产活动的运行,是确保电学行业勘测能力的重要构成。但是受其型号种类繁多、技术参数不同和量程宽等多种因素影响,校准过程时间长、数据处理缓慢等问题也时常出现。为了降低使用数字多用表时的失误率,提升工作效率,设计出数字多用表校准系统是十分必要的。     

数字多用表远程校准系统的设计与开发

数字多用表种类繁多,不同表的校准量程、校准档位、及技术参数选取不一样,人工手动校准时间较长,且存在人为失误风险。目前市场上鲜有对数字多用表进行自动校准的专用软件,本文主要研究数字多用表的远程校准技术,开发自动校准程序。通过远程加载校准程序实现对不同表进行自动校准,通过远程桌面控制技术来实现远程校准操作,从而提高了数字多用表的校准效率和校准可靠性。     

用5520A建立数字多用表校准装置测量不确定度评定

该文对应用5520A建立六位半及以下数字多用表计量校准装置的测量不确定度评定进行了详细分析;对测量原理、测量方法、数学模型、方差及传播系数、不确定度来源也作了描述;可以作为撰写数字多用表计量标准技术报告的参考资料.     

精密运算放大器自动校零

本文简述了最新的精密运放的数字修理工调技术。     

基于CVI的数字示波器自动校准系统设计

以LabWindows/CVI为软件平台,利用VISA和SCPI命令开发完成数字示波器自动校准系统。该系统可快速完成基于GPIB,RS232,LAN接口的数字示波器的自动化校准,保存测试数据,并自动判定测试结果,同时通过ActiveX技术实现Microsoft Word校准证书的自动生成、打印和保存。系统可消除人工手动操作引入的误差,具有长时间工作的稳定性,保证了计量工作的一致性。该系统具有易扩展性,只需通过添加对应型号示波器的控制文件就可以支持新的数字示波器。     

一种新型子母型数字多用表的研制

介绍一种新型的子母型数字多用表,该多用表在保留原有测量功能的前提下,增加了远程监视功能,此功能借助先进的跳频技术将母机测量的数据发送给子机,以达到测量值在母机和子机的液晶屏上同时显示的目的,从而满足高空、狭小等特殊作业环境使用.该表采用低功耗的PIC单片机作为处理器,以节约能耗,增加电池寿命.     

Resistance - something behind automated calibration

It is not controversial to say that automation will increase the efficiency of any process, compared with the current performance. In many automation projects, however, one important issue has been overlooked: resistance. This resistance is not electrical resistance governed by Ohm's law. It is resistance to change by personnel when automation or technology changes are suggested. This is a common sociotechnical barrier during the course of phasing in new technology. This article is about an unsuccessful attempt to automate calibration processes for electronic measuring devices in a well-established instrumentation laboratory and suggestions on how to address the sociotechnical problem that was encountered. After reading this article, the author will recognize that the introduction of new, very helpful technology may not be successful because of human (sociotechnical) factors.     

Mobile digital communications via tone calibration

A new digital signaling technique that is particularly suited for channels impaired by multipath fading is presented. The proposed modulation scheme employs a continuous-wave (CW) tone to calibrate the mobile channel against the multipath-induced phase uncertainties. This technique is applicable to quaternary phase shift keying as well as to more complicated signal constellations such as M-ary phase shift keyed schemes. The advantages of tone calibration are: 1) robustness of the receiver and 2) elimination of the link dependent error floor. Furthermore, since the CW tone can also be used for coherent signal demodulation, carrier phase acquisition can be achieved within a bit time. This property is particularly attractive when a burst of data with a short burst length has to be detected. This radio technique is useful for both the terrestrial mobile and the newer satellite-aided mobile communication (SAMC) services.     

Online calibration of MOSFET on-state resistance for precise current sensing

An approach for online current sensing calibration is presented where an auxiliary switch and a precision sense resistor are connected in parallel with a main power switch to achieve accuracy comparable to the sense resistor method, together with the advantage of essentially no additional power loss. The proposed current-sensing circuit and the calibration methods are particularly well suited for digital controller implementations where the required control and calibration functions can be easily accomplished. Experimental results with a digitally controlled 1.5-V 15-A synchronous buck converter demonstrate functionality of the online calibration approach, showing a significant improvement in accuracy over voltage sensing across the power MOSFET on-resistance.     

Offset-injection digital background calibration for VCO-based ADC

A new offset-injection digital background calibration technique for VCO-based ADC is proposed to compensate for VCO nonlinearity. By injecting a predetermined offset signal, the new technique suppresses in-band distortions caused by VCO nonlinearity successfully. The offset-injection technique draws support from orthogonal polynomials least mean square algorithm to improve the computation efficiency. A dual-path all-standard-cell VCO-based ADC is also proposed to inject the calibration signal. The proposed VCO-based ADC achieves 71.9 dB of signal to noise and distortion ratio and 11.65 bits of effective number of bit.     

A precise digital phase shifter using a phase-locked loop

A phase-locked loop containing a voltage-controlled oscillator (v.c.o.) synchronised to a harmonic of its fundamental output frequency may be used to form an attractive digital phase shifter providing low phase error with relatively simple circuitry and control requirements. Phase increments of 2?/n radians are obtained, where n is the order of harmonic used.     

基于数字天顶仪的时间标定方法

为了获得高精度的时间信息,常采用GPS等授时系统进行授时,但在野外等复杂环境下往往接收不到GPS等授时信息。数字天顶仪是一种高精度的天文定位仪器,采用数字天顶仪进行时间标定的研究相对较少。考虑到数字天顶仪的定位结果受恒星视位置和时间的影响,首先分别研究了时间误差及星表精度对恒星视位置的影响,然后分析了恒星视位置对数字天顶仪定位精度的影响。基于数字天顶仪的定位原理提出了一种时间标定的新方法,并得出时间标定的精度在0.025 s。实验数据的分析结果表明该时间标定的方法是可行的。     

下行波束形成系统的校正算法及FPGA实现

校正系统对于解决数字波束形成天线实现过程中的通道幅相失配等问题具有非常重要的意义.根据一种基于并行正交码的校正算法,采用并行化设计方法,结合先进的FPGA器件,设计了一个下行波束形成天线阵列的校正系统,并给出了该校正系统运行速度和校正效果的分析,证明了该校正系统能完全满足下行波束形成中实时校正的需求.     

精密测角法中测量误差对内方位元素标定的影响

通过误差传递推导误差公式,确定了各参数对内方位元素精度的影响关系.为了明确对相机内方位元素精度的影响因素,对像点位置坐标精度和物方视场角精度与相机内方位元素精度的关系进行研究.在现有的精密测角法的基础上,推导关系公式来确定各参数对内方位元素精度的影响关系.对采样点各个数据的精度及其组数对结果精度的影响进行讨论.结果表明:在像点位置坐标标准差1μm内,物方视场角极限误差0.7"内,位置坐标精度对主距f精度影响较大,而物方视场角精度对主点x0精度影响较大;测量数组数(采样点数)量对结果误差有很大的影响.实验证明:该影响与实际结果相符.     

A digital background calibration technique for time-interleavedanalog-to-digital converters

A 10-bit 40-Msample/s two-channel parallel pipelined ADC with monolithic digital background calibration has been designed and fabricated in a 1 μm CMOS technology. Adaptive signal processing and extra resolution in each channel are used to carry out digital background calibration. Test results show that the ADC achieves a signal-to-noise-and-distortion ratio of 55 dB for a 0.8-MHz sinusoidal input, a peak integral nonlinearity of 0.34 LSB, and a peak differential nonlinearity of 0.14 LSB, both at a 10-bit level. The active area is 42 mm², and the power dissipation is 565 mW from a 5 V supply     

Split-ADC based digital background calibration for time-interleaved ADC

A novel Time-Interleaved Analog-to-Digital Converter (TIADC) digital background calibration for the mismatches of offsets, gain errors, and timing skews based on split-ADC is proposed. Firstly, the split-ADC channels in present TIADC architecture are designed to convert input signal at two different channel sampling rates so that redundant channel to facilitate pair permutation is avoided. Secondly, a high-order compensation scheme for correction of timing skew error is employed for effective calibration to preserve high-resolution when input frequency is high. Numerical simulation performed by MATLAB for a 14-bit TIADC based on 7 split-ADC channels shows that Signal-to-Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFD) of the TIADC achieve 86.2 dBc and 106 dBc respectively after calibration with normalized input frequency near Nyquist frequency.