Electrical behavior of p-type PbS-based metal-oxide-semiconductor thin film transistors

Chemically deposited lead sulfide (PbS) thin films were used as the semiconductor active layer in common-gated thin film transistors. The PbS films were deposited at room temperature on SiO₂/Si-p wafers. Lift-off was used to define source and drain contacts (gold, Au) on top of the PbS layer with channel lengths ranging from 10 to 80 μm. The Si-p wafer with a back chromium-gold contact served as the common gate for the transistors. Experimental results show that as-deposited PbS are p-type in character and the devices exhibit typical drain current versus source-drain voltage (I_DS-V_DS) behavior as a function of gate voltage. The values of threshold voltage of the devices were in the range from −7.8 to 1.0 V, depending on the channel length. Channel mobility was approximately 10^− 4 cm²V^− 1 s^− 1. The low channel mobility in the devices is attributed to the influence of the microstructure of the nanocrystalline thin films. The electrical performance of the PbS-based devices was improved by thermal annealing the devices in forming gas at 250 °C. In particular, channel mobility increased and threshold voltage decreased as a consequence of the thermal annealing.     

Effect of thickness of ZnO active layer on ZnO-TFT's characteristics

We have investigated the electrical characteristics of ZnO thin film transistors with respect to the thickness of ZnO active layers. The ZnO layers with the thickness of 30 nm to 150 nm were deposited on bottom gate patterned Si substrate by RF sputtering at room temperature. The low-temperature oxide served as gate dielectric. As ZnO channel layer got thicker, the leakage current at V_DS = 30 V and V_G = 0 V greatly increased from 10^− 10 A to 10^− 6 A, while the threshold voltage decreased from 15 V to 10 V. On the other hand, the field effect mobility got around 0.15 cm²/V s except for the 30-nm-thick channel. Overall, the 55-nm-thick ZnO channel layer showed the best performance.     

Copper phthalocyanine thin-film field-effect transistor with SiO2/Ta2O5/SiO2 multilayer insulator

Top-contact Copper phthalocyanine (CuPc) thin-film field-effect transistor (TFT) with SiO₂/Ta₂O₅/SiO₂ (STS) multilayer as the dielectric was fabricated and investigated. With the multi-layer dielectric, drive voltage was remarkably reduced. A relatively large on-current of 1.1 × 10⁻⁷ A at a V_GS of −15 V was obtained due to the strong coupling capability provided by the STS multilayer gate insulator. The device shows a moderate performance: saturation mobility of μ_sat = 6.12 × 10⁻⁴ cm²/V s, on-current to off-current ratio of I_on/I_off = 1.1 × 10³, threshold voltage of V_TH = −3.2 V and sub-threshold swing SS = 1.6 V/dec. Atomic force microscope images show that the STS multilayer has a relative smooth surface. Experiment results indicate that STS multilayer is a promising insulator for the low drive voltage CuPc-based TFTs.     

Annealing effect on dielectric and leakage current characteristics of Mn-doped Ba0.6Sr0.4TiO3 thin films as gate insulators for low voltage ZnO thin film transistor

We report on the dielectric properties and leakage current characteristics of 3 mol% Mn-doped Ba_0.6Sr_0.4TiO₃ (BST) thin films post-annealed up to 600 °C following room temperature deposition. The suitability of 3 mol% Mn-doped BST films as gate insulators for low voltage ZnO thin film transistors (TFTs) is investigated. The dielectric constant of 3 mol% Mn-doped BST films increased from 24 at in-situ deposition up to 260 at an annealing temperature of 600 °C due to increased crystallinity and the formation of perovskite phase. The measured leakage current density of 3 mol% Mn-doped BST films remained on the order of 5 × 10^− 9 to 10^− 8 A/cm² without further reduction as the annealing temperature increased, thereby demonstrating significant improvement in the leakage current characteristics of in-situ grown Mn-doped BST films as compared to that (5 × 10^− 4 A/cm² at 5 V) of pure BST films. All room temperature processed ZnO-TFTs using a 3 mol% Mn-doped BST gate insulator exhibited a field effect mobility of 1.0 cm²/Vs and low voltage device performance of less than 7 V.     

Ammonia-free chemically deposited CdS films as active layers in thin film transistors

In this work we have grown CdS thin films using an ammonia-free chemical bath deposition process for the active layer in thin film transistors. The CdS films were deposited substituting sodium citrate for ammonia as the complexing agent. The electrical characterization of the as-deposited CdS-based thin film transistors shows that the field effect mobility and threshold voltage were in the range of 0.12-0.16 cm²V⁻¹ s⁻¹ and 8.8-25 V, respectively, depending on the channel length. The device performance was improved considerably after thermal annealing in forming gas at 250 °C for 1 h. The mobility of the annealed devices increased to 4.8-8.8 cm²V⁻¹ s⁻¹ and the threshold voltage decreased to 8.4-12 V. I_on/I_off for the annealed devices was approximately 10⁵-10⁶.     

Fabrication of n-type Schottky barrier thin-film transistor with channel length and width of 0.1 μm and erbium silicide source/drain

In this paper, a Schottky barrier polycrystalline silicon thin-film transistor (SB TFT) with erbium silicide source/drain is demonstrated using low temperature processes. A low temperature oxide is used for a gate dielectric and the transistor channel is crystallized by a metal-induced lateral crystallization process. An n-type SB TFT shows a normal electrical performance with subthreshold slope of 239 mV/dec, I_ON/I_OFF ratio of 5.8 × 10⁴ and I_ON of 2 μA/µm at V_G = 3 V, V_D = 2.5 V for 0.1 μm device. A process temperature is maintained at less than 600 °C throughout the whole processes. The SB TFT is expected to be a promising candidate for a next system-on-glass technology and an alternative 3D integration technology.     

Influence of process steps on the performance of microcrystalline silicon thin film transistors

Bottom gate microcrystalline silicon thin film transistors (μc-Si TFT) have been realized with two types of films: μc-Si(1) and μc-Si(2) with crystalline fraction of 80% and close to 100% respectively. On these TFTs we applied two types of passivation (SiN_x and resist). μc-Si TFTs with resist as a passivation layer present a low leakage current of about 2.10^− 12 A for V_G = − 10 and V_D = 0.1V an ON to OFF current ratio of 10⁶, a threshold voltage of 7 V, a linear mobility of 0.1 cm²/V s, and a sub-threshold voltage of 0.9 V/dec. Microcrystalline silicon TFTs with SiN_x as a passivation present a new phenomenon: a parasitic current for negative gate voltage (− 15 V) causes a bump and changes the shape of the sub-threshold region. This excess current can be explained by and oxygen contamination at the back interface.     

Temperature dependent microwave performance of AlGaN/GaN high-electron-mobility transistors on high-resistivity silicon substrate

The influence of temperature (− 50 °C to + 200 °C) was studied on the DC and microwave characteristics of AlGaN/GaN high-electron-mobility transistors (HEMTs) on high resistivity Si substrate for the first time. The AlGaN/GaN HEMTs exhibited a current-gain cut-off frequency (f_T) of 11.8 GHz and maximum frequency of oscillation (f_max) of 27.5 GHz. When compared to room temperature values, about 4% and 10% increase in f_T and f_max and 23% and 39.5% decrease in f_T and f_max were observed when measured at − 50 °C and 200 °C, respectively. The improvement of I_D, g_mf_T, and f_max at − 50 °C is due to the enhancement of 2DEG mobility and effective electron velocity. The anomalous drain current reduction in the I-V curves were observed at low voltage region at the temperature ≤ 10 °C but disappeared when the temperature reached ≥ 25 °C. A positive threshold voltage (V_th) shift was observed from − 50 °C to 200 °C. The positive shift of V_th is due to the occurrence of trapping effects in the devices. The drain leakage current decreases with activation energies of 0.028 eV and 0.068 eV. This decrease of leakage current with the increase of temperature is due to the shallow acceptor initiated impact ionization.     

Instability of threshold voltage under constant bias stress in pentacene thin film transistors employing polyvinylphenol gate dielectric

The instability of threshold voltage and mobility of pentacene thin film transistors using a poly(4-vinylphenol) gate dielectric have been investigated under constant bias stress. The mobility was very stable in vacuum by exhibiting 2% variation after 6 h stress even under the high gate bias stress of V_GS = − 20 V. Meanwhile, we observe a negative shift of threshold voltage under stress in vacuum. This shift is attributed to charges trapped in deep electronic states in pentacene near the gate interface. We propose a model for the negative shift of the threshold voltage and extract the hole concentration, 4.5 × 10¹¹ cm^− 2, needed to avoid the onset of stress effects, resulting in a design rule of the channel width to length ratio larger than 40.     

Demonstration of logic AND device using a split-gate pentacene field effect transistor

We report on the fabrication and performance of pentacene-based split-gate field effect transistors (FETs) on doped Si/SiO₂ substrates. Several transistors with split gate structures were fabricated and demonstrated AND logic functionality. The transistor’s functionality was controlled by applying either 0 or − 10 V to each of the gate electrodes. When − 10 V was simultaneously applied to both gates, the transistor was conductive (ON), while any other combination of gate voltages rendered the transistor highly resistive (OFF). A significant advantage of this device is that AND logic devices with multiple inputs can be built using a single pentacene channel with multiple gates. The p-type carrier mobility of charge within the pentacene active layer of these transistors was about 10^− 5 cm²/V-s. We attribute the low value of mobility primarily to the sharp contours of the pentacene film between the drain and the source contacts and to defects in the pentacene film. The average charge density was 1.4 × 10¹² holes/cm². Despite low mobility, the devices operated at lower drain-source (V_DS) and gate-source (V_GS) voltages as compared with previously reported pentacene based FETs.     

Electrical characterization of high-k gate dielectrics on Ge with HfGeN and GeO2 interlayers

Two kinds of HfSiO_x/interlayers (ILs)/Ge gate stack structures with HfGeN- and GeO₂-ILs were fabricated using electron cyclotron resonance (ECR) plasma sputtering and the subsequent post deposition annealing (PDA). It was found that HfGe was formed by the deposition of Hf metal on Ge and changed to HfGeN by N₂ ECR-plasma irradiation, which was used as IL. Another IL was GeO₂, which was grown by thermal oxidation at 500 °C. For dielectrics with HfGeN-IL, PDA of 550 °C resulted in effective oxide thickness (EOT) of 2.2 nm, hysteresis of 0.1 V, and interface state density (D_it) = 7 × 10¹² cm^− 2 eV^− 1. For dielectrics with GeO₂-IL, PDA of 500 °C resulted in EOT of 2.8 nm, hysteresis of 0.1 V, and D_it = 1 × 10¹² cm^− 2 eV^− 1. The structural change of HfSiO_x/GeO₂/Ge during the PDA was clarified by using X-ray photoelectron spectroscopy, and the gate stack formation for obtaining the good IL was discussed.     

Amorphous structure and electrical performance of low-temperature annealed amorphous indium zinc oxide transparent thin film transistors

The effect of low-temperature (200 °C) annealing on the threshold voltage, carrier density, and interface defect density of amorphous indium zinc oxide (a-IZO) thin film transistors (TFTs) is reported. Transmission electron microscopy and x-ray diffraction analysis show that the amorphous structure is retained after 1 h at 200 °C. The TFTs fabricated from as-deposited IZO operate in the depletion mode with on-off ratio of > 10⁶, sub-threshold slope (S) of ~ 1.5 V/decade, field effect mobility (μ_FE) of 18 ± 1.6 cm²/Vs, and threshold voltage (V_Th) of − 3 ± 0.7 V. Low-temperature annealing at 200 °C in air improves the on-current, decreases the sub-threshold slope (1.56 vs. 1.18 V/decade), and increases the field effect mobility (μ_FE) from 18.2 to 23.3 cm²/Vs but also results in a V_Th shift of − 15 ± 1.1 V. The carrier density in the channel of the as-deposited (4.3 × 10¹⁶ /cm³) and annealed at 200 °C (8.1 × 10¹⁷ /cm³) devices were estimated from test-TFT structures using the transmission line measurement methods to find channel resistivity at zero gate voltage and the TFT structures to estimate carrier mobility.     

Electrical and structural characterization of AlGaN/GaN field-effect transistors with recessed gate

Performance of AlGaN/GaN heterostructure field-effect transistors (HFETs) with recessed gate was investigated and compared with non-recessed counterparts. Optimal dry etch conditions by plasma assisted Ar sputtering were found for ∼6 nm gate recess of a 20 nm thick AlGaN barrier layer. A decrease of the residual strain after the gate recessing (from −0.9 GPa to −0.68 GPa) was evaluated from the photoluminescence measurement. The saturation drain current at the gate voltage V_G = 1 V decreased from 1.05 A/mm to 0.85 A/mm after the recessing. The gate voltage for a maximal transconductance (240−250 mS/mm) has shifted from −3 V for non-recessed HFETs to −0.2 V for recessed counterparts. Similarly, the threshold voltage increased after the gate recessing. A decrease of the sheet charge density from 1 × 10¹³ cm⁻² to 4 × 10¹² cm⁻² at V_G = 0 V has been evaluated from the capacitance measurements. The RF measurements yielded a slight increase of the cut-off frequencies after the gate recessing. All these indicate that the gate recessing is a useful tool to optimize the AlGaN/GaN HFET performance for high-frequency applications as well as for the preparation of normally-off devices.     

Study on ZnGa2O4:Cr a.c. powder electroluminescent device

An a.c. powder electroluminescent (EL) device using ZnGa₂O₄:Cr³⁺ phosphor was fabricated by the screen printing method. Optical and electrical properties of the device were investigated. The fabricated device shows a red emission at 695 nm driven by the a.c. voltage. The emission is attributed to the energy transfer from hot electrons to Cr³⁺ centers via self-activated Ga-O groups. Luminance (L) versus voltage (V) matches the well-known equation of L = L₀exp(− bV ^− 1 / 2) and luminance increases proportionally with frequency due to the increase of excitation probability of host lattice or Cr³⁺ centers. The diagram of the charge density (Q) versus applied voltage (V) is based on a conventional Sawyer-Tower circuit. At 280 V and 1000 Hz, the luminance and the luminous efficiency of the fabricated powder EL device are about 1.0 cd/m² and 13 lm/W, respectively. And under the high field, the device fabricated with the oxide-based phosphor of ZnGa₂O₄:Cr³⁺ shows excellent stability in comparison with the conventional sulfide powder EL device.     

Improvement of bias stability of indium zinc oxide thin film transistors by the incorporation of hafnium fabricated by radio-frequency magnetron sputtering

We report on the fabrication and performance of amorphous oxide thin film transistors with indium zinc oxide (In₂O₃:ZnO = 1:1 mol%) and various ratios of hafnium-doped indium zinc oxide (IZO:HfO₂ = 2:0, 0.3, 0.7, and 1.1 mol%) deposited at the same deposition conditions for semiconductor channel layer. The carrier concentration (N_cp) of the HIZO films was further decreased from 7.08 × 10¹⁷ to 5.0 × 10¹⁶ cm^− 3. This indicates that Hf metal cations effectively suppress carrier generation due to the high electron negativity (1.3) of Hf. In addition, we compared bias instability of both devices after bias temperature stress (BTS) test under on-current state at V_DS of 10 V and I_DS of 3 μA at 60 °C for 420 min. It was found that the Hf metal cations could be effectively incorporated in the IZO thin films as a suppressor against both the oxygen deficiencies and the carrier generation in the ZnO-based system.     

Ion beam deposition of α-Ta films by nitrogen addition and improvement of diffusion barrier property

Ta thin films were deposited on Si (100) substrates by an ion beam deposition method at various substrate bias voltages under Ar + N₂ atmosphere with different pressure ratios of Ar and N₂. The effects of nitrogen pressure in the plasma gas and the substrate bias voltage on the surface morphology, crystalline microstructure, electrical resistivity and diffusion barrier property were investigated. It was found that the fraction of a metastable β-phase in the Ta film deposited at the substrate bias voltage of − 50 V films decreased by adding nitrogen gas, while the α-Ta phase became dominant. As a result, the Ta films deposited at the substrate bias voltage of − 50 V under Ar (9 Pa) + N₂ (3 Pa) atmosphere showed a dominant α-phase with good surface morphology, low resistivity, and superior thermal stability as a diffusion barrier.     

Electrical and materials properties of AlN/ HfO2 high-k stack with a metal gate

In this study, aluminum nitride (AlN) was grown by molecular layer deposition on HfO₂ that had been deposited on 200 mm Si (100) substrates. The AlN was grown on HfO₂ using sequential exposures of trimethyl-aluminum and ammonia (NH₃) in a batch vertical furnace. Excellent thickness uniformity on test wafers from the top of the furnace to the bottom of the furnace (across the furnace load) was obtained. The equivalent oxide thickness was 16.5-18.8 Å for the AlN/HfO₂ stack on patterned device wafers with a molybdenum oxynitride metal gate with leakage current densities from low 10^− 5 to mid 10^− 6 A/cm² at threshold voltage minus one volt. There was no change in the work function with the AlN cap on HfO₂ with the MoN metal gate, even with a 1000 °C anneal.     

ZnO-based metal-semiconductor field-effect transistors with Ag-, Pt-, Pd-, and Au-Schottky gates

Metal-semiconductor field-effect transistors (MESFETs) were fabricated by reactive dc sputtering of either Ag, Pt, Pd, and Au as Schottky gate contacts on ZnO thin films grown by pulsed-laser deposition on a-plane sapphire substrates. The individual properties and influences of the four gate metals on the performance of the MESFETs have been investigated. Pt- and Ag-gate MESFETs show excellent electric properties with on/off-ratios of 4.5 × 10⁶ and 1.1 × 10⁸, respectively, and low off-currents in the picoampere range. The leakage currents for Pd- and Au-MESFETs are 2 and 4 orders of magnitude higher than for Ag. Maximum off-voltages of − 1.4 V have to be applied at the gate in order to fully close the n-type (normally-on) channels. Channel mobilities of 6.3, 11.4, 12.8, and 24 cm²/Vs were observed for Ag, Pt, Pd, and Au, respectively. Studies of the device performance at elevated temperatures in the range between 25 °C and 150 °C revealed that the MESFETs are stable at least until 75 °C. An annealing effect, which improved the MESFET's electric properties, could be observed for Ag, Pt, and Au.     

Low temperature short channel polycrystalline silicon thin film transistors with high reliability for flat panel display

We have investigated a short channel (L ≤ 1 μm) effect on the electrical reliability of the low temperature poly-Si thin film transistors (TFT) on a glass substrate. The threshold voltage of the p-type poly-Si TFT was observed to be decreased due to the drain induced barrier lowering as the channel length decreased. In the n-type poly-Si TFT with a lightly-doped-drain (LDD), the threshold voltage was slightly decreased when a high drain voltage was applied, while the field effect mobility decreased due to the series resistance of the LDD region in the short channel poly-Si TFT. As the temperature increased, the field effect mobility increased about 80% due to the increase of the thermal activated carrier concentration. We have also investigated the degradation of a short channel poly-Si TFT under hot carrier and self-heating stress. After hot carrier stress (V_GS = 2V, V_DS = 15V), the field effect mobility was considerably decreased up to 20% due to the trap state generation induced by the hot carrier. The subthreshold slope and threshold voltage were scarcely degraded. After the self-heating stress (V_GS = V_DS = 15V), the subthreshold slope, mobility, and threshold voltage were degraded. Transfer characteristics measured at the high drain voltage (V_DS = 10V) were shifted to a negative direction because of hole trapping at the backside interface between the polysilicon film and buffer oxide on the glass substrate.     

Nonlinear current-voltage properties and accelerated aging behavior of ZPCCL-based varistors with sintering temperature

The nonlinear electrical properties and accelerated aging behavior of the varistors, which are composed of ZnO-Pr₆O₁₁-CoO-Cr₂O₃-La₂O₃ (ZPCCL)-based ceramics, were investigated for different sintering temperatures. The increase of sintering temperature led to more densified ceramics, whereas it decreased the nonlinear properties and varistor voltage. The highest nonlinearity of varistors was obtained from sintering temperature of 1240 °C, in which the nonlinear coefficient is 79.4 and the leakage current is 0.3 μA. However, the highest stability of varistors was obtained from sintering temperature of 1260 °C, in which the %ΔV_1 mA is + 1.9%, the %Δα is − 10.6%, and the %ΔI_L is + 20% for stress state of 95 V_1 mA/150 °C/24 h.