Program Cache Busy Time Control Method for Reducing Peak Current Consumption of NAND Flash Memory in SSD Applications

In current NAND flash design, one of the most challenging issues is reducing peak current consumption (peak ICC), as it leads to peak power drop, which can cause malfunctions in NAND flash memory. This paper presents an efficient approach for reducing the peak ICC of the cache program in NAND flash memory — namely, a program Cache Busy Time (tPCBSY) control method. The proposed tPCBSY control method is based on the interesting observation that the array program current (ICC2) is mainly decided by the bit‐line bias condition. In the proposed approach, when peak ICC2 becomes larger than a threshold value, which is determined by a cache loop number, cache data cannot be loaded to the cache buffer (CB). On the other hand, when peak ICC2 is smaller than the threshold level, cache data can be loaded to the CB. As a result, the peak ICC of the cache program is reduced by 32% at the least significant bit page and by 15% at the most significant bit page. In addition, the program throughput reaches 20 MB/s in multiplane cache program operation, without restrictions caused by a drop in peak power due to cache program operations in a solid‐state drive.     

Comparative Study of Quick Electron Detrapping and Random Telegraph Signal and Their Dependences on Random Discrete Dopant in Sub-40-nm NAND Flash Memory

In sub-40-nm Flash memory, random discrete dopant (RDD) effect modulates post program/erase (P/E) cycling $V_{t}$ instabilities through quick electron detrapping (QED) as well as random telegraph signal (RTS). In this letter, for the first time, we discuss the QED phenomenon and its physical origin by comparison with RTS phenomenon. P/E cycling stress not only aggravates the RTS but also generates the new phenomenon of QED which results from transiently trapped charges at near-interface defects during program. By applying a new test algorithm, we could successfully extract the QED component from RTS, both of which are modulated by RDD effect and worsen tail bits in multilevel-cell Flash memory.      

A 16 Gb 3-Bit Per Cell (X3) NAND Flash Memory on 56 nm Technology With 8 MB/s Write Rate

A 16 Gb 8-level NAND flash chip on 56 nm CMOS technology has been fabricated and is being reported for the first time. This is the first 3-bit per cell (X3) chip published with all-bitline (ABL) architecture, which doubles the write performance compared with conventional shielded bitline architecture. A new advanced cache program algorithm provides another 15% improvement in write performance. This paper also discusses a technique for resolving the sensing error resulting from cell source line noise, which usually varies with the data pattern. The new architecture and advanced algorithm enable an 8 MB/s write performance that is comparable to previously published 2-bit per cell (4-level) NAND performance. Considering the significant cost reduction compared to 4-level NAND flash based on the same technology, this chip is a strong candidate for many mainstream applications.     

Design of Integrated Selection and Recirculation Circuitry for a High-Speed, Low-Power, Magnetic Thin-Film Memory

The circuit design for a high-speed, low-power, magnetic thin-film memory is described. The modest operating-current requirements of the memory element, 50 milliampere word currents and 40 milliampere bit currents, permit the use of integrated selection and recirculation circuits. The selection system uses one transistor per word line and has a matrix array of word drivers and word switches to select one word line. Word current rise time is 2 to 3 nanoseconds. The 1-millivolt readout signal, 6 nanoseconds in duration, is amplified by means of a high-gain (1400), wide-band (50 Mc/s) sense amplifier with a differential input stage. Information is written into the memory with a bit driver which generates 40 milliampere current pulses of either polarity. Design considerations such as the ac coupling in the sense arnplifier, the relation between amplifier internal noise and system mean free time between errors, and the minimization of noise are discussed. A variety of transistor geometries was used to optimize the devices to the individual circuit functions. These geometries are illustrated.     

Novel Planar Electromagnetic Bandgap Structures for Mitigation of Switching Noise and EMI Reduction in High-Speed Circuits

Planar electromagnetic bandgap (EBG) structures with novel meandered lines and super cell configuration are proposed for mitigating simultaneous switching noise propagation in high-speed printed circuit boards. An ultrawide bandgap extending from 250 MHz to 12 GHz and beyond is demonstrated by both simulation and measurement, and a good agreement is observed. These perforated EBG-based power planes may cause spurious and unwanted radiation. In this paper, leakage radiation through these imperfect planes is carefully investigated. It is found that the leakage field from these planar EBG structures is highly concentrated around the feed point, and the field intensity is attenuated dramatically when passing across several periods of patches. A novel concept of using these EBG structures for electromagnetic interference reduction is also introduced. Finally, the impact of power plane with EBG-patterned structures on signal integrity is studied.     

High-Speed and Low-Power IP for Embedded Block Coding with Optimized Truncation (EBCOT) Sub-Block in JPEG2000 System Implementation

In this paper we propose novel high-speed and low-power architecture for the context formation sub-block in tier-1 block of JPEG2000 system. The proposed architecture is inspired from the statistical analysis results on 20 test images, each one 512*512 pixels, gray scale with 8 bit pixels. The proposed architecture incorporates a check unit to detect unnecessary operations in both pass1 and pass2 of the EBCOT block. For code block size of 64*64 bits, the timing and power consumption analysis show that the proposed architecture reduces the power consumption about 20.64% and increases the processing speed to about 33.67% with respect to the speedy reference architecture. The proposed architecture has a processing speed close to the parallel mode architectures with almost the same area for serial mode architectures and more power saving. The proposed architecture gathers the basic advantages of the serial and parallel mode implementations in addition to lower power consumption. Ramy E. Aly received the B.S. degree in electrical engineering from University of Alexandria, Egypt, in 1994, and the M.S. degree in electrical engineering from Old Dominion University, VA, in 2001 and M.S. in computer engineering from University of Louisiana at Lafayette, in 2002. He is currently working toward his Ph.D. degree at the Center for Advanced Computer Studies (CACS), University of Louisiana, Lafayette. Since 2001, he has been a Research Assistant with the CACS, in the VLSI Research group of M. A. Bayoumi, University of Louisiana. His research interests include low-power VLSI circuit design, low-power SRAM design, JPEG2000 Architecture and CAD-tools. Magdy A. Bayoumi(S'80-M'84-SM'87-F'99) received the B.Sc. and M.Sc. degrees in electrical engineering from Cairo University, Cairo, Egypt, in 1973 and 1977, the M.Sc. degree in computer engineering from Washington University in St. Louis, MO, in 1981, and the Ph.D. degree in electrical engineering from the University of Windsor, Windsor, ON, Canada, in 1984. Currently, he is the Director of the Center for Advanced Computer Studies (CACS), Department Head of the Computer Science Department, the Edmiston Professor of Computer Engineering, and the Lamson Professor of Computer Science at The Center for Advanced Computer Studies, University of Louisiana at Lafayette, where he has been a Faculty Member since 1985. He has edited and coedited three books in the area of VLSI Signal Processing. He has one patent pending. His research interests include VLSI design methods and architectures, low-power circuits and systems, digital signal processing architectures, parallel algorithm design, computer arithmetic, image and video signal processing, neural networks, and wide-band network architectures. Dr. Bayoumi received the University of Louisiana at Lafayette 1988 Researcher of the Year Award and the 1993 Distinguished Professor Award. He was an Associate Editor of the IEEE CIRCUITS AND DEVICES MAGAZINE, the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, the IEEE TRANSACTIONS ON NEURAL NETWORKS, and the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: ANALOG AND DIGITAL SIGNAL PROCESSING. He was an Associate Editor of the Circuits and Devices Magazine and is currently an Associate Editor of Integration, the VLSI Journal, and the Journal of VLSI Signal Processing Systems. He is a Regional Editor for the VLSI Design Journal and on the Advisory Board of the Journal on Microelectronics Systems Integration. From 1991 to 1994, he served on the Distinguished Visitors Program for the IEEE Computer Society, and he is on the Distinguished Lecture Program of the Circuits and Systems Society. He was the Vice President for technical activities of the IEEE Circuits and Systems Society. He was the Cochairman of the Workshop on Computer Architecture for Machine Perception in 1993, and is a Member of the Steering Committee of this workshop. He was the General Chairman of the 1994 MWSCAS and is a Member of the Steering Committee of this symposium. He was the General Chairman for the 8th Great Lake Symposium on VLSI in 1998. He has been on the Technical Program Committee for ISCAS for several years and he was the Publication Chair for ISCAS'99. He was also the General Chairman of the 2000 Workshop on Signal Processing Design and Implementation. He was a founding member of the VLSI Systems and Applications Technical Committee and was its Chairman. He is currently the Chairman of the Technical Committee on Circuits and Systems for Communication and the Technical Committee on Signal Processing Design and Implementation. He is a Member of the Neural Network and the Multimedia Technology Technical Committees. Currently, he is the faculty advisor for the IEEE Computer Student Chapter at the University of Louisiana at Lafayette.     

Novel pumping schemes for fluoride-based thulium-doped fiber amplifier at 690 and 1050 nm (or 1400 nm)

Signal amplification in the S- and S/sup +/-band is demonstrated for the first time by simultaneous pumping of thulium-doped fiber amplifier (TDFA) with 690 and 1050 nm (or 1400 nm). Both pumping schemes are investigated and shown to be highly efficient: Roughly 20 dB of signal gain is available with only 80 mW of 1050 nm plus 42 mW of 690 nm, while signal input power is fixed at -35 dBm. Furthermore, these excitations can take advantage of low-cost readily available pump laser diodes at 690 nm for digital video disk applications. This makes TDFA a promising candidate for coarse wavelength-division-multiplexing applications in metropolitan area network and access network environment.     

High Injection Efficiency and Low-Voltage Programming in a Dopant-Segregated Schottky Barrier (DSSB) FinFET SONOS for nor-type Flash Memory

A dopant-segregated Schottky barrier (DSSB) FinFET silicon–oxide–nitride–oxide–silicon (SONOS) for nor-type Flash memory is successfully demonstrated. Compared with a conventional FinFET SONOS device, the DSSB FinFET SONOS device exhibits high-speed programming at low voltage. The sharp dopant-segregated Schottky contact at the source side can generate hot electrons, and it can be used to provide high injection efficiency at low voltage without any constraint on the choice of the proper gate and drain voltage. The DSSB FinFET SONOS device is therefore a promising candidate for nor-type Flash memory with high-speed and low-power programming.      

Theory and Design of Broad-Band Nongrounded Matched Loads for Planar Circuits (Short Paper)

A filter theory approach is used for the synthesis of very broad-band resistive terminations with no direct grounding. The immediate use is in microwave integrated circuits (MIC's) where no holes or wraparound straps are desirable. Bandwidths achieved amount to 100 and 160 percent for networks of order 2 and 6, respectively. The total circuit lengths are lambda and 3 lambda/2 in these cases. This performance is superior to older designs where only 30-40 percent is obtained.     

Formation of uniform GaAs multi-atomic steps with 20–30 nm periodicity and related structures on vicinal (111)B planes by MBE

We studied morphology of GaAs surfaces and the transport properties of two-dimensional electron gas (2DEG) on vicinal (111)B planes. Multi-atomic steps (MASs) are found on the vicinal (111)B facet grown by molecular beam epitaxy, which will affect electron transport on the facet. We also studied how the morphology of GaAs epilayers on vicinal (111)B substrates depends on growth conditions, especially on the As₄ flux. The uniformity of MASs on the substrates have been improved and smooth surfaces were obtained when the GaAs was grown with high As₄ flux, providing step periodicity of 20 nm. The channel resistance of the 2DEG perpendicular to the MASs is reduced drastically with this smooth morphology. These findings are valuable not only for fabricating quantum devices on the (111)B facets but also those on the vicinal (111)B substrates.     

Evaluation of a PECVD advanced barrier (k = 3.7) for 32 nm CMOS technology and below

An advanced dielectric barrier proposed for sub-45 nm CMOS technology nodes is firstly characterized on 300 mm full sheet wafers. The barrier is a bi-layer deposited by PECVD. The copper diffusion barrier property is ensured by a depositing dense initiation layer with the efficiency of a standard SiCN barrier (k = 5.0). The top layer, thicker, with lower density, enables the decrease of the barrier k-value to 3.66 and plays the role of etch stop layer. Combined with a PECVD porous a-SiOC:H dielectric (k-value = 2.5), the advanced dielectric barrier is successfully integrated in a C65 dual damascene architecture reaching a 3% gain in RC. A high via chain resistance yield is evidence of good via opening. Finally, the advanced barrier shows the same electromigration performance than the standard SiCN barrier.     

Fin Width $(W_{rm fin})$ Dependence of Programming Characteristics on a Dopant-Segregated Schottky-Barrier (DSSB) FinFET SONOS Device for a NOR-Type Flash Memory Device

This letter is aimed at experimentally investigating the fin width (W_fin) dependence of both a dopant-segregated Schottky-barrier (DSSB) and a conventional FinFET SONOS device with diffused p-n junctions for application of a NOR-type flash memory device. High parasitic resistance (R_para) at the source/drain by a narrowed W_fin results in degradation of memory performance for the conventional FinFET SONOS device. In contrast, it is shown that a narrow W_fin significantly improves the memory performance for the DSSB FinFET SONOS device, resulting from an improved lateral electric field without a significant change of the R_para value.     

Time-dependent dielectric wearout technique with temperature effect for reliability test of ultrathin (<2.0 nm) single layer and dual layer gate oxides

Ultrathin gate oxide is essential for low supply voltage and high drive current for ULSI devices. The continuous scaling of oxide thickness has been a challenge on reliability characterization with conventional time-dependent dielectric breakdown (TDDB) technique. A new technique, the time-dependent dielectric wearout (TDDW), is proposed as a more practical and effective way to measure oxide reliability and breakdown compared to conventional TDDB methodology. The wearout of oxide is defined as the gate current reaches a critical current density with the circuit operating voltage level. It is shown that although a noisy soft breakdown always exists for ultrathin oxide, with constant-voltage stressing, a big runaway can also be observed for oxides down to 1.8 nm by monitoring the I–V characteristics at a reduced voltage. Devices are found still working after soft breakdowns, but no longer functional after the big runaway. However, by applying E-model to project dielectric lifetime, it shows that the dielectric lifetime is almost infinity for the thermal oxide at 1.8 nm range. It is also demonstrated that the dual voltage TDDW technique is also able to monitor the breakdown mechanism for nitride/oxide (N/O) dual layer dielectrics.     

Confocal Microscopy for In Situ Multi-Modal Characterization and Patterning of Laser-Reduced Graphene Oxide (Adv. Funct. Mater. 30/2023)

Graphene oxide (GO) films can be readily prepared at wafer scale, then reduced to form graphene-based conductive circuits relevant to a range of practical device applications. Among a variety of reduction methods, laser processing has emerged as an important technique for localized reduction and patterning of GO films. In this study, the novel use of confocal microscopy is demonstrated for high-resolution characterization, in situ laser reduction, and versatile patterning of GO films. Multi-modal imaging and real-time tracking are performed with 405 and 488 nm lasers, enabling large-area direct observation of the reduction progress. Using image analysis to cluster flake types, the different stages of reduction can be attributed to thermal transfer and accumulation. Delicate control of the reduction process over multiple length scales is illustrated using millimeter-scale stitched patterns, micropatterning of single flakes, and direct writing conductive 2D wires with sub-micrometer resolution (530 nm). The general applicability of the technique is shown, allowing fabrication of both conductive reduced graphene oxide (rGO) films (sheet resistance: 2.5 kOhm sq⁻¹) and 3D microscale architectures. This simple and mask-free method provides a valuable tool for well-controlled and scalable fabrication of reduced GO structures using compact low-power lasers (< 5 mW), with simultaneous in situ monitoring and quality control.     

Modification of Novel Conductive PEDOT:Sulfonated Polyimide Nano-Thin Films by Anionic Surfactant and Poly(vinyl alcohol) for Electronic Applications

Conductive poly(3,4-ethylenedioxythiophene):sulfonated polyimide (PEDOT: SPI) nanoscale thin films were successfully developed by addition of anionic surfactant and poly(vinyl alcohol) (PVA) for potential application in electronic devices. In this work, sodium dodecyl sulfate (SDS) surfactant was introduced into PEDOT:SPI aqueous suspensions to improve the dispersion stability of the particles in water, leading to high transparency and low contact angle of PEDOT:SPI thin films. All of the conducting polymer thin films showed high transparency of more than 85% transmission. Conductivity enhancement and good film-formation properties of PEDOT:SPI were achieved by adding various amounts of PVA to each polymer aqueous suspension because of the resulting conformational changes. The highest conductivity of 0.134 S/cm was achieved at 0.08 wt.% PVA in PEDOT:SPI2/SDS/PVA film, increased by a factor of 3.5 compared with the original material. In addition, PVA also improved the thermal stability of the conductive films, as verified by thermogravimetric analysis (TGA). The interactions between conducting polymers, PVA, and SDS surfactant affecting nano-thin film properties were revealed and investigated. Moreover, the interactions between SDS and SPI were proven to be different from those between SDS and poly(styrenesulfonate) (PSS) in conventional PEDOT:PSS solutions.     

Energy-Band-Engineered Unified-RAM (URAM) Cell on Buried $hbox{Si}_{1 - y}hbox{C}_{y}$ Substrate for Multifunctioning Flash Memory and 1T-DRAM

A band-offset-based unified-RAM (URAM) cell fabricated on a Si/$ hbox{Si}_{1 - y}hbox{C}_{y}$ substrate is presented for the fusion of a nonvolatile memory (NVM) and a capacitorless 1T-DRAM. An oxide/nitride/oxide (O/N/O) gate dielectric and a floating-body are combined in a FinFET structure to perform URAM operation in a single transistor. The O/N/O layer is utilized as a charge trap layer for NVM, and the floating-body is used as an excess hole storage node for capacitorless 1T-DRAM. The introduction of a pseudomorphic SiC-based heteroepitaxial layer into the Si substrate provides band offset in a valence band. The FinFET fabricated on the energy-band-engineered $hbox{Si}_{1 - y}hbox{C}_{y}$ substrate allows hole accumulation in the channel for 1T-DRAM. The band-engineered URAM yields a cost-effective process that is compatible with a conventional body-tied FinFET SONOS. The fabricated URAM shows highly reliable NVM and high-speed 1T-DRAM operations in a single memory cell.      

Integrated modeling of Self-heating of confined geometry (FinFET,NWFET, and NSHFET) transistors and its implications for the reliability of sub-20 nm modern integrated circuits

The evolution of transistor topology from planar to confined geometry transistors (i.e., FinFET, Nanowire FET, Nanosheet FET) has met the desired performance specification of sub-20 nm integrated circuits (ICs), but only at the expense of increased power density and thermal resistance. Thus, self-heating effect (SHE) has become a critical issue for performance/reliability of ICs. Indeed, temperature is one of the most important factors determining ICs reliability, such as Negative Bias Temperature Instability (NBTI), Hot Carrier Injection (HCI), and Electromigration (EM). Therefore, an accurate SHE model is essential for predictive, reliability-aware ICs design. Although SHE is collectively determined by the thermal resistances/capacitances associated with various layers of an IC, most researchers focus on isolated components within the hierarchy (i.e., a single transistor, few specific circuit configurations, or specialized package type). This fragmented approach makes it difficult to verify the implications of SHE on performance and reliability of ICs based on confined geometry transistors. In this paper, we combine theoretical modeling and systematic transistor characterization to extract thermal parameters at the transistor level to demonstrate the importance of multi-time constant thermal circuits to predict the spatio-temporal SHE in modern sub-20 nm transistors. Based on the refined Berkeley Short-channel IGFET Model Common Multi-Gate (BSIM-CMG) model, we examine SHE in typical digital circuits (e.g., ring oscillator) and analog circuits (e.g., two-stage operational amplifier) by Verilog-A based HSPICE simulation. Similarly, we develop a physics-based thermal compact model for packaged ICs using an effective media approximation for the Back End Of Line (BEOL) interconnects and ICs packaging. We integrate these components to investigate SHE behavior implication on ICs reliability and explain why one must adopt various (biomimetic) strategies to improve the lifetime of self-heated ICs.