New compact CMOS continuous-time low-Voltage analog rank-order filter architecture

A new compact CMOS continuous-time analog rank-order filter topology is presented. The hardware complexity grows linearly with the number of inputs at the rate of only two transistors per input. The implementation is based on a multiple input differential structure. The rank is programmable with the tail current source for all rank-order values from the Min to the Max case. The circuit has low voltage and low power consumption requirements. Experimental results are presented that verify the functionality and accuracy of the circuit. Simulation results show satisfactory operation in the 100-MHz frequency range for 0.5-/spl mu/m CMOS technology and using a single 1.8-V supply. Two buffered versions of the circuit and efficient techniques for reduction of corner errors are also discussed.     

A CMOS analog continuous-time delay line with adaptive delay-timecontrol

A CMOS analog continuous-time delay line composed of cascaded first-order current-domain all-pass sections is discussed. Each all-pass section consists of CMOS transistors and a single capacitor. The operation is based on the square-law characteristic of an MOS transistor in saturation. The delay time per section can either be controlled by an external voltage or locked to an external reference frequency by means of a control system which features a large capture range. Experimental verification has been performed on two setups: an integrated cascade of 26 identical all-pass sections and a frequency-locking system breadboard built around two identical on-chip all-pass sections     

An elliptic continuous-time CMOS filter with on-chip automatic tuning

A voice-band continuous-time filter is described which was designed based on the technique of fully balanced networks and was fabrication in a 3.5-/spl mu/ CMOS technology. The filter implements a fifth-order elliptic low-pass transfer function with 0.05-dB passband ripple and 3.4 kHz cutoff frequency. A phase-locked loop control system fabricated on the same chip automatically references the frequency response of the filter to an external fixed clock frequency. The cutoff frequency was found to vary by less than 0.1% for an operating temperature range of 0-85/spl deg/C. The absolute value accuracy of the cutoff frequency was 0.5% (standard deviation). With /spl plusmn/5-V power supplies the measured dynamic range of the filter was approximately 100 dB.     

An analog continuous-time neural network

An analog continuous-time neural network is described. Building blocks which include the capability for on-chip learning and an example network are described and test results are presented. We are using analog nonvolatile CMOS floating-gate memories for storage of the neural weights. The floating-gate memories are programmed by illuminating the entire chip with ultraviolet light. The subthreshold operation of the CMOS transistor in analog VLSI has a very low power dissipation which can be utilized to build larger computational systems, e.g., neural networks. The experimental results show that the floating-gate memories are promising, and that the building blocks are operating as separate units; however, especially the time constants involved in the computations of the continuous-time analog neural network should be studied further.     

High-linearity continuous-time filter in 5-V VLSI CMOS

High-linearity self-tuning continuous-time filters, fabricated in a standard 1.6-μm 5-V CMOS process, are presented. Frequency control is achieved using switchable arrays of highly linear double-polysilicon capacitors in an active RC filter structure, resulting in tunable filters with very low signal distortion. One filter, a Tow-Thomas biquad, exhibits dynamic range and signal linearity of typically 91 dB. Another smaller implementation, a Sallen and Key filter, attains ⩾76 dB. Cutoff frequency response is maintained to an accuracy of around ±5%     

A Gm-C continuous-time anti-alias filter for UWB analog front-end

A proposed constant drain-source transconductor topology is designed to keep linearity at high frequency. By using the proposed operational transconductance amplifier as a building block, a fourth-order low-pass filter is realized. The filter was fabricated in 0.18 μm CMOS technology and feathers a 250 MHz cutoff frequency. The measured IM3 performance is ?36 dB at 0.6 V_pp input swing and the power consumption is 22 mW.     

A field programmable analog array for CMOS continuous-time OTA-Cfilter applications

A programmable high-frequency operational transconductance amplifier (OTA) is proposed and analyzed. A general configurable analog block (CAB) is presented, which consists of the proposed programmable OTA, programmable capacitor and MOSFET switches. Using the CABs, the universal tunable and field programmable analog array (FPAA) can be constructed, which can realize many signal-processing functions, including filters. A tuning circuit is also discussed. The proposed OTA has been simulated and fabricated in CMOS technology. The results show that the OTA has the transconductance tunable/programmable in a wide range of 700 times and the -3-dB bandwidth larger than 20 MHz. A universal 5×8 CAB array has been fabricated. The chip has also been configured to realize OTA-C 60-kHz and 500-kHz bandpass filters based on ladder simulation and biquad cascade     

A micropower CMOS continuous-time filter with on-chip automatic tuning

This paper presents a CMOS implementation of a low-voltage micropower G/sub m/-C biquad with on-chip automatic tuning. The filter is suitable for any kind of application involving low-frequency ranges, and very low-power consumption, such as biomedical devices. The operational transconductance amplifier (OTA) is implemented with the transistors working in the weak inversion saturation region, thus allowing the use of very small currents that minimize the power consumption. The aspect ratios are small enough not to degrade the frequency response. The tuning algorithm is based on amplitude tracking. The filter output amplitude is quantized using a low-power amplifier and an asymmetric comparator. A digital controller varies the tuning parameters until the maximum quantized amplitude is found. The system works down to a voltage supply of 1.75 V. The center frequency is tunable over one and a half decades, from 300 Hz to 10 kHz for bias currents changing from 6 to 200 nA and a 20-pF integrating capacitance, giving an overall filter accuracy of up to 99.55%. The power consumption of the second-order filter including the common-mode correction circuitry is in the order of 200 nW for the 10-nA bias current. It exhibits a dynamic range of 54 dB and occupies an area of 0.06 mm/sup 2/ excluding the area of the integrating capacitances.     

Design of low-voltage CMOS continuous-time filter with on-chipautomatic tuning

A technique for designing a low-voltage continuous-time active filter is presented in this paper. In this technique, current sources are added to the inverting or noninverting op-amp terminals such that the op-amp input common-mode voltages can be set close to one of the supply rails to allow low-voltage operation. An automatic frequency and Q tuning technique is proposed for tuning the active filter using programmable capacitor arrays (PCAs). The proposed tuning technique does not require any peak detectors, which are difficult to implement at a low supply voltage. Instead, it uses a few analog comparators, a digital comparator, and a few binary counters to adjust the PCAs. To demonstrate the proposed techniques, a 1-V 1-MHz second-order filter fabricated in a conventional 1.2-μm CMOS process is presented. For a 5-kHz input signal, the filter achieves a THD of -60.2 dB for a peak-to-peak output voltage of 600 mV. The frequency tuning range is between 585 kHz and 1.325 MHz. The measured power consumption for the filter alone consumes about 0.52 mW and for the entire system consumes about 1.6 mW for a supply voltage of ±0.5 V     

High-frequency voltage-controlled continuous-time lowpass filter using linearised CMOS integrators

The design and implementation of a continuous-time lowpass filter with voltage-controlled cutoff frequency and passband ripple is presented. The circuit uses a linearised CMOS transconductor as a basic integrating building block. A voltage-controlled phase-adjusting scheme is employed in the integrator to compensate for excess phase in the transconductance at high frequencies. The fabricated filter is capable of realising cutoff frequencies as high as 2 MHz and handles single-ended input signals up to 4 V p-p with less than 1% distortion.     

A fully parallel CMOS analog median filter

A fully integrated CMOS implementation of a continuous-time analog median filter is presented. The median filter uses two compact analog circuits as building blocks to implement the variable delay and median detection. Median detectors are based on current saturating transconductance comparators, while the time delay is implemented using first-order all-pass filters. Both circuits allow modular expansion for the implementation of large median filter array processors. Based on these blocks, a new fast technique for parallel image processing is presented. It is shown that an image of 91/spl times/80 pixels can be processed in less than 8 /spl mu/s using an array of median filter cells. Experimental results of a test chip prototype in 2-/spl mu/m CMOS MOSIS technology are presented.     

An analog CMOS autopilot

Results are presented of an analog LSI CMOS missile autopilot. The autopilot is a two-chip set which requires a total area of 210000 sq miles and consumes 700 mW of power. The set is fabricated in a double-poly p-well silicon-gate technology. The chips perform a wide array of analog functions, including precision filtering, full-wave demodulation, digital-to-analog conversion, limiting, pulsewidth modulation, and offset cancellation. A number of digital functions are also provided. The chip set was functionally correct on the first iteration after computer-aided verification. The output noise of the chip set is 6.5 mV, integrated over a bandwidth of 5-500 Hz. Results are presented over a temperature range of -55/spl deg/C to 125/spl deg/C.     

A 4-MHz CMOS continuous-time filter with on-chip automatic tuning

A third-order elliptic low-pass continuous-time filter with a 4-MHz cutoff frequency, integrated in a 3-μm p-well CMOS process, is presented. The design procedure is based on the direct simulation of a doubly terminated LC ladder filter by capacitors and fully balanced, current-controlled transconductance amplifiers with extended linear range. The on-chip automatic tuning circuit uses a phase-locked loop implemented with an 8.5-MHz controlled oscillator that matches a specific two-integrator loop of the filter. The complete circuit features 70-dB dynamic range (THD<-50 dB) and consumes only 16 mW from ±2.5-V supplies     

A sampled analog MOS LSI adaptive filter

Describes a novel realization of an adaptive filter using sampled analog MOS LSI techniques in which the basic functional block is an electrically programmable transversal filter whose tap weights are modified according to the least mean square algorithm. A rotating tap weight structure is used to realize a 32-tap programmable transversal filter with features for the adaptive operation included on an NMOS silicon gate chip. A wide range of magnitude and phase characteristics have been used to test this system and the results on the residual error and the convergence time under different conditions are reported. Some practical limitations are also presented.     

Electronically tunable high-input impedance voltage-mode universal biquadratic filter based on simple CMOS OTAs

This paper describes a new electronically tunable three inputs and single output voltage-mode universal biquadratic filter based on simple CMOS operational transconductance amplifiers (OTAs) and grounded capacitors. The proposed configuration provides lowpass, highpass, bandpass, bandstop and allpass voltage responses at a high impedance input terminal, which enable easy cascadability. Additionally, the circuit parameters ω_o${\omega }_o$ and Q   can be set orthogonally by adjusting the transconductances and grounded capacitors. The filter also offers an independent electronic control of parameters ω_o${\omega }_o$ by adjusting the transconductance through the bias current/voltage of the OTA. For realizing all the filter responses, no critical component matching condition is required, and all the incremental parameter sensitivities are low. PSPICE simulation results are performed to confirm the theoretical analysis.     

Active-phase-compensated biquadratic highpass filter

A new three-amplifier active-phase-compensated biquadratic highpass filter is presented. It is shown that for the matched amplifiers the circuit exhibits a stable Q-factor and, unlike the Akerberg and Mossberg highpass circuit, feedforward paths are not required.     

A 2-μm CMOS fifth-order low-pass continuous-time filter forvideo-frequency applications

A fifth-order elliptic low-pass continuous-time filter based on triode transconductors for applications in the video frequency range is presented. Fabricated in a standard 2-μm CMOS technology, the circuit occupies 6 mm² of silicon area including the automatic tuning circuitry. The filter achieves a 7-MHz cutoff frequency using a parasitic pole compensation scheme. The dynamic range is 40 dB and power consumption is 30 mW for a 5-V supply. A transconductor biasing strategy which allows a continuous tuning range for the cutoff frequency of one decade is presented     

A 10.7-MHz 68-dB SNR CMOS continuous-time filter with on-chipautomatic tuning

A maximally flat 10.7-MHz fourth-order bandpass filter with an on-chip automatic tuning system is presented. The signal-to-in-band integrated noise ratio (SNR) of the automatically tuned filter is around 68 dB. The third intermodulation distortion (IM3) is lower than -40 dB for a two-tone input signal of 3.2 V peak to peak (V_p-p). The complete system operates with supply voltages of ±2.5 V. The power consumption of the system is 220 mW. All this has been achieved due to the use of a low-distortion transconductor, the development of a high-frequency CMOS resistor, and the realization of an advanced on-chip automatic tuning system for both frequency and bandwidth control. The chip has been fabricated in a standard 1.5-μm n-well CMOS process     

An improved CMOS active-R filter

New CMOS building blocks are proposed for inverting and noninverting buffered integrators using only resistors and CMOS transistor arrays. These buildings blocks are then used to design state variable type active-R filters without the use of external capacitors. The new circuits do not suffer the loading problems associated with other active-R realization, and are much less susceptible to distortion and instability. Furthermore, the possibility of voltage tunable filters is demonstrated.     

A low power CMOS 3.3 Gbps continuous-time adaptive equalizer for serial link

This paper describes using a high-speed continuous-time analog adaptive equalizer as the front-end of a receiver for a high-speed serial interface,which is compliant with many serial communication specifications such as USB2.0,PCI-E2.0 and Rapid 10.The low and high frequency loops are merged to decrease the effect of delay between the two paths,in addition,the infinite input impedance facilitates the cascade stages in order to improve the high frequency boosting gain.The implemented circuit architecture could facilitate the wide frequency range from 1 to 3.3 Gbps with different length FR4-PCB traces,which brings as much as 25 dB loss.The replica control circuits are injected to provide a convenient way to regulate common-mode voltage for full differential operation.In addition,AC coupling is adopted to suppress the common input from the forward stage.A prototype chip was fabricated in 0.18-μm 1P6M mixed-signal CMOS technology.The actual area is 0.6×0.57 mm~2 and the analog equalizer operates up to 3.3 Gbps over FR4-PCB trace with 25 dB loss.The overall power dissipation is approximately 23.4 mW.