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1.
This paper discusses the design and implementation of a stereo image digitizer for use in digital image processing applications. The system operates in real time with respect to the standard television refresh rate and it possesses several signal sampling, routing, and transformation options which can be controlled from an external digital computer. Results obtained with a prototype unit are illustrated and compared using precision test patterns and natural scenes.  相似文献   

2.
One of the problems in the development of multiprocessor systems for image analysis is the selection and efficient utilization of an interconnection network between the multiple processing units. This paper proposes a system organization centered around a class of interconnection networks and a global bus. Control schemes are developed for realizing the intertask communication requirements typically encountered in the parallel formulation of problems for image analysis. These schemes are simple, distributed and efficient. The utility of this organization is demonstrated by evaluating the performance of two applications.  相似文献   

3.
This paper presents novel algorithmic and architectural solutions for real-time and power-efficient enhancement of images and video sequences. A programmable class of Retinex-like filters, based on the separation of the illumination and reflectance components, is proposed. The dynamic range of the input image is controlled by applying a suitable non-linear function to the illumination, while the details are enhanced by processing the reflectance. An innovative spatially recursive rational filter is used to estimate the illumination. Moreover, to improve the visual quality results of two-branch Retinex operators when applied to videos, a novel three-branch technique is proposed which exploits both spatial and temporal filtering. Real-time implementation is obtained by designing an Application Specific Instruction-set Processor (ASIP). Optimizations are addressed at algorithmic and architectural levels. The former involves arithmetic accuracy definition and linearization of non-linear operators; the latter includes customized instruction set, dedicated memory structure, adapted pipeline, bypasses, custom address generator, and special looping structures. The ASIP is synthesized in standard-cells CMOS technology and its performances are compared to known Digital signal processor (DSP) implementations of real-time Retinex filters. As a result of the comparison, the proposed algorithmic/architectural design outperforms state-of-art Retinex-like operators achieving the best trade-off between power consumption, flexibility, and visual quality.
Giovanni RamponiEmail:

Sergio Saponara   is a Research Scientist and Assistant Professor at the University of Pisa. He was born in Bari, Italy, in 1975. He received the Electronic Engineering degree cum laude and the Ph.D. in Information Engineering, both from Pisa University, in 1999 and 2003, respectively. Since 2001 he collaborates with Consorzio Pisa Ricerche, Italy and in 2002 he was with IMEC, Belgium as Marie Curie research fellow. His research and teaching interests include electronic circuits and systems for multimedia, telecom and automation. He co-authored more than 40 papers including journals, conferences and patents. Luca Fanucci   is Associate Professor of Microelectronics at the University of Pisa. He was born in Montecatini, Italy, in 1965. He received the Doctor Engineer degree and the Ph.D. in Electronic Engineering from the University of Pisa in 1992 and 1996, respectively. From 1992 to 1996, he was with the European Space Agency's Research and Technology Center, Noordwijk, The Netherlands, and from 1996 to 2004 he was a Research Scientist of the Italian National Research Council in Pisa. His research interests include design technologies for integrated circuits and systems, with emphasis on system-level design, hardware/software co-design and low-power. He co-authored more than 100 journal/conference papers and holds more than 10 patents. Stefano Marsi   was born in Trieste, Italy, in 1963. He received the Doctor Engineer degree in Electronic Engineering (summa cum laude) in 1990 and the Ph.D. degree in 1994. Since 1995 he has held the position of researcher in the Department of Electronics at the University of Trieste where he is the teacher of courses in electronic field. His research interests include non-linear operators for image and video processing and their realization through application specific electronics circuits. He is author or co-author of more than 40 papers in international journals, proceedings of international conferences or contributions in books. Giovanni Ramponi   is Professor of Electronics at the Department of Electronics of the University of Trieste, Italy. His research interests include nonlinear digital signal processing, and the enhancement and feature extraction in images and image sequences. Prof. Ramponi has been an Associate Editor of the IEEE Signal Processing Letters and of the IEEE Transactions on Image Processing; presently is an AE of the SPIE Journal of Electronic Imaging. He has participated in various EU and National Research Projects. He is the co-inventor of various pending international patents and has published more than 140 papers in international journals and conference proceedings, and as book chapters. Prof. Ramponi contributes to several undergraduate and graduate courses on digital signal processing.   相似文献   

4.
This paper presents a dataflow functional computer (DFFC) developed at the Etablissement Technique Central de l'Armement (ETCA) and dedicated to real-time image processing. Two types of data-driven processing elements, dedicated respectively to low-level and mid-level processings are integrated in a regular 3D array. The design of the DFFC relies on a close integration of the dataflow-architecture principles and the functional programming concept. An image processing algorithm, expressed with a syntax similar to that of functional programming (FP) is first converted into a dataflow graph. The nodes of this graph are real-time operators that can be implemented on the physical processors of the dataflow machine. This dataflow graph is then mapped directly onto the processor array. The programming environment includes a complete compilation stream from the FP specification to hardware implementation, along with a global operator database. Apart from being a research tool for real-time image processing, the DFFC may also be used to perform the automatic synthesis of autonomous vision automata from a high-level functional specification. An experimental system, including 1024 lowlevel custom dataflow processors and 12 T800 transputers, was built and can perform up to 50 billion operations/s. Several image processing algorithms were implemented on this system and run in real-time at digital video speed.  相似文献   

5.
To meet both flexibility and performance requirements, particularly when implementing high-end real-time image/video processing algorithms, the paper proposes to combine the application specific instruction-set processor (ASIP) paradigm with the reconfigurable hardware one. As case studies, the design of partially reconfigurable ASIP (r-ASIP) architectures is presented for two classes of algorithms with widespread diffusion in image/video processing: motion estimation and retinex filtering. Design optimizations are addressed at both algorithmic and architectural levels. Special processor concepts used to trade-off performance versus flexibility and to enable new features of post-fabrication configurability are shown. Silicon implementation results are compared to known ASIC, DSP or reconfigurable designs; the proposed r-ASIPs stand for their better performance–flexibility figures in the respective algorithmic class.
Luca FanucciEmail:

Sergio Saponara   got the Laurea degree, cum laude, and the Ph.D. in Electronic Engineering from the University of Pisa in 1999 and 2003, respectively. In 2002, he was with IMEC, Leuven (B), as Marie Curie Research Fellow. Since 2001, he collaborates with Consorzio Pisa Ricerche-TEAM in Pisa. He is senior researcher at the University of Pisa in the field of VLSI circuits and systems for telecom, multimedia, space and automotive applications. He is co-author of more than 80 scientific publications. He holds the chair of electronic systems for automotive and automation at the Faculty of Engineering. Michele Casula   received the Laurea degree in Electronic Engineering from the University of Pisa in 2005. Since 2006, he is pursuing a Ph.D. degree in Information Engineering at the same university. His current interests involve VLSI circuits design, computer graphics, and Network-on-Chips. Luca Fanucci    received the Laurea degree and the Ph.D. degree in Electronic Engineering from the University of Pisa in 1992 and 1996, respectively. From 1992 to 1996, he was with ESA/ESTEC, Noordwijk (NL), as a research fellow. From 1996 to 2004, he was a senior researcher of the Italian National Research Council in Pisa. He is Professor of Microelectronics at the University of Pisa. His research interests include design methodologies and hardware/software architectures for integrated circuits and systems. Prof. Fanucci has co-authored more than 100 scientific publications and he holds more than ten patents.  相似文献   

6.
Technology evolution makes possible the integration of heterogeneous components as programmable elements (processors), hardware dedicated blocks, hierarchical memories and buses. Furthermore, an optimized reconfigurable logic core embedded within a System-on-Chip will associate the performances of dedicated architecture and the flexibility of programmable ones. In order to increase performances, some of the applications are carried out in hardware, using dynamically reconfigurable logic, rather than software, using programmable elements. This approach offers a suitable hardware support to design malleable systems able to adapt themselves to a specific application. This article makes a synthesis of the Ardoise project. The first objective of Ardoise project was to design and to produce a dynamically reconfigurable platform based on commercial FPGAs. The concept of dynamically reconfigurable architecture depends partially on new design methodologies elaboration as well as on the programming environment. The platform architecture was designed to be suitable for real-time image processing. The article outlines mainly the Ardoise tools aspect: development environment and real-time management of the hardware tasks. The proposed methodology is based on a dynamic management of tasks according to an application scenario written using C++ language.
Lounis KessalEmail:
  相似文献   

7.
Modern microscopic volumetric imaging processes lack capturing flexibility and are inconvenient to operate. Additionally, the quality of acquired data could not be assessed immediately during imaging due to the lack of a coherent real-time visualization system. Thus, to eliminate the requisition of close user supervision while providing real-time 3D visualization alongside imaging, we propose and describe an innovative approach to integrate imaging and visualization into a single pipeline called an online incrementally accumulated rendering system. This system is composed of an electronic controller for progressive acquisition, a memory allocator for memory isolation, an efficient memory organization scheme, a compositing scheme to render accumulated datasets, and accumulative frame buffers for displaying non-conflicting outputs. We implement this design using a laser scanning confocal endomicroscope, interfaced with an FPGA prototyping board through a custom hardware circuit. Empirical results from practical implementations deployed in a cancer research center are presented in this paper.  相似文献   

8.
This paper describes a network-based video capture and processing peripheral, called the Vidboard, for a distributed multimedia system centered around a 1-Gbit/s asynchronous transfer mode (ATM) network. The Vidboard is capable of generating full-motion video streams having a range of presentation (picture size, color space, etc.) and network (traffic, transport, etc.) characteristics. The board is also capable of decoupling video from the real-time constraints of the television world, which allows easier integration of video into the software environment of computer systems. A suite of ATM-based protocols has been developed for transmitting video from the Vidboard to a workstation, and a series of experiments are presented in which video is transmitted to a workstation for display.  相似文献   

9.
A polynomial approach to the representation of gray images for machine vision is described. An algebraic system is developed where a polynomial in two variables with real coefficients represents a gray image and it is shown that most of the standard image processing tasks like smoothing, edge detection, rotation and magnification can be done by operating certain polynomials called template polynomials. This method is also applied to connected component labelling, shape decomposition, template matching, and the skeletonization of a gray image without a priori thresholding. A technique is developed to decompose a template and do parallel processing.  相似文献   

10.
MACSYM is a hierarchical parallel processing system for pattern understanding applications. It features event-driven parallel processing for knowledge-based understanding of document images. The system is composed of a master processor, slave processors and a large shared memory, and is equipped with versatile communication facilities. The parallel processing software system M.UM has been developed on MACSYM. It supplies a parallel processing language MacC, an extended version of C, and supports the programming for document image understanding. The Japanese newspaper layout understanding system EXPRESS is being developed on MACSYM. It analyzes a newspaper image and extracts articles in a few seconds.  相似文献   

11.
This paper presents the structure and design criteria of a neural network-based multimedia information processing and analysis system (MIPAS) which can be used to deal with more-complicated intelligence issues. According to the structure and design criteria, a software environment (SEMIPAS), which supports the implementation of multimedia information (image + speech, image + characters, speech + characters, image + speech + characters) processing and analysis applications, is implemented and introduced. Under this software environment, a multimedia information processing and analysis system called “To Know the World” is constructed. Experiments show that the multimedia information processing and analysis is much more powerful and effective than single-medium information processing and analysis.  相似文献   

12.
发动机ECU标定系统需要标定人员根据实时工况数据来即时调整ECU的控制策略。即时显示发动机运行状态,同时存储实时数据对于标定工作意义重大。提出一种发动机ECU标定系统结构实现方法,实现工况数据的实时采集与标定数据的在线标定。设计一种改进的行程编码算法对数据进行无损压缩,便于数据的传输、存储、查询;利用数据缓存队列、优化线程调度策略,将任务分配到不同处理器上运行,保证系统的实时响应与数据处理效率。在发动机ECU标定系统的应用中表明该方法满足了标定系统对实时性、准确性、高效性的要求。  相似文献   

13.
传统的并行处理控制系统在处理存储器中易失性用户大数据时,对CPU的利用率很低,导致处理控制工作精密度差。为了解决此问题,设计了一种新的大数据并行处理控制系统,分别对系统的硬件和软件进行设计,分析了控制系统中各组件的结构关系,重点设计了系统总线、中央处理器;软件部分分为打开文件、更新文件、监测运行、数据连接四步。为了检测系统的可行性,与传统并行处理控制系统进行实验对比,结果显示,设计的并行处理控制系统能够充足的利用系统CPU,精确地处理存储器中易失性用户大数据。该系统具有超强的工作能力,值得推广使用。  相似文献   

14.
视频设备被广泛应用于公共区域、智能交通和工业生产等许多领域,其产生的视频数据具有体量巨大、速度极快、价值稀疏和完全非结构化等大数据典型特征。为了进一步提高视频大数据的处理性能,提出了一种基于Spark Streaming的视频大数据并行处理方法,设计了基于Spark Streaming的视频大数据并行处理框架,针对帧间无关分析算法和帧间相关分析算法分别给出了并行化策略,前者利用数据并行机制将去冗余后的视频帧映射到不同节点并行处理,后者利用流水线并行机制将分析算法的各个算子根据依赖关系映射到不同节点并行处理;结合实际应用对并行处理框架和并行化策略进行了评价,设计了电梯乘客数并行检测算法和电梯门异常并行检测算法,当节点数增加到16个时,电梯乘客数检测算法的性能加速比为615%,电梯门异常检测的性能加速比为253%。  相似文献   

15.
16.
Future factories will feature strong integration of physical machines and cyber-enabled software, working seamlessly to improve manufacturing production efficiency. In these digitally enabled and network connected factories, each physical machine on the shop floor can have its ‘virtual twin’ available in cyberspace. This ‘virtual twin’ is populated with data streaming in from the physical machines to represent a near real-time as-is state of the machine in cyberspace. This results in the virtualization of a machine resource to external factory manufacturing systems. This paper describes how streaming data can be stored in a scalable and flexible document schema based database such as MongoDB, a data store that makes up the virtual twin system. We present an architecture, which allows third-party integration of software apps to interface with the virtual manufacturing machines. We evaluate our database schema against query statements and provide examples of how third-party apps can interface with manufacturing machines using the VMM middleware. Finally, we discuss an operating system architecture for VMMs across the manufacturing cyberspace, which necessitates command and control of various virtualized manufacturing machines, opening new possibilities in cyber-physical systems in manufacturing.  相似文献   

17.
We present a framework for massively parallel climate impact simulations: the parallel System for Integrating Impact Models and Sectors (pSIMS). This framework comprises a) tools for ingesting and converting large amounts of data to a versatile datatype based on a common geospatial grid; b) tools for translating this datatype into custom formats for site-based models; c) a scalable parallel framework for performing large ensemble simulations, using any one of a number of different impacts models, on clusters, supercomputers, distributed grids, or clouds; d) tools and data standards for reformatting outputs to common datatypes for analysis and visualization; and e) methodologies for aggregating these datatypes to arbitrary spatial scales such as administrative and environmental demarcations. By automating many time-consuming and error-prone aspects of large-scale climate impacts studies, pSIMS accelerates computational research, encourages model intercomparison, and enhances reproducibility of simulation results. We present the pSIMS design and use example assessments to demonstrate its multi-model, multi-scale, and multi-sector versatility.  相似文献   

18.
Pressure mapping smart textile is a new type of sensing modality that transforms the pressure distribution over surfaces into digital ”image” and ”video”, that has rich application scenarios in Human Activity Recognition (HAR), because all human activities are linked with force change over certain surfaces. To speed up its application exploration, we propose a toolkit named LwTool for the data processing, including: (a) a feature library, including 1830 ready-to-use temporal and spatial features, (b) a hierarchical feature selection framework that automatically picks out the best features for a new application from the feature library. As real-time processing capability is important for instant user feedback, we emphasize not only on good recognition result but also on reducing time cost when selecting features. Our library and algorithms are validated on Smart-Toy and Smart-Bedsheet applications, an 89.7% accuracy for Smart-Toy and an 83.8% accuracy for Smart-Bedsheet can be achieved (10-fold cross-validation) using our feature library. Adopting the feature selection algorithm, the processing speed is increased by more than 3 times while maintaining high accuracy for both two applications. We believe our method could be a general and powerful toolkit in building real-time recognition software systems for pressure mapping smart textile.  相似文献   

19.
Plagiarism refers to the act of presenting external words, thoughts, or ideas as one’s own, without providing references to the sources from which they were taken. The exponential growth of different digital document sources available on the Web has facilitated the spread of this practice, making the accurate detection of it a crucial task for educational institutions. In this article, we present DOCODE 3.0, a Web system for educational institutions that performs automatic analysis of large quantities of digital documents in relation to their degree of originality. Since plagiarism is a complex problem, frequently tackled at different levels, our system applies algorithms in order to perform an information fusion process from multi data source to all these levels. These algorithms have been successfully tested in the scientific community in solving tasks like the identification of plagiarized passages and the retrieval of source candidates from the Web, among other multi data sources as digital libraries, and have proven to be very effective. We integrate these algorithms into a multi-tier, robust and scalable JEE architecture, allowing many different types of clients with different requirements to consume our services. For users, DOCODE produces a number of visualizations and reports from the different outputs to let teachers and professors gain insights on the originality of the documents they review, allowing them to discover, understand and handle possible plagiarism cases and making it easier and much faster to analyze a vast number of documents. Our experience here is so far focused on the Chilean situation and the Spanish language, offering solutions to Chilean educational institutions in any of their preferred Virtual Learning Environments. However, DOCODE can easily be adapted to increase language coverage.  相似文献   

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