A systematic dry etching process for profile control of quantum dots and nanoconstrictions

In essence, quantum dot dimensions and others can be laterally and vertically defined by using either bottom up or top down methods respectively. In fabrication that uses top down method, etch process hold a chief role. Varieties of etch times and oxygen flow rates in ranges 75–88 s and 20–50 sccm, respectively, were devised to fabricate optimum dimension of nanostructure. As a result, as etch time increased, lateral etch rate of silicon quantum dot, source and drain and also the nanostructure etch depth increased. However, high roughness of etched silicon surface profile led to concave surfaces of source and drain. In this research, no significant relation between quantum dot diameters and oxygen flow rates was found. There was a reflection point, fixed data dot of 26 sccm, of the decreasing and increasing lines of relation between nanostructure depth of etched silicon and nanostructure gradient with the O₂ flow rate.     

Optical diagnostics of plasma chemistries and chamber conditions in gate oxide stack etch

Various kinds of plasma chemistries were used in the study of polysilicon gate stack etch. Different degrees of gate oxide surface roughness were observed. Stable gate oxide thickness and smooth surface were found when using fluorine-based plasma chemistries. In contrast, non-fluorine-based chemistry tends to give uneven gate oxide thickness and rough surface. The stability of the gate oxide thickness can be controlled by chamber seasoning when using non-fluorine-based chemistry. It is also noticed that fluorine-based chemistries always result in thicker remaining gate oxide than the one without fluorine. The type of wafer used for seasoning can also have influence on chamber condition and subsequently the etch rates and gate oxide thickness. From the trends of emission intensity of Si, it is believed that etch byproducts as well as chamber wall polymer have potential impacts on the observed variation of gate oxide surface roughness, thickness, and etch rates.     

Characteristics of germanium dry etching using inductively coupled SF6 plasma

Inductively coupled SF₆ plasma etching of germanium (Ge) was investigated at different inductively coupled plasma (ICP) power levels, the SF₆ flow rate, and the working pressure. The etch rate of Ge increases from 1007 to 2447 nm/min as the SF₆ flow rate increases from 10 to 60 sccm. Also, the etch rate of Ge increases from 265 to 1007 nm/min as the ICP power level increases from 100 to 400 W whereas the etch rate of Ge decreases from 552 to 295 nm/min as the working pressure increases from 5 to 20 mTorr. The etch profile is isotropic. As SF₆ flow, ICP power and working pressure decrease the surface roughness decreases. Optical emission spectroscopy was used to examine the gas phase species in the plasma, and emission from excited atomic S and F has been identified. Composition of the surface due to SF₆ plasmas has been obtained using X-ray photoelectron spectroscopy. Reaction layers on germanium due to inductively coupled SF₆ plasma etching are found to be a thin, layer with of G–-S, Ge–F and Ge–O bonded species.     

Influence of processing and annealing steps on electrical properties of InAlN/GaN high electron mobility transistor with Al2O3 gate insulation and passivation

We report on preparation and electrical characterization of InAlN/AlN/GaN metal–oxide–semiconductor high electron mobility transistors (MOS HEMTs) with Al₂O₃ gate insulation and surface passivation. About 12 nm thin high-κ dielectric film was deposited by MOCVD. Before and after the dielectric deposition, the samples were treated by different processing steps. We monitored and analyzed the steps by sequential device testing. It was found that both intentional (ex situ) and unintentional (in situ before Al₂O₃ growth) InAlN surface oxidation increases the channel sheet resistance and causes a current collapse. Post deposition annealing decreases the sheet resistance of the MOS HEMT devices and effectively suppresses the current collapse. Transistors dimensions were source-to-drain distance 8 μm and gate width 2 μm. A maximum transconductance of 110 mS/mm, a drain current of ～0.6 A/mm (V_GS = 1 V) and a gate leakage current reduction from 4 to 6 orders of magnitude compared to Schottky barrier (SB) HEMTs was achieved for MOS HEMT with 1 h annealing at 700 °C in forming gas ambient. Moreover, InAlN/GaN MOS HEMTs with deposited Al₂O₃ dielectric film were found highly thermally stable by resisting 5 h 700 °C annealing.     

The fabrication and dry etching of poly-Si/TaN/Mo gate stack in the metal inserted poly-Si stack structure

The Mo-based metal inserted poly-Si stack (MIPS) structure is an appropriate choice for metal gate and high-k integration in sub-45 nm gate-first CMOS device. A novel metal nitride layer of TaN or AlN with high thermal stability has been introduced between Mo and poly-Si as a barrier material to avoid any reaction of Mo during poly-Si deposition. After Mo-based MIPS structure is successfully prepared, dry etching of poly-Si/TaN/Mo gate stack is studied in detail. The three-step plasma etching using the Cl₂/HBr chemistry without soft landing step has been developed to attain a vertical poly-Si profile and a reliable etch-stop on the TaN/Mo metal gate. For the etching of TaN/Mo gate stack, two methods using BCl₃/Cl₂/O₂/Ar plasma are presented to get both vertical profile and smooth etched surface, and they are critical to get high selectivity to high-k dielectric and Si substrate. In addition, adding a little SF₆ to the BCl₃/O₂/Ar plasma under the optimized conditions is also found to be effective to smoothly etch the TaN/Mo gate stack with vertical profile.     

Positive bias temperature instabilities on sub-nanometer EOT FinFETs

PBTI degradation on FinFETs with HfO₂/TiN gate stack (EOT < 1 nm) is studied. Thinner TiN layer decreases interfacial oxide thickness, and reduces PBTI lifetime. This behavior is consistent with the results in planar devices. Corner rounding effect on PBTI is also analyzed. Finally, charge pumping measurements on devices with several fin widths devices apparently show a higher density of defects in the top-wall high-κ oxide than in the sidewall of the fin. This could explain more severe PBTI degradation.     

On the current conduction mechanisms of CeO2/La2O3 stacked gate dielectric

It was found that the electrical properties of CeO₂/La₂O₃ stack are much better than a single layer La₂O₃ film. A thin CeO₂ capping layer can effectively suppress the oxygen vacancy formation in the La₂O₃ film. This work further investigates the current conduction mechanisms of the CeO₂ (1 nm thick)/La₂O₃ (4 nm thick) stack. Results show that this thin stacked dielectric film still has a large leakage current density; the typical 1−V leakage can exceed 1 mA/cm² at room temperature. The large leakage current should be due to both the oxide defect centers as well as the film structure. Results show that at low electric field (<0.2 MV/cm), the thermionic emission induced current conduction in this stacked structure is quite pronounced as a result of interface barrier lowering due to the capping CeO₂ film which has a higher k value than that of the La₂O₃ film. At higher electric fields, the current conduction is governed by Poole–Frenkel (PF) emission via defect centers with an effective energy level of 0.119 eV. The temperature dependent current–voltage characteristics further indicate that the dielectric defects may be regenerated as a result of the change of the thermal equilibrium of the redox reaction in CeO₂ film at high temperature and the drift of oxygen under the applied electric field.     

Compound semiconductor MOSFETs

Enhancement mode, high electron mobility MOSFET devices have been fabricated using an oxide high-κ gate dielectric stack developed using molecular beam epitaxy. A template layer of Ga₂O₃, initially deposited on the surface of the III-V device unpins the GaAs Fermi level while a (Gd_xGa_1−x)₂O₃ bulk ternary layer forms the highly resistive layer to reduce leakage current through the dielectric stack. A midgap interface state density of ∼2 × 10¹¹ cm⁻² eV⁻¹ and a dielectric constant of 20 are determined using electrical measurements.. N-channel MOSFETs with a gate length of 1 μm and a source-drain spacing of 3 μm show a threshold voltage, saturation current and transconductance of 0.11 V, 380 mA/mm and 250 mS/mm, respectively.     

Comprehensive effects of strained Ge1−xSnx and device layout arrangement on a nano-scale Ge-based PMOSFET with a short channel

Layout patterns, including salient gate width and dummy active diffusion region (dummy OD), significantly influence the carrier mobility gain of nano scale devices. Germanium (Ge)-based devices with Ge–tin (GeSn) alloy embedded in the source/drain (S/D) regions have been regarded a promising candidate for higher channel mobility. Second-order piezoresistance coefficients were used to estimate the carrier mobility gain within the desired Ge-based device channel. A 20 nm Ge-based p-type metal oxide semiconductor field effect transistor with 100 nm gate width and 100 nm dummy OD width was selected to explore the layout effect of the short channel device. The device consisted of S/D region Ge_1−xSn_x alloy, compressive-stressed contact etch stop layer, and deposited shallow trench isolation with different process-induced stress magnitudes. Maximum carrier mobility gain of 93.65% was obtained when a 10 nm narrow distance between OD and dummy OD was achieved.     

Challenges and performance limitations of high-k and oxynitride gate dielectrics for 90/65 nm CMOS technology

For low power applications, the increase of gate leakage current, caused by direct tunneling in ultra-thin oxide films, is the crucial factor eliminating conventional SiO₂-based gate dielectrics in sub-90 nm CMOS technology development. Recently, promising performance has been demonstrated for poly-Si/high-k and poly-Si/SiON gate stacks in addressing gate leakage requirements for low power applications. However, the use of poly-Si gate electrodes on high-k created additional issues such as channel mobility and reliability degradations, as well as Fermi level pinning of the effective gate work function. Therefore, oxynitride gate dielectrics are being proposed as an intermediate solution toward the sub-65/45 nm nodes. Apparently, an enhanced SiON gate dielectric stack was developed and reported to achieve high dielectric constant and good interfacial properties. The purpose of this paper is to provide a comprehensive review some of the device performance and limitation that high-k and oxynitride as dielectric materials are facing for sub-65/45 nm node.     

Influence of the polysilicon doping on the electrical quality of thin oxides: a confrontation between vertical and horizontal furnaces

In this work, the influence of polysilicon doping on thin oxides (thickness equal or below 10 nm) quality and reliability (thickness equal or below 10 nm) in MOS capacitors with polysilicon gate is evaluated. By observing the polysilicon deposed in vertical and horizontal furnaces, a higher degradation in the oxide–silicon interface at high doping concentration has been found. In the case of vertical furnaces, a more evident charge trapping in the constant current stress (CCS) V(t) curves and Qbd (ERCS) degradation have also been noticed. Resistivity measurements at different concentrations show a saturation effect just in correspondence of the oxide degradation. From a morphological point of view, the poly deposited in vertical furnaces consists of grains which are larger than the ones found in horizontal furnace polysilicon and contains lower microdefectivity. Starting from these observations a model explaining the polysilicon morphology role in the oxide reliability can be proposed. According to it, the degradation of the interface is caused by the phosphorus coming from the “in situ” doped polysilicon. The hypothesis is that, at high concentrations and in presence of very large polysilicon grains, phosphorous cannot segregate at the interfaces among the polysilicon grains and, moving through the thin oxide, damages the silicon interface. This model has been confirmed by electrical, AFM and TEM analysis and all the collected data have been related to the finished devices performances (yield and reliability of CMOS flash memories, 0.25 μm technology and below).     

Electrical characteristics of MOSFETs with La2O3/Y2O3 gate stack

A metal oxide semiconductor field effect transistor (MOSFET) with ultra-thin La₂O₃/Y₂O₃ high-k gate dielectric was fabricated. The effects of thermal treatment process on both physical and electrical characteristics of the La₂O₃/Y₂O₃ stack were studied using XPS and electrical measurements. It was observed that the effective mobility of the fabricated MOSFETs with La₂O₃/Y₂O₃ gate stack was not degraded with increasing the annealing temperatures up to 600 °C. X-ray photoelectron spectroscopy (XPS) analysis also revealed that the formation of SiO₂ and silicate layer at the interface was suppressed in La₂O₃/Y₂O₃ stack compare to that of in La₂O₃ single layer. Obtained results suggesting that La₂O₃/Y₂O₃ gate stack is one of the promising candidates for high-k gate insulator to be used in the future metal oxide field effect transistors.     

Carbon etching with a high density plasma etcher

Generating suitable passivation on the carbon sidewall is a major challenge facing carbon etching especially for films thicker than 500 nm. Patterning carbon hard mask stacks for sub 90 nm technologies was tested for three different O₂-based chemistries using an inductively coupled plasma etch tool. The results show that the etched carbon profiles are highly dependant upon the O₂ flow and the total time of the etch process. Extended over etch times quite often initiates lateral etching and rapid loss of profile and critical dimension. An HBr/O₂/N₂ chemistry has been shown to provide the best options for profile control and more resistance to profile loss during extended over etching than the other chemistries which were tested during this study.     

Mechanism of positive charge generation in the bulk of HfAlO/SiO2 stack

We have investigated electrical stress-induced positive charge buildup in a hafnium aluminate (HfAlO)/silicon dioxide (SiO₂) dielectric stack (equivalent oxide thickness = 2.63 nm) in metal–oxide–semiconductor (MOS) capacitor structures with negative bias on the TaN gate. Various mechanisms of positive charge generation in the dielectric have been theoretically studied. Although, anode hole injection (AHI) and valence band hole tunneling are energetically favorable in the stress voltage range studied, the measurement results can be best explained by the dispersive proton transport model.     

Scaling the MOSFET gate dielectric: From high-k to higher-k? (Invited Paper)

We discuss options for metal–oxide-semiconductor field-effect transistor (MOSFET) gate stack scaling with thin titanium nitride metal gate electrodes and high-permittivity (‘high-k’) gate dielectrics, aimed at gate-first integration schemes. Both options are based on further increasing permittivity of the dielectric stack. First, we show that hafnium-based stacks such as TiN/HfO₂ can be scaled to capacitance equivalent thickness in inversion (T_inv) of 10 Å and equivalent oxide thickness (EOT) of 6 Å by using silicon nitride instead of silicon oxide as a high-k/channel interfacial layer. This is based on the higher dielectric constant of Si₃N₄ and on its resistance to oxidation. Although the nitrogen introduces positive fixed charges, carrier mobility is not degraded. Secondly, we investigate whether Ti-based ‘higher-k’ dielectrics have the potential to ultimately replace Hf. We discuss oxygen loss from TiO₂ as a main challenge, and identify two migration pathways for such oxygen atoms: In addition to well-known down-diffusion and channel Si oxidation, we have newly observed oxygen up-diffusion through the TiN metal gate, forming SiO₂ at the poly-Si contact. We further address the performance of Si₃N₄ and HfO₂ as oxygen barrier layers.     

Interface studies of ALD-grown metal oxide insulators on Ge and III–V semiconductors (Invited Paper)

Atomic layer deposited (ALD) HfO₂/GeO_xN_y/Ge(1 0 0) and Al₂O₃/In_0.53Ga_0.47As(1 0 0) ? 4 × 2 gate stacks were analyzed both by MOS capacitor electrical characterization and by advanced physical characterization to correlate the presence of electrically-active defects with chemical bonding across the insulator/channel interface. By controlled in situ plasma nitridation of Ge and post-ALD annealing, the capacitance-derived equivalent oxide thickness was reduced to 1.3 nm for 5 nm HfO₂ layers, and mid-gap density of interface states, D_it = 3 × 10¹¹ cm^?2 eV^?1, was obtained. In contrast to the Ge case, where an engineered interface layer greatly improves electrical characteristics, we show that ALD-Al₂O₃ deposited on the In_0.53Ga_0.47As (1 0 0) ? 4 × 2 surface after in situ thermal desorption in the ALD chamber of a protective As cap results in an atomically-abrupt and unpinned interface. By avoiding subcutaneous oxidation of the InGaAs channel during Al₂O₃ deposition, a relatively passive gate oxide/III–V interface is formed.     

Impact of gate poly doping and oxide thickness on the N- and PBTI in MOSFETs

We study n- and pMOS devices with 3.2–30 nm thick SiON or SiO₂ gate dielectrics and n⁺⁺ or p⁺⁺ doped polysilicon gates to identify the type and energetic location of defects created through bias temperature stress. The results clearly indicate a dependence of the type of BTS induced defects on the stress polarity and the gate poly doping. If holes are provided from the p⁺⁺ poly gate and the gate dielectric is sufficiently thin, NBTI-type donor-like defects may occur even under positive bias stress conditions. For devices with sufficiently thick dielectrics or n⁺⁺ poly gated devices, holes are absent during PBTI stress and acceptor-like defects are created.     

Growth temperature dependence of epitaxial Gd2O3 films on Si(1 1 1)

This article reports on the epitaxy of crystalline high κ oxide Gd₂O₃ layers on Si(1 1 1) for CMOS gate application. Epitaxial Gd₂O₃ thin films have been grown by Molecular Beam Epitaxy (MBE) on Si(1 1 1) substrates between 650 and 750 °C. The structural and electrical properties were investigated depending on the growth temperature. The C–V measurements reveal that equivalent oxide thickness (EOT) equals 0.7 nm for the sample deposited at the optimal temperature of 700 °C with a relatively low leakage current of 3.6 × 10^?2 A/cm² at |V_g ? V_FB| = 1 V.     

Analysis of nanometer-scale InGaAs/InAs/InGaAs composite channel MOSFETs using high-K dielectrics for high speed applications

The outstanding electron transport properties of InGaAs and InAs semiconductor materials, makes them attractive candidates for future nano-scale CMOS. In this paper, the ON state and OFF state performance of 30 nm gate length InGaAs/InAs/InGaAs buried composite channel MOSFETs using various high-K dielectric materials is analyzed using Synopsys TCAD tool. The device features a composite channel to enhance the mobility, an InP spacer layer to minimize the defect density and a heavily doped multilayer cap. The simulation results show that MOSFETs with Al₂O₃/ZrO₂ bilayer gate oxide exhibits higher gm/I_D ratio and lower sub threshold swing than with the other dielectric materials. The measured values of threshold voltage (V_T), on resistance (R_ON) and DIBL for Lg = 30 nm In_0.53Ga_0.47As/InAs/In_0.53Ga_0.47As composite channel MOSFET having Al₂O₃/ZrO₂ (EOT = 1.2 nm) bilayer dielectric as gate oxide are 0.17 V, 290 Ω-µm, and 65 mV/V respectively. The device displays a transconductance of 2 mS/µm.     

Development of highly conducting n-type micro-crystalline silicon oxide thin film and its application in high efficiency amorphous silicon solar cell

Wide band gap and highly conducting n-type nano-crystalline silicon film can have multiple roles in thin film solar cell. We prepared phosphorus doped micro-crystalline silicon oxide films (n-μc-SiO:H) of varying crystalline volume fraction (X_c) and applied some of the selected films in device fabrication, so that it plays the roles of n-layer and back reflector in p-i-n type solar cells. It is generally understood that a higher hydrogen dilution is needed to prepare micro-crystalline silicon, but in case of the n-μc-SiO:H an optimized hydrogen dilution was found suitable for higher X_c. Observed X_c of these films mostly decreased with increased plasma power (for pressure<2.0 Torr), increased gas pressure, flow rate of oxygen source gas and flow rates of PH₃>0.08 sccm. In order to determine deposition conditions for optimized opto-electronic and structural characteristics of the n-μc-SiO:H film, the gas flow rates, plasma power, deposition pressure and substrate temperature were varied. In these films, the X_c, dark conductivity (σ_d) and activation energy (E_a) remained within the range of 0–50%, 3.5×10⁻¹⁰ S/cm to 9.1 S/cm and 0.71 eV to 0.02 eV, respectively. Low power (30 W) and optimized flow rates of H₂ (500 sccm), CO₂ (5 sccm), PH₃ (0.08 sccm) showed the best properties of the n-μc-SiO:H layers and an improved performance of a solar cell. The photovoltaic parameters of one of the cells were as follows, open circuit voltage (V_oc), short circuit current density (J_sc), fill-factor (FF), and photovoltaic conversion efficiency (η) were 950 mV, 15 mA/cm², 64.5% and 9.2% respectively.