A recursive method for synthesizing quantum/reversible quaternary parallel adder/subtractor with look-ahead carry

Multiple-valued quantum logic circuits are a promising choice for future quantum computing technology since they have several advantages over binary quantum logic circuits. Adder/subtractor is the major component of the ALU of a computer and is also used in quantum oracles. In this paper, we propose a recursive method of hand synthesis of reversible quaternary full-adder circuit using macro-level quaternary controlled gates built on the top of ion-trap realizable 1-qudit quantum gates and 2-qudit Muthukrishnan–Stroud quantum gates. Based on this quaternary full-adder circuit we propose a reversible circuit realizing quaternary parallel adder/subtractor with look-ahead carry. We also show the way of adapting the quaternary parallel adder/subtractor circuit to an encoded binary parallel adder/subtractor circuit by grouping two qubits together into quaternary qudit values.     

Towards quantum reversible ternary coded decimal adder

Quantum ternary logic is a promising emerging technology for the future quantum computing. Ternary reversible logic circuit design has potential advantages over the binary ones like its logarithmic reduction in the number of qudits. In reversible logic all computations are done in an invertible fashion. In this paper, we propose a new quantum reversible ternary half adder with quantum cost of only 7 and a new quantum ternary full adder with a quantum cost of only 14. We termed it QTFA. Then we propose 3-qutrit parallel adders. Two different structures are suggested: with and without input carry. Next, we propose quantum ternary coded decimal (TCD) detector circuits. Two different approaches are investigated: based on invalid numbers and based on valid numbers. Finally, we propose the quantum realization of TCD adder circuits. Also here, two approaches are discussed. Overall, the proposed reversible ternary full adder is the best between its counterparts comparing the figures of merits. The proposed 3-qutrit parallel adders are compared with the existing designs and the improvements are reported. On the other hand, this paper suggested the quantum reversible TCD adder designs for the first time. All the proposed designs are realized using macro-level ternary Toffoli gates which are built on the top of the ion-trap realizable ternary 1-qutrit gates and 2-qutrit Muthukrishnan–Stroud gates.     

Designing new ternary reversible subtractor circuits

The reducing of the width of quantum reversible circuits makes multiple-valued reversible logic a very promising research area. Ternary logic is one of the most popular types of multiple-valued reversible logic, along with the Subtractor, which is among the major components of the ALU of a classical computer and complex hardware. In this paper the authors will be presenting an improved design of a ternary reversible half subtractor circuit. The authors shall compare the improved design with the existing designs and shall highlight the improvements made after which the authors will propose a new ternary reversible full subtractor circuit. Ternary Shift gates and ternary Muthukrishnan–Stroud gates were used to build such newly designed complex circuits and it is believed that the proposed designs can be used in ternary quantum computers. The minimization of the number of constant inputs and garbage outputs, hardware complexity, quantum cost and delay time is an important issue in reversible logic design. In this study a significant improvement as compared to the existing designs has been achieved in as such that with the reduction in the number of ternary shift and Muthukrishnan-Stroud gates used the authors have produced ternary subtractor circuits.     

The quantum realization of Arnold and Fibonacci image scrambling

The quantum Fourier transform, the quantum wavelet transform, etc., have been shown to be a powerful tool in developing quantum algorithms. However, in classical computing, there is another kind of transforms, image scrambling, which are as useful as Fourier transform, wavelet transform, etc. The main aim of image scrambling, which is generally used as the preprocessing or postprocessing in the confidentiality storage and transmission, and image information hiding, was to transform a meaningful image into a meaningless or disordered image in order to enhance the image security. In classical image processing, Arnold and Fibonacci image scrambling are often used. In order to realize these two image scrambling in quantum computers, this paper proposes the scrambling quantum circuits based on the flexible representation for quantum images. The circuits take advantage of the plain adder and adder modulo $N$ to factor the classical transformations into basic unitary operators such as Control-NOT gates and Toffoli gates. Theoretical analysis indicates that the network complexity grows linearly with the size of the number to be operated.     

Synthesis of quaternary reversible/quantum comparators

Multiple-valued quantum circuits are promising choices for future quantum computing technology, since they have several advantages over binary quantum circuits. Quaternary logic has the advantage that classical binary functions can be very easily represented as quaternary functions by grouping two bits together into quaternary values. Grover’s quantum search algorithm requires a sub-circuit called oracle, which takes a set of inputs and gives an output stating whether a given search condition is satisfied or not. Equality, less-than, and greater-than comparisons are widely used as search conditions. In this paper, we show synthesis of quaternary equality, less-than, and greater-than comparators on the top of ion-trap realizable 1-qudit gates and 2-qudit Muthukrishnan–Stroud gates.     

量子计算模拟及优化方法综述

在处理某些大规模并行问题时,量子计算因量子位独特的叠加态和纠缠态特性,相比经典计算机在并行处理方面具有更明显的优势。现阶段,物理量子比特计算机受限于可扩展性、相干时间和量子门操作精度,在经典计算机上开展量子计算模拟成为研究量子优越性和量子算法的有效途径。然而,随着量子比特数的增加,模拟所需的计算机资源呈指数增长。因此,研究大规模量子计算模拟在保证计算准确度、精度及效率的情况下减少模拟所需资源具有重要意义。从量子比特、量子门、量子线路、量子操作系统等方面展开,阐述量子计算的基本原理和背景知识。同时总结基于经典计算机的量子计算模拟基本方法,分析不同方法的设计思路和优缺点,列举目前常见的量子计算模拟器。在此基础上,针对量子计算模拟的通信开销问题,从节点拆分和通信优化2个方面出发,讨论基于超级计算机集群的量子计算模拟优化方法。     

A novel design of 8-bit adder/subtractor by quantum-dot cellular automata

Application of quantum-dot is a promising technology for implementing digital systems at nano-scale. QCA supports the new devices with nanotechnology architecture. This technique works based on electron interactions inside quantum-dots leading to emergence of quantum features and decreasing the problem of future integrated circuits in terms of size. In this paper, we will successfully design, implement and simulate a new full adder based on QCA with the minimum delay, area and complexities. Also, new XOR gates will be presented which are used in 8-bit controllable inverter in QCA. Furthermore, a new 8-bit full adder is designed based on the majority gate in the QCA, with the minimum number of cells and area which combines both designs to implement an 8-bit adder/subtractor in the QCA. This 8-bit adder/subtractor circuit has the minimum delay and complexity. Being potentially pipeline, the QCA technology calculates the maximum operating speed.     

Novel designs of nanometric parity preserving reversible compressor

Reversible logic is a new field of study that has applications in optical information processing, low power CMOS design, DNA computing, bioinformatics, and nanotechnology. Low power consumption is a basic issue in VLSI circuits today. To prevent the distribution of errors in the quantum circuit, the reversible logic gates must be converted into fault-tolerant quantum operations. Parity preserving is used to realize fault tolerant in this circuits. This paper proposes a new parity preserving reversible gate. We named it NPPG gate. The most significant aspect of the NPPG gate is that it can be used to produce parity preserving reversible full adder circuit. The proposed parity preserving reversible full adder using NPPG gate is more efficient than the existing designs in term of quantum cost and it is optimized in terms of number of constant inputs and garbage outputs. Compressors are of importance in VLSI and digital signal processing applications. Effective VLSI compressors reduce the impact of carry propagation of arithmetic operations. They are built from the full adder blocks. We also proposed three new approaches of parity preservation reversible 4:2 compressor circuits. The third design is better than the previous two in terms of evaluation parameters. The important contributions have been made in the literature toward the design of reversible 4:2 compressor circuits; however, there are not efforts toward the design of parity preservation reversible 4:2 compressor circuits. All the scales are in the nanometric criteria.     

Molecular solutions of the RSA public-key cryptosystem on a DNA-based computer

The RSA public-key cryptosystem is an algorithm that converts a plain-text to its corresponding cipher-text, and then converts the cipher-text back into its corresponding plain-text. In this article, we propose five DNA-based algorithms??parallel adder, parallel subtractor, parallel multiplier, parallel comparator, and parallel modular arithmetic??that construct molecular solutions for any (plain-text, cipher-text) pair for the RSA public-key cryptosystem. Furthermore, we demonstrate that an eavesdropper can decode an encrypted message overheard with the linear steps in the size of the encrypted message overheard.     

Design of low power multi-ternary digit multiplier in CNTFET technology

This work introduces the method to implement energy efficient designs of arithmetic units such as a ternary full adder, ripple carry adder, single-trit multiplier and multi-trit multiplier using carbon nanotube field effect transistors (CNTFETs). A CNTFET unique feature of the threshold voltage variation by changing the CNT diameter, make it a suitable alternative for being employed in ternary logic designs. In designing the proposed circuits, decoder circuit functionality is realized by various threshold detector circuits tuned to a specific logical threshold voltage value. The multiplier circuit is designed by combing the capacitive logic and the minority function. In order to test the practicability of proposed circuits in cascaded circuits, multi-digit adder and multiplier circuits are constructed. The proposed multi-digit multiplier structure is based on classical Wallace multiplier and includes various optimized versions of adder and multiplier circuits. Extensive simulation has been done to examine the competency of proposed designs under different test conditions. The design of 3-trit multiplier formed by combing the proposed adder and multiplier circuits shows 16 times reduction in power consumption as well as energy consumption in comparison to previous multiplier design.     

Design of BCD adder with five input majority gate for QCA

In the digital world BCD numbers play a pivotal role in constituting decimal numbers. New different technologies are emerging in order to obtain low area/power/delay factors to replace the CMOS technology. One such technology is quantum cellular automata (QCA) realization, through which many arithmetic circuits can be designed. This paper deals with the implementation of BCD adder with 5 input majority gates for QCA. The 3 input majority gate and an inverter are basic elements of QCA. In this project amalgamation of majority gates with 3 and 5 inputs are used instead of implementing the entire circuit using 3 input majority gate in the BCD i.e. mainly comprised by partly consumed gates and entirely consumed gates. The proposed is designed and functional verification is done by Verilog HDL and Modelsim version 10.4a. The proposed design has been verified and the delay of existing and proposed design is analysed using Xilinx tool. The numbers of partly consumed and entirely consumed gates are less when compared to the existing method of implementation. The delay is reduced compared to the existing system which shows the improvement of 9.84%. The drawback of crossovers that leads the difficulty in implementation and reduces the efficiency of the circuit is reduced in the proposed implementation.     

经典逻辑门与量子逻辑门之比较

本文通过经典逻辑门与量子逻辑门之比较,论述了量子计算的特点、量子算法的巨大威力及量子逻辑门的实现问题。     

Design of reversible logic based full adder in current-mode logic circuits

Demand of Very Large Scale Integration (VLSI) circuits with very high speed and low power are increased due to communication system's transmission speed increase. During computation, heat is dissipated by a traditional binary logic or logic gates. There will be one or more input and only one output in irreversible gates. Input cannot be reconstructed using those outputs. In low power VLSI, reversible logic is commonly preferred in recent days. Information is not lost in reversible gates and back computation is possible in reversible circuits with reduced power dissipation. Reversible full adder circuits are implemented in the previous work to optimize the design and speed of the circuits. Reversible logic gates like TSG, Peres, Feynman, Toffoli, Fredkin are mostly used for designing reversible circuits. However it does not produced a satisfactory result in terms of static power dissipation. In this proposed research work, reversible logic is implemented in the full adder of MOS Current-Mode Logic (MCML) to achieve high speed circuit design with reduced power consumption. In VLSI circuits, reliable performance and high speed operation is exhibited by a MCML when compared with CMOS logic family. Area and better power consumption can be produced implementing reversible logic in full adder of MCML. Minimum garbage output and constant inputs are used in reversible full adder. The experimental results shows that the proposed designed circuit achieves better performance compared with the existing reversible logic circuits such as Feynman gate based FA, Peres gate based FA, TSG based FA in terms of average power, static power dissipation, static current and area.     

Linear nearest neighbor optimization in quantum circuits: a multiobjective perspective

Several current implementations of quantum circuits rely on the linear nearest neighbor restriction, which only allows interaction between adjacent qubits. Most methods that address the process of converting a generic circuit to an equivalent circuit which satisfies this restriction, minimize the number of additional SWAP gates required by this process. Moreover, most methods which address this problem are designed for 1D circuits. Considering the new and promising proposals for 2D quantum circuits, what we propose is a new perspective on this problem, namely that it can be seen as a multiobjective optimization problem. To test our hypothesis, we developed a multiobjective evolutionary algorithm that solves this problem by considering two objectives: minimizing the size of the 2D grid where the circuit is placed, and minimizing the number of additional SWAP gates. Of the methods designed for 2D circuits, only one considers different grid sizes which are much larger than strictly necessary. Consequently, our algorithm makes considerations which other methods do not make, since it naturally finds the grid which requires fewer SWAP gates for the circuit conversion, whether it is one-dimensional or two-dimensional. Our experimental results indicate that allowing a larger grid size results in fewer additional SWAP gates in about 73% of the tested circuits. Additionally, the average improvement we found when using larger grid sizes is about 30%, while the best improvement over using the smallest possible grid is 63.8%.     

Improved quantum ripple-carry addition circuit

A serious obstacle to large-scale quantum algorithms is the large number of elementary gates, such as the controlled-NOT gate or Toffoli gate. Herein, we present an improved linear-depth ripple-carry quantum addition circuit, which is an elementary circuit used for quantum computations. Compared with previous addition circuits costing at least two Toffoli gates for each bit of output, the proposed adder uses only a single Toffoli gate. Moreover, our circuit may be used to construct reversible circuits for modular multiplication, Cx mod M with x < M, arising as components of Shor’s algorithm. Our modular-multiplication circuits are simpler than previous constructions, and may be used as primitive circuits for quantum computations.     

Controlled gates for multi-level quantum computation

Multi-level (ML) quantum logic can potentially reduce the number of inputs/outputs or quantum cells in a quantum circuit which is a limitation in current quantum technology. In this paper we propose theorems about ML-quantum and reversible logic circuits. New efficient implementations for some basic controlled ML-quantum logic gates, such as three-qudit controlled NOT, Cycle, and Self Shift gates are proposed. We also propose lemmas about r-level quantum arrays and the number of required gates for an arbitrary n-qudit ML gate. An equivalent definition of quantum cost (QC) of binary quantum gates for ML-quantum gates is introduced and QC of controlled quantum gates is calculated.     

CMOS Design of Ternary Arithmetic Devices

This paper presents CMOS circuit designs of a ternary adder and a ternary multiplier,formulated using transmission function theory.Binary carry signals appearing in these designs allow conventional look-ahead carry techniques to be used.compared with previous similar designs,the circuits proposed in this paper have advantages such as low dissipation,low output impedance,and simplicity of construction.     

Harmony-search algorithm for 2D nearest neighbor quantum circuits realization

Motivated by its promising applications, quantum computing is an emerging area of research. This paper addresses the NP-complete problem of finding Nearest Neighbor (NN) realization of quantum circuits on a 2-Dimensional grid. In certain quantum technologies, only physically adjacent qubits are allowed to interact with each other hence the need for NN requirement. Circuits with distant qubits are made NN-compliant by introducing swap gates, hence increasing cost. In this work, we present a Harmony Search (HS) based intelligent metaheuristic algorithm to efficiently realize low cost NN circuits utilizing input line reordering. The distinct feature of the proposed technique is that initial qubits placement is found using HS based metaheuristic followed by an efficient, problem-specific local heuristic to perform swap gate insertion. The effectiveness of the proposed algorithm is demonstrated by comparing its performance to a number of recent published approaches. Solutions found by the proposed technique show reduction in the number of swaps needed in the range of 4% – 36% on average when compared to state-of-the-art techniques. Compared to other approaches, the implemented algorithm is scalable and was able to find optimized circuits within 4 seconds in the worst case.     

Implementing a one-bit reversible full adder using quantum-dot cellular automata

Quantum-dot cellular automata (QCA) technique is one of the emerging and promising nanotechnologies. It has considerable advantages versus CMOS technology in various aspects such as extremely low power dissipation, high operating frequency and small size. In this paper, designing of a one-bit full adder is investigated using a QCA implementation of Toffoli and Fredkin gates. Then, a full adder design with reversible QCA1 gates is proposed regarding to overhead and power savings. Our proposed full adder design is more preferable when considering both circuit area and speed. The proposed design uses only two QCA1 gates and maximizes the circuit density and focuses on a layout of the circuit which is minimal in using QCA cells.