Hot-carrier-induced degradation in p-channel LDD MOSFET's

When the p-channel MOSFET is stressed near the maximum substrate current Isub, the lifetime t (5-percent increase in the transconductance) followstI_{sub} = A(I_{sub}/I_{d})^{-n}, with n = 2.0. A simple electron trapping model is proposed to explain the observed power law relationship. The current ratioI_{sub}/I_{d}and the maximum channel electric field decrease with increasing stress time, which is consistent with electron trapping in the oxide during the stress.     

Hot-carrier-induced photovoltage in silicon bipolar junction transistors

As bipolar junction transistors (BJTs) are scaled down, the current density increases and base pushout may happen. To prevent base widening, the collector doping concentration is increased; therefore, this increases the electric field in the base-collector junction. In the active operation of BJTs, impact ionization happens and impact-ionization-induced photon emission is created in the base-collector (BC) junction and photon absorption happens in the base-emitter (BE) junction. This makes the carrier injection from the BE junction to the BC junction with avalanche different from that without avalanche. Similarly, the avalanche-induced light emission in the BE junction will induce photocarriers in the BC junction diode. In this paper, we report observation of the photovoltage in the BC junction resulting from hot-carrier electroluminence in the BE junction on a conventional low-power n-p-n bipolar transistor. We found a photovoltage of 0.36 V and a collector current reversal in the inverse active operation.     

Dynamic hot-carrier induced degradation in n-channel polysilicon thin-film transistors

The effects of hot-carriers under dynamic stress on the transfer characteristics and the noise performance of n-channel polysilicon thin-film transistors are analysed. The observed decrease in the on-state current is directly related to the mobility of a damaged region extended over a length of about 0.53 μm beside the drain, which is evaluated through analysis of the transfer characteristics at low drain voltage. The mobility degradation in the damaged region is due to the formation of traps located near the polysilicon/gate oxide interface as evidenced by the 1/f noise measurements.     

Single-transistor-latch-induced degradation of front- andback-channel thin-film SOI transistors

The front- and back-channel transistor characteristics in thin-film silicon-on-insulator (SOI) MOSFETs have been studied before and after front-channel hot-carrier stress resulting from single-transistor latch. This stress causes the following significant changes: (a) a reduction of the front-channel current for a given gate voltage, (b) an increase in front-channel drain-source breakdown voltage when measured in the reverse mode, and (c) a decrease in the back-channel transconductance. These changes can be attributed to the hot-carrier induced interface traps on both front and back interfaces near the drain junction     

Fluorination-mitigated high-current degradation of amorphous InGaZnO thin-film transistors

As growing applications demand higher driving currents of oxide semiconductor thin-film transistors(TFTs), severe instabilities and even hard breakdown under high-current stress(HCS) become critical challenges. In this work, the triggering voltage of HCS-induced self-heating(SH) degradation is defined in the output characteristics of amorphous indium-galliumzinc oxide(a-IGZO) TFTs, and used to quantitatively evaluate the thermal generation process of channel donor defects. The fluorinated a-IGZO...     

Effects of hydrogenation on the performance and stability of p-channel polycrystalline silicon thin-film transistors

The effects of hydrogenation on the performance and stability under electrical stress of p-channel polycrystalline silicon thin-film transistors (polysilicon TFTs) are investigated. The hydrogenation is performed in pure H₂ plasma or in plasma of 4% H₂ diluted in He gas. Devices hydrogenated in plasma of H₂/He exhibit lower subthreshold swing with better uniformity and lower leakage current, which indicate passivation of mid-gap trap states arising from dangling bonds at the grain boundaries. Hot-carrier experiments demonstrate that the stability of p-channel TFTs is improved as the hydrogenation becomes more efficient due to the effective removal of donor-type trap states at the grain boundaries.     

Bias-stress stability of low-voltage p-channel and n-channel organic thin-film transistors on flexible plastic substrates

The bias-stress stability of low-voltage organic p-channel and n-channel thin-film transistors (TFTs) based on five promising organic semiconductors and fabricated on flexible polyethylene naphthalate (PEN) substrates has been investigated. In particular, it has been studied to which extent the bias-stress-induced decay of the on-state drain current of the TFTs is affected by the choice of the semiconductor and by the gate-source and drain-source voltages applied during bias stress. It has been found that for at least some of the organic p-channel TFTs investigated in this study, the bias-stress stability is comparable to that of a-Si:H and metal-oxide TFTs, despite the fact that the organic TFTs were fabricated at significantly lower process temperatures, which is important in view of the fabrication of these devices on plastic substrates.     

Hot-carrier-induced degradation in nitrided oxide MOSFETs

Hot-carrier-induced degradation in commercially prepared silicon-gate MOSFETs incorporating ammonia annealed, nitrided oxides as the gate dielectric is examined and compared with the degradation observed in similar devices incorporating conventional oxides. Nitridation at 1100°C for 2 h is observed to reduce the rate of transconductance degradation and threshold voltage increase by nearly half, compared to the oxide for stressing at both low and high gate bias, and to modify the effects of stressing on the substrate current characteristics. In contrast, nitridation at 1150°C produces both improvements and degradations in device stability depending on the parameter examined and the stress conditions. While ammonia annealing introduces nitrogen, it also appears to incorporate excess hydrogen in the dielectrics that alters charge trapping and interface-state generation so that the performance of the dielectric under electrical stress depends on the concentrations of both species     

Substrate current and degradation of n-channel polycrystalline silicon thin-film transistors

Experimental investigation of the substrate current I_sub as a function of the gate voltage has been performed in n-channel polycrystalline silicon thin-film transistors (polysilicon TFTs), considering the drain voltage as a parameter of the study. At low gate voltages, I_sub exhibits a peak located close to the threshold voltage of the transistor due to hot-carriers generated by impact ionization. At higher gate voltages, I_sub increases monotonically with increasing the gate voltage, which is attributed to the temperature rise owing to self-heating. The degradation behavior of polysilicon TFTs, stressed under two different gate and drain bias conditions that cause the same substrate current due to hot-carrier and self-heating effects, is investigated.     

Cut-off frequency and transit time analysis in short geometry polysilicon thin-film transistors

An accurate model for the drain characteristics, transconductance, cut-off frequency and transit time of a short geometry polysilicon thin film transistor (poly-Si TFT) is presented. An accurate threshold voltage and field dependent mobility are the key parameters in determining the above-threshold characteristics. The current-voltage characteristics of the device show an excellent agreement with experimental results. The transconductance for both linear and saturation regions is calculated and its variation with channel length, drain and gate voltages is studied. The total gate capacitance including the geometric capacitance and the fringing capacitance is also evaluated and simple closed form expressions for the cut-off frequency and transit time are obtained. A high cut-off frequency is achieved, which is important in realizing the device for millimetre and microwave frequency applications.     

Electrical instability in short channel organic thin-film transistors induced by lucky-polaron mechanism

In this work we study the electrical stability under both gate bias stress and gate and drain bias stress of short channel (L = 5 μm) bottom contact/top gate OTFTs made on flexible substrate with solution-processed organic semiconductor and fluoropolymer gate dielectric. These devices show high field-effect mobility (μ_FE> 1 cm²V⁻¹s⁻¹) and excellent stability under gate bias stress (bias stress V_ds = 0V). However, after prolonged bias stress performed at high drain voltage, V_ds, the transfer characteristics show a decreased threshold voltage, degradation of the subthreshold slope and an apparent increase in the field effect mobility. Furthermore, the output characteristics show an asymmetry when measured in forward and reverse mode. These experimental results can be explained considering that the bias stress induces the damage of a small part of the device channel, localized close to the source contact. The analysis of the experimental data through 2D numerical simulations supports this explanation showing that the electrical characteristics after bias stress at high V_ds can be reproduced considering the creation of donor-like interface states and trapping of positive charge into the gate dielectric at the source end of the device channel. In order to explain this degradation mechanism, we suggest a new physical model that, assuming holes injection from the source contact into the channel in bounded polarons, envisages the defect creation at the interface near the source end of the channel induced by injection of holes that gained energy from both the high longitudinal electric fields and the polaron dissolution.     

Substrate current in silicon p-channel MOS transistors

Substrate currents are observed in silicon p-channel MOSFET devices. These currents are similar to those observed in n-channel MOSFETs but have a markedly higher threshold voltage.     

Source-gated thin-film transistors

The thin-film transistor is one of a family of field-effect transistors. They all operate in the same way: a gate modulates the conductance of a channel and the current saturates when the drain end is depleted of carriers. The authors introduce a source-gated transistor that overcomes some of the fundamental limitations of the field-effect transistor. The gate controls the supply of carriers and the current saturates when the source is depleted of carriers. The result is a thin-film transistor that can operate at lower voltages with larger gains and lower power dissipation. It should also preserve its characteristics with smaller dimensions.     

Hot-carrier-induced degradation in ultra-thin-film fully-depleted SOI MOSFETs

The charge-pumping measurement technique was successfully applied to submicron (L_eff = 0.35 μm) n-MOSFETs on ultra-thin (50 nm) SOI film. The hot-carrier-induced degradation is studied by examining the damages to both gate-oxide and buried-oxide (BOX) interfaces. We found that when stressed at maximum substrate current, interface-trap generation is still the primary cause for hot-carrier-induced degradation. Even for ultra-thin-film SOI devices, the hot-carrier-induced damage is locally confined to the gate-oxide interface and only minor damage is observed at the buried-oxide interface. The buried-oxide interface charging contributes less than 5% of the overall drain current degradation.     

Hot-carrier-induced degradation in p-MOSFETs under AC stress

Lifetimes under AC stress are calculated with a quasistatic model using parameters extracted from DC stress data. For inverter-like waveforms, the measurement data show reasonable agreement with the simulation results. For waveforms with turnoff transient occurring in the presence of high drain voltage, more degradation than the model predicts is found if the transient is short (⩽10 ns) and gate voltage is high     

Hot-carrier-induced degradation of LDD polysilicon TFTs

In order to improve the stability of polysilicon thin-film transistors (TFTs) several drain junction architectures have been proposed. In this paper, the hot-carrier (HC) related stability of the lightly doped drain (LDD) TFT architecture is analyzed by using an iterative algorithm that relates the HC induced damage to the carrier injection across the device interfaces with gate and substrate oxide. The resulting creation of interface states and trapped charge is taken into account by using a system of rate equations that implements mathematically the Lais two step model, in which the generation of interface states is attributed to the trapping of hot-holes by centres into the oxide followed by the recombination with hot electrons. The rate equations are solved self-consistently with the aid of a device simulation program. By successive iterations, the time evolution of the interface state density and positive trapped charge distribution has been reconstructed, and the electrical characteristics calculated with this model are in good agreement with experimental data. This algorithm represent an improvement of an already proposed degradation model, in which the interface states formation dynamics is accounted by using a phenomenological approach. The present model has been applied to reproduce the degradation pattern of LDD TFTs and it is found that generation of interface states proceed almost symmetrically on the front and back device interfaces, starting from the points in which the transverse electric field peaks, and moving toward the drain side of the device. The final interface states distribution determines a sort of "bottleneck" in the active layer carrier density, that can explain the sensitivity to HC induced damage of both transfer and output characteristics.     

Hot-carrier-induced MOSFET degradation under AC stress

The effects of gate and drain voltage waveforms on the hot-carrier-induced MOSFET degradation are studied. Drain votage transients have little effect on the degradation rate. Only the falling edge of the gate pulse in the presence of a high drain voltage enhances the degradation rate. For devices in typical inverter circuits, dc stress results together with the substrate current waveform can predict the degradation rate under ac stress for a wide range of rise and delay times.     

Anomalous turn-on voltage degradation during hot-carrier stress inpolycrystalline silicon thin-film transistors

In this letter, we present experimental data showing that hot-carrier stress in laser annealed polycrystalline silicon thin-film transistors provokes an anomalous turn-on voltage variation. Although under various hot-carrier stress intensities the maximum transconductance degradation shows the same power-time dependent law, turn-on voltage can exhibit different behaviors. This observation lead to the conclusion that turn-on voltage depends on two different degradation mechanisms: injection of hot carriers into the gate oxide and degradation of grain boundaries. We show that these two mechanisms may be distinguished since they obey different power-time dependent laws as a function of stress duration     

Characteristics of p-channel polysilicon conductivity modulatedthin-film transistors

A p-channel polysilicon conductivity modulated thin-film transistor (CMTFT) is demonstrated and experimentally characterized. The transistor uses the concept of conductivity modulation in the offset region to obtain a significant reduction in on-state resistance. The conductivity modulation is achieved by injecting minority carriers (electrons) into the offset region through a diode added to the drain. Experimental results show that the conductivity modulation in the p-channel device is as effective as that in the n-channel device. This structure can provide 1.5 to 2 orders of magnitude higher on-state current than that of the conventional offset drain thin-film transistor (TFT) at drain voltage ranging from -15 V to -5 V while still maintaining low leakage current and simplicity in device operation. The p-channel CMTFT can be combined with the n-channel CMTFT to form CMOS high-voltage drivers, which is very suitable for use in fully integrated large-area electronic applications     

Anomalous hot-carrier behavior for LDD p-channel transistors

It has previously been reported that gradual junction p-channel transistors can have shorter lifetimes under hot-carrier stress conditions than abrupt junction devices (see IEEE Trans. Electron Devices, vol. 39, p. 2290-98, 1992). Here, the work is extended to LDD (lightly doped drain) structures. p-MOS hot-carrier effects are examined for deep submicron structures with abrupt and LDD junctions. It is shown that, contrary to the case of n-MOS transistors, the lifetimes for hot-carrier stress of the LDD p-MOS transistors are actually shorter than their abrupt junction counterparts, in the range of LDD dopings examined here. This is explained in terms of two competing mechanisms, gate electronic injection, which decreases for the LDD junctions, and the size of the damage region in the oxide, which increases for the LDD junctions. It is concluded that using LDD-type structures for hot-carrier control does not automatically guarantee longer lifetimes