Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison

In this paper, some of the most practically interesting full adder topologies are analyzed in terms of their delay dependence on the supply voltage fluctuations, which are a major contribution to the delay uncertainty, which in turn limits the speed performance of current VLSI circuits. Analytical models of the delay sensitivity with respect to supply variations are derived by following a simplified circuit analysis, and the resulting expressions are simple enough to afford a deeper insight into the impact of supply voltage variations on each topology. The models are shown to be sufficiently accurate through simulations with CMOS technologies having a minimum feature size ranging from 90 nm to 0.35 mum. Several interesting properties and design considerations are derived from these models, and the effect of the supply voltage scaling, technology scaling, transistor sizing, and input transition time is discussed. Strategies to evaluate the delay sensitivity since the early design phases (e.g., from ring oscillator measurements) are also introduced. As a fundamental result, it is shown that the delay sensitivity to supply variations will increase in the next technology nodes, thus, it is expected that controlling the supply variations will be an increasingly important issue in the design of the next generation VLSI circuits. The proposed methodology is also analyzed in the case of more general digital circuits, and is used to estimate the impact of the inter-die threshold voltage variations on the delay of the considered full adder topologies     

GaAs/AlGaAs and InGaAs/AlGaAs MODFET inverter simulations

Although MODFET's have exhibited the fastest switching speed for any digital circuit technology, there is as yet no clear consensus on optimal inverter design rules. We therefore have developed a comprehensive MODFET device model that accurately accounts for such high gate bias effects as transconductance degradation and increased gate capacitance. The device model, which agrees with experimental devices fabricated in this laboratory, is used in the simulation of direct-coupled FET logic (DCFL) inverters with saturated resistor loads. Based on simulation results, the importance of large driver threshold voltage not only for small propagation delay times but for wide logic swings and noise margins is demonstrated. Furthermore, minimum delay times are found to occur at small supply voltages as seen experimentally. Both of these results are attributed to the reduction of detrimental high gate bias effects. The major effect of reducing the gate length on delay time is to decrease the load capacitance of the gate. Using 0.25-µm gates, delay times of 5 and 3.6 ps at 300 and 77 K, respectively, are predicted. Finally, the recently introduced In-GaAs/AlGaAs MODFET's are shown to have switching speeds superior to those of conventional GaAs/AlGaAs MODFET's.     

Dual-Mode Multiple-Band Digital Controller for High-Frequency DC–DC Converter

An integrated digital controller design for dc-dc converter is proposed in this paper. The proposal presents a multiple- band dual-stage (MBDS) delay line A/D converter (ADC) for wide dynamic range of operation with reduced ripple, chip area, and power consumption. This proposal also introduces a novel folding logic for digital error calculation and dual-mode error control PID for improving transient response. A complete closed-loop experimental prototype is demonstrated on a field-programmable-gate- array-based setup. The feasibility and functionality of the proposed digital controller is verified with a closed-loop synchronous buck converter prototype that switches at 1 MHz and regulates over a wide output voltage range of 1.6-3.3 V. The proposed MBDS delay line ADC is fabricated with discrete logic gates and flip-flops. The integrated digital controller is also implemented using standard cell-based design methodology in 0.5-mum CMOS technology. The design reduces 33 % on-chip area compared to an equivalent of 64 tap delay line ADC. The complete digital controller chip takes less than 0.7 mm² of silicon area and consumes an average current of 92 muA at 1-MHz switching frequency. The voltage-mode digital loop achieves tracking time of less than 10 mus for 1-V step change of the reference voltage and settling time of 20 mus. Post layout simulation and experimental results are demonstrated.     

A monotonic digitally controlled delay element

A monotonic digitally controlled delay element (DCDE) is implemented in the 0.18 /spl mu/m CMOS technology. In this paper, the design procedure of the new architecture and measurement results are reported. The delay of the DCDE changes monotonically with respect to the digital input vector. The monotonicity is one of the important features of this new architecture. Due to its monotonic behavior, the design of the DCDE is rather straightforward. The DCDE can be analyzed by a simple set of empirical equations with reasonable accuracy and can be made more tolerant to process, temperature, and supply voltage variations. The implemented delay element provides a delay resolution of as low as 2 ps and consumes 170 /spl mu/W to 340 /spl mu/W static power depending on the digital input vector.     

A high-efficiency fully digital synchronous buck converter power delivery system based on a finite-state machine

A fully digital, self-adjusting, and high-efficiency power supply system has been developed based on a finite-state machine (FSM) control scheme. The system dynamically monitors circuit performance with a delay line and provides a substantially constant minimum supply voltage for digital processors to properly operate at a given frequency. In addition, the system adjusts the supply voltage to the required minimum under different process, voltage, and temperature and load conditions. The design issues of the fully digital power delivery system are discussed and addressed. This digital FSM scheme significantly reduces the complexity of control-loop implementation (<1800 gates) and power consumption (< 100 /spl mu/W at 1.2 V) compared to other approaches based on proportional-integral-differential control. The power delivery control system is fabricated in a 0.13-/spl mu/m CMOS process and its core die size is 160 /spl times/ 110 /spl mu/m/sup 2/.     

A high-speed programmable CMOS interface system combining D/Aconversion and FIR filtering

This paper describes the design, integrated circuit realization, and experimental characterization of a high-speed programmable interface system combining the functions of digital-to-analog (D/A) conversion and FIR filtering. The system comprises four high-speed digital delay lines, with programmable delay length, together with four high-speed steering-current D/A converters with independent digitally-programmable gains. A demonstration prototype chip has been fabricated in a 1.2-μm digital CMOS technology. At 54 MHz conversion rate and digital delay lines clocked at 18 MHz, it consumes 115 mW for a full-scale output current of 13.3 mA at 5 V supply     

A measurement method for the increase of digital switching time due to hot-electron stress

Channel hot-electron (CHE) injection poses a reliability problem for n-channel field-effect transistors with small design rules. One often assesses the reliability of a particular fabrication process and design by subjecting individual transistors, instead of an entire circuit, to continuous or pulsed voltage stress. Simple inspection of the linear region transconductance degradation and threshold voltage shift of the individual devices, however, does not yield direct information on the circuit performance impact of channel hot-electron stress. In this letter we describe a simple measurement method for the extraction of the increase of digital switching time due to channel hot-electron stress. One performs this measurement on discrete transistors so that reliability tests still employ these individual devices. We obtain good agreement between this method and a direct measurement of the increased switching time of a CMOS inverter. We also find that the switching time changes negligibly even when the linear transistor characteristics are severely degraded if this swiching delay is measured with the same source and drain terminals as were employed for the hot-electron stress.     

MSW devices for EW receiver applications

Conclusion Significant improvements are required in the performance of MSW dispersive delay lines and filter banks before they are ready for systems application. Typically delay lines with bandwidths of 1 GHz or greater, differential delays in the range 200 ns to 1s, and minimum phase errors (<±1 °) are required for large (40 dB) dynamic range compressive receivers. However, techniques are evolving (see rest of this issue) in this relatively new area of technology which will allow systems performance requirements on phase errors to be met. Possible approaches to low phase error dispersive delay lines include reflective arrays, stepped ground planes, and multiple YIG films. The stepped ground plane technique is the most advanced and uses an optimization approach to the delay-line design, which results in a minimum phase error [20]. Ultimately the minimum achievable phase error will be limited by reflections from transducers and multiple mode effects in the delay lines. The MSW compressive receiver requires parallel advances in high-speed digital processing techniques to achieve its full potential.The MSW filter bank provides a simple channelization technique applicable up to approximately 20 GHz. Narrowband channels with 10 dB insertion loss, 3 dB bandwidths of 10 to 40 MHz, and 50 dB bandwidths of 30 to 120 MHz are possible with the already demonstrated techniques. Broader bandwidth channels in the range 50 to 200 MHz with flat passband response require improved transducer design techniques. The channelized receiver does not require extremely high-speed operations but, since a large number of channels are involved, size and cost become very significant.     

A mixed-signal approach to high-performance low-power linearfilters

We present a new approach to the design of high-performance low-power linear filters. We use p-channel synapse transistors as analog memory cells, and mixed-signal circuits for fast low-power arithmetic. To demonstrate the effectiveness of our approach, we have built a 16-tap 7-b 200-MHz mixed-signal finite-impulse response (FIR) filter that consumes 3 mW at 3.3 V. The filter uses synapse pFETs to store the analog tap coefficients, electron tunneling and hot-electron injection to modify the coefficient values, digital registers for the delay line, and multiplying digital-to-analog converters to multiply the digital delay-line values with the analog tap coefficients. The measured maximum clock speed is 225 MHz; the measured tap-multiplier resolution is 7 b at 200 MHz. The total die area is 0.13 mm². We can readily scale our design to longer delay lines     

An ultra-low power CMOS DC–DC buck converter with double-chain digital PWM technique

In present-day integrated digital circuits are become attractive choice for the DC–DC buck converters. This paper proposes a novel approach of CMOS DC–DC buck converter with double-chain digital pulse width modulation (PWM) for ultra-low power applications. The proposed digital PWM architecture consists of double delay lines which is to reduce power consumption and improves ripple voltage with the resolution. An algorithm is proposed that describes the operation of digital PWM. The double chain digital PWM is implemented and analyzed in cadence platform using commercial 180 nm TSMC design kit. The promising results reveals that the power consumption is reduces up to 1.16 µW with occupies less area under the operating frequency of 100 kHz. The DC–DC buck converter with proposed PWM achieves peak efficiency of 92.6% including a load current range of 4–10 mA. This proposed digital PWM method demonstrates its ability to minimize the ripple voltage by 49% and enables to DC–DC converter for compose in a compact chip area as compared to conventional converters. Measured and Simulated power efficiency are made good agreement with each other.     

Delay-locked loop technique for temperature stabilisation ofinternal delays of CMOS FPGA devices

A delay-locked loop (DLL) technique for use with typical CMOS field programmable gate array (FPGA) devices is presented. It allows for temperature stabilisation of the internal delays of the devices, especially when the digital delay lines are designed. The voltage V_cc supplying the FPGA device is varied within a limited range by the DLL to stabilise the internal delays of the device under changes in the ambient temperature. The method is illustrated by presenting results of the realisation of an interpolating time counter with 200 ps resolution, implemented on a single CMOS FPGA device     

A high-resolution time interpolator based on a delay locked loopand an RC delay line

An architecture for a time interpolation circuit with an rms error of ~25 ps has been developed in a 0.7-μm CMOS technology. It is based on a delay locked loop (DLL) driven by a 160-MHz reference clock and a passive RC delay line controlled by an autocalibration circuit. Start-up calibration of the RC delay line is performed using code density tests (CDT). The very small temperature/voltage dependence of R and C parameters and the self calibrating DLL results in a low-power, high-resolution time interpolation circuit in a standard digital CMOS technology     

Energy optimization of pipelined digital systems using circuit sizing and supply scaling

We present a systematic method for minimizing the energy of pipelined digital systems, through joint optimization of each pipeline stage and the system. A pipeline stage with a constant load can either be optimized for delay at a given input size, minimized for energy at a fixed delay, or have delay traded off for energy at a fixed input size. The results of these optimizations are combined to yield the design region for energy and delay. At the system level with a fixed throughput constraint, the sensitivities to input size and output load of all pipeline stages form the optimal energy criteria that provide a systematic method to minimize the total system energy. This method is applied to a media datapath, where we show up to 37% energy saving for a fixed performance. The minimal energy-delay curve of the system obtained through application of this method demonstrates similar characteristics as that of a single pipeline stage. With voltage scaling, the optimal solution displays a strong dependency between delay, energy, and supply voltage. The proper tradeoff between these entities makes a fundamental impact on efficient digital design.     

A 2.5 GHz All-Digital Delay-Locked Loop in 0.13 μm CMOS Technology

A 2.5 GHz, 30 mW, 0.03 mm², all-digital delay-locked loop (ADDLL) in 0.13 mum CMOS technology is presented. The tri-state digital phase detector suppresses the dithering phenomenon and reduces the output peak-to-peak jitter for a counter-controlled digital DLL. The lattice delay unit has both a small delay step and a fixed intrinsic delay of two nand gates. A modified successive approximation register-controller reduces the locking time and allows the DLL to track the process, voltage, temperature, and load variations. This ADDLL locks in 24 cycles and has a closed-loop characteristic. The measured peak-to-peak jitter is 14 ps at 2.5 GHz.     

Designing soft-edge flip-flop-based linear pipelines operating in multiple supply voltage regimes

Soft-edge flip-flop (SEFF) based pipelines can improve the performance and energy efficiency of circuits operating in the super-threshold (supply voltage) regime by enabling the opportunistic time borrowing. The application of this technique to the near-threshold regime of operation, however, faces a significant challenge due to large circuit parameter variations that result from manufacturing process imperfections. In particular, delay lines in SEFFs have to be over-designed to provide larger transparency windows to overcome the variation in path delays, which causes them to consume more power. To address this issue, this paper presents a novel way of designing delay lines in SEFFs to have a large enough transparency window size and low power consumption. Two types of linear pipeline design problems using the SEFFs are formulated and solved: (1) designing energy-delay optimal pipelines for the general usage that requires SEFFs to operate in both the near-threshold and super-threshold regimes, and (2) designing minimum energy consumed pipelines for particular use case with a minimum operating frequency constraint. Design methods are presented to derive requisite pipeline design parameters (i.e., depth and sizing of delay lines in SEFFs) and operating conditions (i.e., supply voltage and operating frequency of the design) in presence of process-induced variations. HSPICE simulation results using ISCAS benchmarks demonstrate the efficacy of the presented design methods.     

Reflection and crosstalk in logic circuit interconnections

Digital logic circuits are now available and are being used with delay times that are comparable to the delays of interconnections used in packaging these circuits. At high speeds, however, such interconnections no longer behave as simple short circuits, but take on the appearance of transmission lines. Unless transmission lines are terminated properly, ``reflections' can develop that might be of sufficient magnitude to produce false logic levels or exceed maximum circuit voltage specifications. One may choose to solve the problem by increasing the density of the system. This, however, introduces the problem of ``crosstalk.' The present article describes several analytical techniques for predicting the kinds of reflections and crosstalk that are typically seen in digital systems, thus enabling the engineer to determine in advance whether or not such ``interconnection noise' will result, how bad it will be, and what the typical interconnection limitations are for circuits of various speeds.     

Standby/active mode logic for sub-1-V operating ULSI memory

New gate logics, standby/active mode logic I and II, for future 1 Gb/4 Gb DRAMs and battery operated memories are proposed. The circuits realize sub-l-V supply voltage operation with a small 1-μA standby subthreshold leakage current, by allowing 1 mA leakage in the active cycle. Logic I is composed of logic gates using dual threshold voltage (Vt) transistors, and it can achieve low standby leakage by adopting high Vt transistors only to transistors which cause a standby leakage current. Logic II uses dual supply voltage lines, and reduces the standby leakage by controlling the supply voltage of transistors dissipating a standby leakage current. The gate delay of logic I is reduced by 30-37% at the supply voltage of 1.5-1.0 V, and the gate delay of logic II is reduced by 40-85% at the supply voltage of 1.5-0.8 V, as compared to that of the conventional CMOS logic     

Current mode ADC design in a 0.5-μm CMOS process

This paper presents a pipelined current mode analog to digital converter (ADC) designed in a 0.5-μm CMOS process. Adopting the global and local bias scheme, the number of interconnect signal lines is reduced numerously, and the ADC exhibits the advantages of scalability and portability. Without using linear capacitance,this ADC can be implemented in a standard digital CMOS process; thus, it is suitable for applications in the system on one chip (SoC) design as an analogue IP. Simulations show that the proposed current mode ADC can operate in a wide supply range from 3 to 7 V and a wide quantization range from ±64 to ±256μA. Adopting the histogram testing method, the ADC was tested in a 3.3 V supply voltage/±64μA quantization range and a 5 V supply voltage/±256μA quantization range, respectively. The results reveal that this ADC achieves a spurious free dynamic range of 61.46dB, DNL/INL are -0.005 to +0.027 LSB/-0.1 to +0.2 LSB, respectively, under a 5 V supply voltage with a digital error correction technique.     

A monolithic digital clock-generator for on-chip clocking of customDSP's

This paper shows a robust and easily implemented clock generator for custom designs. It is a fully digital design suitable for both high-speed clocking and low-voltage applications. This clocking method is digital, and it avoids analog methods like phase locked loops or delay line loops. Instead, the clock generator is based on a ring counter which stops a ring oscillator after the correct number of cycles. Both a 385 MHz clock and a 15 MHz custom DSP application using the on-chip clocking strategy are described. The prototypes have been fabricated in a 0.8 μm standard CMOS process. The major advantages with this clocking method are robustness, small size, low-power consumption, and that it can operate at a very low supply voltage     

Exploring the design space of mixed swing quadrail for low-powerdigital circuits

This paper describes and explores the design space of a mixed voltage swing methodology for lowering the energy per switching operation of digital circuits in standard submicron complementary metal-oxide-semiconductor (CMOS) fabrication processes. Employing mixed voltage swings expands the degrees of freedom available in the power-delay optimization space of static CMOS circuits. In order to study this design space and evaluate the power-delay tradeoffs, analytical polynomial formulations for power and delay of mixed swing circuits are derived and HSPICE simulation results are presented to demonstrate their accuracy. Efficient voltage scaling and transistor sizing techniques based on our analytical formulations are proposed for optimizing energy/operation subject to target delay constraints; up to 2.2× improvement in energy/operation is demonstrated for an ISCAS'85 benchmark circuit using these techniques. Experimental results from HSPICE simulations and measurements from an And-Or-Invert (AO1222) test chip fabricated in the Hewlett-Packard 0.5 μm process are presented to demonstrate up to 2,92× energy/operation savings for optimized mixed swing circuits compared to static CMOS