一种应用于流水线A/D转换器的数字校准算法

通过输入比较器阈值电压到流水线电路计算跳变点高度，重新计算权重，进行数字校准。这种校准方法与数字冗余结合，属于纯数字电路实现，在可实现性与可靠性上具有很大的优势。仿真结果表明，这种方法能保证高精度。     

逐次逼近A/D转换器综述

从逐次逼近A／D转换器（SA-A／D）的工作原理出发，分别对其核心模块D／A转换器和比较器进行了讨论。SA-A／D转换器中的D／A转换器可分为电压定标、电流定标和电荷定标三种，重点分析了三种目前应用较多的并行电容、分段电容和RC混合结构。SA-A／D转换器中的比较器可分为运放结构比较器和锁存（latch）比较器，实际常常使用这两种结构级联的高速高精度比较器，并配合失调校准技术，达到较高精度。最后，简要总结了SA-A／D转换器的研究现状，阐述了其在精度、速度和功耗三个方面的发展状况。     

一种应用于A/D转换器的Flash单元的设计

针对A/D转换器中广泛使用的Flash单元,设计了一组由全差分预放大器、动态比较器和D触发器组成的电路。对电路的抗翻转噪声能力进行了分析和仿真,指出,通过改进全差分预放大器的共模反馈电路,有效提高了Flash单元抗翻转噪声的能力。利用SMIC 0.18μm CMOS混合信号工艺,将设计的Flash单元应用到一个Flash A/D转换器中进行了流片。A/D转换器具有100 MHz奈奎斯特采样带宽。流片测试结果表明,采用该Flash单元的A/D转换器的信噪比SNR获得了改善,有效位数ENOB能提高大约0.6比特。     

模拟/数字转换器的动态性能参数处理

文章介绍了一种针对模拟／数字转换器(ADC)的动态性能参数设计的灵活易用的分析程序。该程序基于使用FFT算法的谱分析测试方法，并通过设计一个交互性能良好、功能丰富的用户图形界面(GUI)，使用户可以方便地分析4～20位分辨率的ADC的量化结果，并给出多种动态性能参数的分析值，便于设计者和使用者评估ADC的性能。     

Analog-to-Digital Converters: Digitizing the Analog World

Challenges in analog-to-digital (A/D) conversion for future scaled complementary metal-oxide-semiconductor (CMOS) technologies are investigated. The analysis of a figure of merit (FOM) that accounts for energy per conversion step indicates that op-amps are one of the most significant performance bottlenecks. New mixed-signal circuit architectures, which are more suitable for A/D conversion in scaled CMOS technologies and are more energy efficient than traditional architectures, are described. These circuits sense the crossing of virtual ground with comparators or zero-crossing detectors instead of forcing the virtual ground with op-amps. The FOM derivations for the comparator and zero-crossing based circuits indicate potentially a large improvement over traditional op-amp based circuits. The designs and experimental results of analog-to-digital converters based on a prototype comparator and zero-crossing are discussed in detail.     

Conversion Errors in 4-Bit Flash Analog-to-Digital Converters

Conversion errors in 4-bit flash analog-to-digital converters are computed from difference equations as a function of the ratio of the comparator input impedance to the R-2R bias network values. For maximum conversion errors less than 3 percent, the comparator input impedance should be 1000 times greater than the R value of the bias network.     

Power Dissipation Bounds for High-Speed Nyquist Analog-to-Digital Converters

A very important limitation of high-speed analog-to-digital converters (ADCs) is their power dissipation. ADC power dissipation has been examined several times, mostly empirically. In this paper, we present an attempt to estimate a lower bound for the power of ADCs, based on first principles and using pipeline and flash architectures as examples. We find that power dissipation of high-resolution ADCs is bound by noise, whereas technology is the limiting factor for low-resolution devices. Our model assumes the use of digital error correction, but we also study an example on the power penalty due to matching requirements. A comparison with published experimental data indicates that the best ADCs use about 50 times the estimated minimum power. Two published ADCs are used for a more detailed comparison between the minimum bound and today's designs.      

16位A/D转换器的精度测试

文中好一种低成本、高可靠性的Ａ．Ｄ转换器（ＡＤＣ）转换精度的计算机辅助测试方法,并对测试系统的原理、结构及算法进行了描述。该方法适合于分率低于１６位的逐次逼近型ＡＤＣ的测试,对ＡＤＣ的入厂检验测试有一定的实用价值。     

A Frequency-Translating Hybrid Architecture for Wide-Band Analog-to-Digital Converters

A parallel architecture for high-bandwidth analog-to-digital conversion is presented. The proposed architecture uses frequency translation along with multi-rate signal processing to digitize a wide-band continuous-time analog signal through an array of identical narrowband analog-to-digital converters (ADCs). The basic idea behind this structure is to decompose the input signal into smaller frequency (channels). Each channel is composed of a two-path system that includes mixers, identical low-pass filters and identical baseband ADCs. The signal in each two-path channel is sampled and digitized into narrowband quadrature signals. After digitizing the signal in each channel, the low-rate subband samples are upconverted back to their respective center frequencies, then filtered and combined to reconstruct the digital representation of the original wide-band input signal. The digital filters are designed to minimize the reconstruction error. The effects of some major nonidealities are discussed. Several simulation results are also presented to demonstrate the performance of the system.     

数字信道化技术中ADC的性能分析

在卫星通信系统中,数字信道化技术的应用越来越广泛,而模数转换器（ADC）作为数字信道化器前端不可缺少的一部分起着至关重要的作用。基于ADC基本原理和性能,仿真分析了在ADC量化位数不同的条件下,ADC对数字已调信号解调性能的影响。     

高速模/数转换器常规参数的动态测试

高速模拟／数字转换器(ADC)被广泛应用于视频和无线通讯等领域。如何对高速ADC的性能进行准确评估是一个受到高度关注的课题。准确评估高速ADC的性能需要采用动态测试方法。文章运用码密度立方图分析法，分析了高速ADC常规参数，包括失调、微分非线性、积分非线性、失码、增益误差等，的动态测试。     

A Novel Sampling Switch Suitable for Low-Voltage Analog-to-Digital Converters

提出了一种适用于低电源电压的新型高线性度采样开关.与传统低电压采样开关相比,这种新型采样开关不仅消除了MOS开关由于栅源电压随输入信号变化所引入的非线性,而且进一步消除了MOS开关由于阈值电压随输入信号变化引入的非线性.这是通过采用一个与采样MOS开关具有相同阈值电压的\"复制\"开关得以实现的.基于Chartered 0.35μm标准CMOS工艺,文中设计了一个此类新型MOS采样开关,在输入信号为0.2MHz正弦波,峰峰值为1.2V,采样时钟频率为2MHz时,无杂散动态范围达到111dB,比栅压自举开关提高了18dB;同时导通电阻的变化减小了90%.这种新型采样开关特别适用于低电压,高精度模数转换器.     

Off-Chip Diagnosis of Aperture Jitter in Full-Flash Analog-to-Digital Converters

Gaussian aperture jitter leads to a reduction in the Signal-to-Noise-Ratio of A/D converters. Other noise sources, faults and nonlinearities also effect the digital output signal. A new off-chip diagnosis method, which systematically separates the jitter-induced errors from the errors caused by these other factors, is described. Deterministic errors are removed via a subtraction technique. High-level ADC simulations have been carried out to determine relations between the size of the jitter or decision-level noise and the remaining random errors. By carrying out two tests at two different input frequencies and using the simulation results, errors induced by decision-level noise can be removed.     

一种适合12位A／D转换器的高速缓冲器

详细论述了一种建立时间为５０ｎｓ（ｍａｘ，精确到０．１％）的高速缓冲器的工作原理及其特殊结构。借助Ｔｓｐｉｃｅ和ＣＡＤ技术对电路设计和工艺过程中的实时参数进行模拟设计，使研制的高速缓冲器具有高速度、高精度和高可靠性。介绍了高速缓冲器在转换时间为６μｓ的１２位Ａ／Ｄ转换器中的应用情况。     

12bit10MS/s流水线结构模数转换器

介绍了12 bit,10 MS/s流水线结构的模数转换器IP核设计。为了实现低功耗,在采样电容和运放逐级缩减的基础上,电路设计中还采用了没有传统前端采样保持放大器的第一级流水线结构,并且采用了运放共享技术。瞬态噪声的仿真结果表明,在10 MHz采样率和295 kHz输入信号频率下,由该方法设计的ADC可以达到92.56 dB的无杂散动态范围,72.97 dB的信号噪声失调比,相当于11.83个有效位数,并且在5 V供电电压下的功耗仅为44.5 mW。     

Toward Wide-Band High-Resolution Analog-to-Digital Converters Using Hybrid Filter Bank Architecture

The paper presents the problem of design and simulation of a high-speed wide-band high-resolution analog-to-digital (ADC) converter working in a bandpass scenario. Such converters play a crucial role in software-defined radio and in cognitive radio technology. One way to circumvent the limits of today’s ADC technologies is to split the analog input signal into multiple components and then sample them with ADCs in parallel. The two main split approaches, time interleaved and frequency splitting, can be modeled using a filter bank paradigm, where each of these two architectures requires a specific analysis for its design. In this research, the frequency splitting approach was implemented with the use of a hybrid filter bank ADC, which requires an output digital filter bank perfectly matched to the input analog filter bank. To achieve this end, an analog transfer function, together with an assumption of strictly band-limited input signal, has been used to design the digital filter bank so far. In contrast, the author proposes dropping the band-limit assumption and shows that the out-of-band input signal has to be taken into account when designing a hybrid filter bank.     

A Comparison Design of Comb Decimators for Sigma-Delta Analog-to-Digital Converters

This paper presents a comparison design of comb decimators based on the non-recursive algorithm and the recursive algorithm. Compared with the recursive algorithm, the main advantage of the non-recursive algorithm is its abilities of reducing power consumption and increasing circuit speed especially when the decimation ratio and filter order are high. Based on the non-recursive algorithm, a decimator with programmable filter orders (3rd, 4th and 5th), decimation ratios (8, 16, 32 and 64) and input bits (1 and 2 bits) has been implemented in a 0.6 m 3.3 V CMOS process. Its measured core power consumption is 44 mW at the oversampling rate of 25 MHz and its highest input data rate is 110 MHz.     

A Use of Limit Cycle Oscillations to Obtain Robust Analog-to-Digital Converters

High quality analog-to-digital conversions are obtained using simple and inexpensive circuits that require no high-precision components. Samples of the analog signal are cycled rapidly through a coarse quantizer while the roundoff error is fed back and subtracted from the input. By means of this feedback, the coarse quantizations are caused to oscillate between levels, keeping their running average representative of the input. A binary coding of the quantized values, summed over Nyquist intervals, provides a high resolution PCM output. The precision is determined by a product of the cycle rate and the spacing of the coarse quantization levels. The system is surprisingly tolerant of inaccuracies in gains and threshold settings; indeed, it has many of the desirable properties of classical feedback servomechanisms. An 8-bit limit cycling converter intended for 1-MHz signal bandwidths has been fabricated of standard components that, in total, cost less than $150.     

Comparison of DEM and BEET Linearization Techniques for Flash Analog-to-Digital Converters

Data converter linearization has been a subject of some interest for most of the past decade. New methods of linearizing analog-to-digital converters (ADCs) continue to be developed. Various linearization methods are available but their comparative strengths and weaknesses are not easily recognizable, making it somewhat difficult to determine which compensator would provide maximum benefit for a specific device. This paper provides a novel performance comparison of two promising real-time linearization methods for flash ADCs: the in-device DEM method, and the peripherally-implemented BEET method using SFDR, SINAD, ENOB, and THD as performance metrics. It is found that BEET is the superior compensator for devices with INL values larger than 0.25 LSB and DNL values larger than 0.25 LSB for optimal SFDR. Results from SINAD, ENOB, and THD metrics indicate that BEET is superior compared to DEM for all devices that have INL>0.05 LSB.     

Application of the Kalman Filter in Linearity Testing of Analog-to-Digital Converters

This work introduces application of the Kalman Filter in linearity test of Analog-to-Digital Converters (ADCs). The Kalman Filter can be used to suppress errors in the histogram counts, based on characteristics of the test environment and the device under test, and achieve high accuracy within short test time. In this paper, appropriate system and noise models, and a corresponding form of the Kalman Filter are developed, while all necessary parameters are obtained from experimental measurements. Simulation and experiment results show that the INL _k test errors are reduced by more than 50% by applying the proposed method. Consequently, this method can achieve desired accuracy with significantly fewer samples as compared to the conventional algorithm, and shorten the linearity test time by a factor of four or higher. This method is valuable for effectively reducing the production test time and cost for ADCs.