Line ordering of reversible circuits for linear nearest neighbor realization

Real quantum computing technologies have different restrictions and constraints which need to be considered during circuit synthesis. In certain technologies, only physically adjacent qubits can interact, which restricts their realizations to only linear nearest neighbor (LNN) architecture. In this work, we formulate the line ordering problem in LNN architecture as task assignment problem to find a mapping (permutation) between task graph and processor graph with minimum cost. We propose two different approaches, a greedy heuristic and a meta-heuristic algorithm based on Harmony Search to solve the task assignment problem. Experimental results show that our algorithms were able to reduce the quantum cost of benchmark circuits by approximately 30 % on average. Moreover, the proposed algorithms were compared to one recently proposed ordering algorithm and were found to further improve the cost by approximately 16 %.     

Automatic synthesis of quaternary quantum circuits

Quaternary encoded binary circuits are more compact than their binary counterpart. Although quaternary reversible circuits are realizable, design of such circuits is still in its infancy. This work proposes a new, enhanced method of quaternary Galois field sum of products (QGFSOP) synthesis for quaternary quantum circuits. To reduce QGFSOP product terms, the algorithm makes use of 11 newly defined quaternary Galois field (QGF) expansions (for a total of 21 QGF expansions). This algorithm achieves QGFSOP minimization with the assistance of a pseudo-Kronecker Galois field decision diagram (QGFDD). This is a novel approach for QGFSOP synthesis. Finally, QGFSOP expressions are translated into quantum cost optimized quaternary quantum circuits using: (1) newly developed quaternary quantum gate realizations of controlled Feynman and Toffoli gate that are optimized in terms of quantum cost, (2) use of composite literals consisting of 1 digit and M–S gates. Performance evaluation against existing works in the literature determined that our proposed method achieves an average QGFSOP expression product term savings of 32.66 %. Also, the synthesized QGFSOP circuits were evaluated in terms of quantum cost.     

Multi-strategy based quantum cost reduction of linear nearest-neighbor quantum circuit

With the development of reversible and quantum computing, study of reversible and quantum circuits has also developed rapidly. Due to physical constraints, most quantum circuits require quantum gates to interact on adjacent quantum bits. However, many existing quantum circuits nearest-neighbor have large quantum cost. Therefore, how to effectively reduce quantum cost is becoming a popular research topic. In this paper, we proposed multiple optimization strategies to reduce the quantum cost of the circuit, that is, we reduce quantum cost from MCT gates decomposition, nearest neighbor and circuit simplification, respectively. The experimental results show that the proposed strategies can effectively reduce the quantum cost, and the maximum optimization rate is 30.61% compared to the corresponding results.     

Linear nearest neighbor optimization in quantum circuits: a multiobjective perspective

Several current implementations of quantum circuits rely on the linear nearest neighbor restriction, which only allows interaction between adjacent qubits. Most methods that address the process of converting a generic circuit to an equivalent circuit which satisfies this restriction, minimize the number of additional SWAP gates required by this process. Moreover, most methods which address this problem are designed for 1D circuits. Considering the new and promising proposals for 2D quantum circuits, what we propose is a new perspective on this problem, namely that it can be seen as a multiobjective optimization problem. To test our hypothesis, we developed a multiobjective evolutionary algorithm that solves this problem by considering two objectives: minimizing the size of the 2D grid where the circuit is placed, and minimizing the number of additional SWAP gates. Of the methods designed for 2D circuits, only one considers different grid sizes which are much larger than strictly necessary. Consequently, our algorithm makes considerations which other methods do not make, since it naturally finds the grid which requires fewer SWAP gates for the circuit conversion, whether it is one-dimensional or two-dimensional. Our experimental results indicate that allowing a larger grid size results in fewer additional SWAP gates in about 73% of the tested circuits. Additionally, the average improvement we found when using larger grid sizes is about 30%, while the best improvement over using the smallest possible grid is 63.8%.     

三值量子基本门及其对量子Fourier变换的电路实现

理论上可以把量子基本门组合在一起来实现任何量子电路和构建可伸缩的量子计算机。但由于构建量子线路的量子基本门数量庞大,要正确控制这些量子门十分困难。因此,如何减少构建量子线路的基本门数量是一个非常重要和非常有意义的课题。提出采用三值量子态系统构建量子计算机,并给出了一组三值量子基本门的功能定义、算子矩阵和量子线路图。定义的基本门主要包括三值量子非门、三值控制非门、三值Hadamard门、三值量子交换门和三值控制CR_k门等。通过把量子Fourier变换推广到三值量子态,成功运用部分三值量子基本门构建出能实现量子Fourier变换的量子线路。通过定量分析发现,三值量子Fourier变换的线路复杂度比二值情况降低了至少50%,表明三值量子基本门在降低量子计算线路复杂度方面具有巨大优势。     

Evolving quantum circuits at the gate level with a hybrid quantum-inspired evolutionary algorithm

This paper proposes an approach to evolve quantum circuits at the gate level, based on a hybrid quantum-inspired evolutionary algorithm. This approach encodes quantum gates as integers and combines the cost and correctness of quantum circuits into the fitness function. A fast algorithm of matrix multiplication with Kronecker product has been proposed to speed up the calculation of matrix multiplication in individuals evaluation. This algorithm is shown to be better than the known best algorithm for matrix multiplication when a certain condition holds. The approach of evolving quantum circuits is validated by some experiments and the effects of some parameters are investigated. And finally, some features of the approach are also discussed.     

Harmony-search algorithm for 2D nearest neighbor quantum circuits realization

Motivated by its promising applications, quantum computing is an emerging area of research. This paper addresses the NP-complete problem of finding Nearest Neighbor (NN) realization of quantum circuits on a 2-Dimensional grid. In certain quantum technologies, only physically adjacent qubits are allowed to interact with each other hence the need for NN requirement. Circuits with distant qubits are made NN-compliant by introducing swap gates, hence increasing cost. In this work, we present a Harmony Search (HS) based intelligent metaheuristic algorithm to efficiently realize low cost NN circuits utilizing input line reordering. The distinct feature of the proposed technique is that initial qubits placement is found using HS based metaheuristic followed by an efficient, problem-specific local heuristic to perform swap gate insertion. The effectiveness of the proposed algorithm is demonstrated by comparing its performance to a number of recent published approaches. Solutions found by the proposed technique show reduction in the number of swaps needed in the range of 4% – 36% on average when compared to state-of-the-art techniques. Compared to other approaches, the implemented algorithm is scalable and was able to find optimized circuits within 4 seconds in the worst case.     

A quantum watermarking scheme using simple and small-scale quantum circuits

A new quantum gray-scale image watermarking scheme by using simple and small-scale quantum circuits is proposed. The NEQR representation for quantum images is used. The image sizes for carrier and watermark are assumed to be \(2n \times 2n\) and \(n \times n\), respectively. At first, a classical watermark with \(n \times n\) image size and 8 bits gray scale is expanded to an image with \(2n \times 2n\) image size and 2 bits gray scale. Then the expanded image is scrambled to be a meaningless image by the SWAP gates that controlled by the keys only known to the operator. The scrambled image is embedded into the carrier image by the CNOT gates (XOR operation). The watermark is extracted from the watermarked image by applying operations in the reverse order. Simulation-based experimental results show that our proposed scheme is excellent in terms of three items, visual quality, robustness performance under noises, and computational complexity.     

On figures of merit in reversible and quantum logic designs

Five figures of merit including number of gates, quantum cost, number of constant inputs, number of garbage outputs, and delay are used casually in the literature to compare the performance of different reversible or quantum logic circuits. In this paper we propose new definitions and enhancements, and identify similarities between these figures of merit. We evaluate these measures to show their strength and weakness. Instead of the number of gates, we introduce the weighted number of gates, where a weighting factor is assigned to each quantum or reversible gate, based on its type, size and technology. We compare the quantum cost with weighted number of gates of a circuit and show three major differences between these measures. It is proved that it is not possible to define a universal reversible logic gate without adding constant inputs. We prove that there is an optimum value for number of constant inputs to obtain a circuit with minimum quantum cost. Some reversible logic benchmarks have been synthesized using Toffoli and Fredkin gates to obtain their optimum values of number of constant inputs. We show that the garbage outputs can also be used to decrease the quantum cost of the circuit. A new definition of delay in quantum and reversible logic circuits is proposed for music line style representation. We also propose a procedure to calculate the delay of a circuit, based on the quantum cost and the depth of the circuit. The results of this research show that to achieve a fair comparison among designs, figures of merit should be considered more thoroughly.      

基于正反控制门的可逆逻辑综合

提出一种基于正反控制(PNC)门可逆网络的级联算法,为3位输入/输出函数设计相应的模板,给出级联网络的约简算法。实验结果表明,与Toffoli门级联成的网络相比,使用PNC门的可逆网络中门的数量较少,在降低网络代价方面具有一定优势。     

Compact quantum gates for hybrid photon–atom systems assisted by Faraday rotation

We present some compact circuits for a deterministic quantum computing on the hybrid photon–atom systems, including the Fredkin gate and SWAP gate. These gates are constructed by exploiting the optical Faraday rotation induced by an atom trapped in a single-sided optical microcavity. The control qubit of our gates is encoded on the polarization states of the single photon, and the target qubit is encoded on the ground states of an atom confined in an optical microcavity. Since the decoherence of the flying qubit with atmosphere for a long distance is negligible and the stationary qubits are trapped inside single-sided microcavities, our gates are robust. Moreover, ancillary single photon is not needed and only some linear-optical devices are adopted, which makes our protocols efficient and practical. Our schemes need not meet the condition that the transmission for the uncoupled cavity is balanceable with the reflectance for the coupled cavity, which is different from the quantum computation with a double-sided optical microcavity. Our calculations show that the fidelities of the two hybrid quantum gates are high with the available experimental technology.     

Reversible circuit synthesis by genetic programming using dynamic gate libraries

We have defined a new method for automatic construction of reversible logic circuits by using the genetic programming approach. The choice of the gate library is 100% dynamic. The algorithm is capable of accepting all possible combinations of the following gate types: NOT TOFFOLI, NOT PERES, NOT CNOT TOFFOLI, NOT CNOT SWAP FREDKIN, NOT CNOT TOFFOLI SWAP FREDKIN, NOT CNOT PERES, NOT CNOT SWAP FREDKIN PERES, NOT CNOT TOFFOLI PERES and NOT CNOT TOFFOLI SWAP FREDKIN PERES. Our method produced near optimum circuits in some cases when a particular subset of gate types was used in the library. Meanwhile, in some cases, optimal circuits were produced due to the heuristic nature of the algorithm. We compared the outcomes of our method with several existing synthesis methods, and it was shown that our algorithm performed relatively well compared to the previous synthesis methods in terms of the output efficiency of the algorithm and execution time as well.     

Towards ultra-efficient QCA reversible circuits

Nanotechnologies, remarkably Quantum-dot Cellular Automata (QCA), offer an attractive perspective for future computing technologies. In this paper, QCA is investigated as an implementation method for reversible logic. A novel XOR gate and also a new approach to implement 2:1 multiplexer are presented. Moreover, an efficient and potent universal reversible gate based on the proposed XOR gate is designed. The proposed reversible gate has a superb performance in implementing the QCA standard benchmark combinational functions in terms of area, complexity, power consumption, and cost function in comparison to the other reversible gates. The gate achieves the lowest overall cost among the most cost-efficient designs presented so far, with a reduction of 24%. In order to employ the merits of reversibility, the proposed reversible gate is leveraged to design the four common latches (D latch, T latch, JK latch, and SR latch). Specialized structures of the proposed circuits could be used as building blocks in designing sequential and combinational circuits in QCA architectures.     

Synthesis of reversible circuits with minimal costs

We present fast algorithms to synthesize exact minimal reversible circuits for various types of gate and cost. By reducing reversible logic synthesis problems to permutation group problems, we use the powerful algebraic software GAP to solve such problems. Our approach can minimize for arbitrary cost functions of gates. In addition, we show that Peres gates are a better choice than the standard Toffoli gates in libraries of universal reversible gates. This work was supported by the NNSF of China under Grant 60773205 and the Fund of Cultivating Leading Scholars in UESTC.     

Novel parity-preserving reversible logic array multipliers

Reversible logic as a new promising design domain can be used for DNA computations, nanocomputing, and especially constructing quantum computers. However, the vulnerability to different external effects may lead to deviation from producing correct results. The multiplication is one of the most important operations because of its huge usage in different computing systems. Thus, in this paper, some novel reversible logic array multipliers are proposed with error detection capability through the usage of parity-preserving gates. By utilizing the new arrangements of existing reversible gates, some new circuits are presented for partial product generation and multi-operand addition required in array multipliers which results in two unsigned and three signed parity-preserving array multipliers. The experimental results show that the best of signed and unsigned proposed multipliers have the lowest values among the existing designs regarding the main reversible logic criteria including quantum cost, gate count, constant inputs, and garbage outputs. For \(4\times 4\) multipliers, the proposed designs achieve up to 28 and 46% reduction in the quantum cost and gate count, respectively, compared to the existing designs. Moreover, the proposed unsigned multipliers can reach up to 58% gate count reduction in \(16\times 16\) multipliers.     

Improved quantum ripple-carry addition circuit

A serious obstacle to large-scale quantum algorithms is the large number of elementary gates, such as the controlled-NOT gate or Toffoli gate. Herein, we present an improved linear-depth ripple-carry quantum addition circuit, which is an elementary circuit used for quantum computations. Compared with previous addition circuits costing at least two Toffoli gates for each bit of output, the proposed adder uses only a single Toffoli gate. Moreover, our circuit may be used to construct reversible circuits for modular multiplication, Cx mod M with x < M, arising as components of Shor’s algorithm. Our modular-multiplication circuits are simpler than previous constructions, and may be used as primitive circuits for quantum computations.     

Designing new ternary reversible subtractor circuits

The reducing of the width of quantum reversible circuits makes multiple-valued reversible logic a very promising research area. Ternary logic is one of the most popular types of multiple-valued reversible logic, along with the Subtractor, which is among the major components of the ALU of a classical computer and complex hardware. In this paper the authors will be presenting an improved design of a ternary reversible half subtractor circuit. The authors shall compare the improved design with the existing designs and shall highlight the improvements made after which the authors will propose a new ternary reversible full subtractor circuit. Ternary Shift gates and ternary Muthukrishnan–Stroud gates were used to build such newly designed complex circuits and it is believed that the proposed designs can be used in ternary quantum computers. The minimization of the number of constant inputs and garbage outputs, hardware complexity, quantum cost and delay time is an important issue in reversible logic design. In this study a significant improvement as compared to the existing designs has been achieved in as such that with the reduction in the number of ternary shift and Muthukrishnan-Stroud gates used the authors have produced ternary subtractor circuits.     

基于量子神经网络的油田水淹层识别方法

针对油藏测井解释中的水淹层识别问题,提出一种量子神经网络模型。该模型用量子旋转门更新量子比特的相位,用受控旋转门实现网络的非线性映射功能。网络可调参数为量子旋转门的旋转角度和受控非门的控制参数。基于梯度下降法设计了学习算法。仿真结果表明,该模型的预测能力优于普通BP网络、模糊神经网络和过程神经网络等其他方法。     

Upper bounds for reversible circuits based on Young subgroups

We present tighter upper bounds on the number of Toffoli gates needed in reversible circuits. Both multiple controlled Toffoli gates and mixed polarity Toffoli gates have been considered for this purpose. The calculation of the bounds is based on a synthesis approach based on Young subgroups that results in circuits using a more generalized gate library. Starting from an upper bound for this library we derive new bounds which improve the existing bound by around 77%.     

Efficient schemes for the quantum teleportation of a sub-class of tripartite entangled states

In this paper we propose two schemes for teleportation of a sub-class of tripartite states, the first one with the four-qubit cluster state and the second one with two Bell pairs as entanglement channels. A four-qubit joint measurement in the first case and two Bell measurements in the second are performed by the sender. Appropriate unitary operations on the qubits at the receiver’s end along with an ancilla qubit result in the perfect teleportation of the tripartite state. Analysis of the quantum circuits employed in these schemes reveal that in our technique the desired quantum tasks are achieved with lesser quantum cost, gate count and classical communication bits compared with other similar schemes.