Broadcast-and-select photonic ATM switch with frequency divisionmultiplexed output buffers

A photonic ATM switch has been developed with frequency division multiplexed (FDM) output buffers. The switch has a broadcast-and-select network architecture using fixed-frequency-channel transmitters and a passive star configuration. Although it has a simple structure, it can provide either broadcast or multicast switching. The output buffers, which resolve cell contentions, are comprised of fiber delay lines that can easily handle signal speed of over 10 Gb/s. Experimental switching of two-multiplexed 10 Gb/s cells with a 2.8-dB power penalty demonstrated high-speed switching     

Tandem-crosspoint ATM switch with input and output buffers

This letter proposes a high-speed input and output buffering asynchronous transfer mode (ATM) switch, named the tandem-crosspoint (TDXP) switch, The TDXP switch consists of multiple crossbar switch planes, which are connected in tandem at every crosspoint. The TDXP switch does not increase the internal line speed in eliminating head-of-line (HOL) blocking. In addition, since the TDXP switch employs a simple cell reading algorithm at the input buffer in order to retain the cell sequence, the TDXP switch does not require the cell sequences to be rebuilt at output buffers using time stamps, as is required by a parallel switch. It is shown that the TDXP switch can eliminate the HOL blocking effectively and achieve high throughput     

Design implementation of ATM switch with input priority anddistributed output buffers

A switch architecture for ATM is described which uses a simple priority module to resolve input contention and a distributed design to permit transfer of input cells to the first free output buffer. The switch has been synthesised using VHDL software and a target generic library and can operate at speeds >400 Mbit/s     

A multistage ATM switch with interstage buffers

Asynchronous transfer mode (ATM) is the transport technique for the broadband ISDN recommended by CCITT (I.121). Many switches have been proposed to accommodate the ATM that requires fast packet switching capability.^1-8 The proposed switches for the broadband ISDN can be classified as being of input queueing or output queueing type. Those of the input queueing type have a throughput performance which is approximately 58 per cent that of the output queueing type. However, output queueing networks require larger amounts of hardware than input queueing networks. In this paper, we propose a new multistage switch with internal buffering that approaches a maximum throughput of 100 per cent as the buffering is increased. The switch is capable of broadcasting and self-routeing. It consists of two switching planes which consist of packet processors, 2 x 2 switching elements, distributors and buffers located between stages and in the output ports. The internal data rate of the proposed switch is the same as that of the arriving information stream. In this sense, the switch does not require speed-up. The switch has log₂ N stages that forward packets in a store-and-forward fashion, thus incurring a latency of log₂ N time periods. Performance analysis shows that the additional delay is small.     

A smart photonic ATM switch architecture with compression strategy

Generally, the limitations of optical delay line and link capacity limit the switching efficiency in the photonic asynchronous transfer mode (ATM) switch. Under the constraints, a smart photonic ATM switch designed for high-speed optical backbone network should have some fast switching strategies so that the congestion can be avoided or reduced. In this paper, we mill propose a novel smart photonic ATM switch architecture with a novel compression strategy. In the smart architecture, while more than two frames are destined for the same destination, the losers will be queued and compressed to reduce the degree of congestion. Therefore, not only the total switching time (TST) can be reduced but also the scarce buffer is able to store more incoming cells. To meet the high-speed switching performance, a simple and efficient compression decision algorithm (CDA) is proposed. The timing of employing compression strategy and the saturated performance of proposed strategy are analyzed. Simulation results show that compared to the conventional photonic ATM switch without compression strategy, the proposed strategy offers a much better performance in terms of queueing delay     

A prototype broadcast-and-select photonic ATM switch with a WDMoutput buffer

A rack-mounted prototype of a broadcast-and-select (B and S) photonic ATM switch is fabricated. This switch has an optical output buffer utilizing wavelength division multiplexed (WDM) signals. The WDM technology solves. The cell-collision problem in a broadcast-and-select network and leads to a simple network architecture and the broadcast/multicast function. The prototype can handle 10-Gb/s nonreturn-to-zero (NRZ) coded cells and 5-Gb/s Manchester-coded cells and has a switch size of four. In this prototype, the level and timing design are key issues. Cell-by-cell level fluctuation is overcome by minimizing the loss difference between the optical paths and adopting a differential receiver capable of auto-thresholding. The temperature control of delay lines was successful in maintaining the phase synchronization. Using these techniques, we are able to provide a WDM highway with a bit error rate of less than 10^-12. Fundamental photonic ATM switching functions, such as optical buffering and fast wavelength-channel selection, are achieved. We show our experimental results and demonstrate the high performance and stable operation of a photonic ATM switch for use in high-speed optical switching systems as an interconnect switch for a modular ATM switch and an ATM cross-connect switch     

An ultrafast photonic ATM switch based on bit-interleavemultiplexing

An optical ATM switch is proposed in which cells from individual input channels are time-division multiplexed in a bit-interleave manner. This switch can easily handle multicast switching because it is based on a broadcast-and-select network. Compared to an alternative switch that uses a cell-interleave time-division multiplexing scheme, the proposed optical switch has a much simpler structure. It does not need a cell compressor at each input and a cell expander at each output, which greatly reduces hardware complexity. Feasibility analyzes showed that a 64×64 photonic ATM switch with 2.5 Gb/s input/output is possible using the proposed technology. In an experimental demonstration, 4 b cells were selected from a 55 Gb/s bit-interleave multiplexed cell stream by using a new nonlinear optical fiber switch. With its high switch throughput, our switch is a strong candidate for future large-capacity optical switching nodes     

Optical input buffers for the HiPower photonic ATM switch-analysisand experiments

We describe an optical input buffer for the HiPower photonic ATM switch. This buffer can control the cell throughput in accordance with back pressure signals and incoming optical cells. We analyze the cell loss probability of the optical input buffer. Only a small buffer size of five is needed to obtain a cell loss probability of less than 10^-15 with 1024 ports. Experimental 10 Gb/s operation using optical fiber delay lines with gate control circuits shows that the bit error rate of the buffer is less than 10^-12     

56 byte optical cell selection at 55 Gbit/s in bit-interleavemultiplexing photonic ATM switch

Experiments on selecting 56 byte optical cells out of a four-channel bit-interleave multiplexed 55 Gbit/s pulse stream are carried out using a nonlinear optical loop mirror (NOLM) including a chalcogenide glass fibre     

SLOB: a switch with large optical buffers for packet switching

Recently, optical packet switch architectures, composed of devices such as optical switches, fiber delay lines, and passive couplers, have been proposed to overcome the electromagnetic interference (EMI), pinout and interconnection problems that would be encountered in future large electronic switch cores. However, attaining the buffer size (buffer depth) in optical packet switches required in practice is a major problem; in this paper, a new solution is presented. An architectural concept is discussed and justified mathematically that relies on cascading many small switches to form a bigger switch with a larger buffer depth. The number of cascaded switches is proportional to the logarithm of the buffer depth, providing an economical and feasible hardware solution. Packet loss performance, control and buffer dimensioning are considered. The optical performance is also modeled, demonstrating the feasibility of buffer depths of several thousand, as required for bursty traffic     

A photonic front-end processor in a WDM ATM multicast switch

Dense wavelength-division multiplexing (DWDM) technology has provided tremendous transmission capacity in optical fiber communications. However, switching and routing capacity is still far behind transmission capacity. This is because most of today's packet switches and routers are implemented using electronic technologies. Optical packet switches are the potential candidate to boost switching capacity to be comparable with transmission capacity. In this paper, we present a photonic asynchronous transfer mode (ATM) front-end processor that has been implemented and is to be used in an optically transparent WDM ATM multicast (3M) switch. We have successfully demonstrate the front-end processor in two different experiments. One performs cell delineation based on ITU standards and overwrites VCI/VPI optically at 2.5 Gb/s. The other performs cell synchronization, where cells from different input ports running at 2.5 Gb/s are phase-aligned in the optical domain before they are routed in the switch fabric. The resolution of alignment is achieved to the extent of 100 ps (or 1/4 bit). An integrated 1×2 Y-junction semiconductor optical amplifier (SOA) switch has been developed to facilitate the cell synchronizer     

Design and performance of Multinet switch: a multistage ATM switcharchitecture with partially shared buffers

A new ATM switch architecture is presented. Our proposed Multinet switch is a self-routing multistage switch with partially shared internal buffers capable of achieving 100% throughput under uniform traffic. Although it provides incoming ATM cells with multiple paths, the cell sequence is maintained throughout the switch fabric thus eliminating the out-of-order cell sequence problem. Cells contending for the same output addresses are buffered internally according to a partially shared queueing discipline. In a partially shared queueing scheme, buffers are partially shared to accommodate bursty traffic and to limit the performance degradation that may occur in a completely shared system where a small number of calls may hog the entire buffer space unfairly. Although the hardware complexity in terms of number of crosspoints is similar to that of input queueing switches, the Multinet switch has throughput and delay performance similar to output queueing switches     

Sorting-based routing algorithms of a photonic ATM cell switch:HiPower

HiPower is a photonic ATM switch having a two-layered structure, consisting of an electrical control layer and an optical transport layer, realized by a detouring hypercube interconnection network structure. Four sorting-based routing algorithms suitable for high-speed hardware control of HiPower are proposed. They are evaluated by computer simulations in terms of delay and cell loss in the switch under uniform traffic distribution. The simulation results suggest that all four methods are acceptable in their traffic characteristics and that the DD method, in which the cell nearest to its destination is given the highest priority in routing, seems to be the most attractive from the hardware implementation viewpoint. It is also confirmed that subpriority sorting based on the number of detourings reduces the delay variance. Simulation results proving that the detouring hypercube network is a practical and powerful architecture for a two-layered ATM cell switch, thus, the HiPower providing high throughput, are given     

Self-clocked optical control of a self-routed photonic switch

Self-routing of 100-Mb/s data through a photonic switch is demonstrated. Individual data bits are subencoded into one of 124 destination addresses using a pulse-interval technique with 80-ps pulses. At the switch, optical processing is used to read the address of an incoming bit and to route that bit to the correct switch output without the aid of an external clock. Although the pulse-interval technique is presented in a bit-switching context, it can readily be extended to a packet-switching environment     

基于色散的ATM自由空间光交换结构

根据波导型光交换的一些弱点，提出了一类克服以上缺点的基于色散异步转移模式（ＡＴＭ）的自由空间光交换结构，并对该结构进行了一些讨论。     

Input and output queueing ATM switch architecture with spatial and temporal slot reservation control

A viable ATM switch architecture exploiting both input and output queueing on a space division switch is proposed. This architecture features both input and output ports that are divided into several groups, and an efficient contention resolution algorithm is developed. The performance study indicates that a group size of eight is sufficient to achieve 90% efficiency.<>     

Optical digital cross-connect system using photonic switch matricesand optical amplifiers

This paper presents, for potential application to network failure restoration, an optical digital cross-connect system (DCS) which uses both a photonic switching network and an electric DCS. It is shown that a system constructed of LiNbO₃ 8×8 switch matrices and semiconductor traveling-wave optical amplifiers (TWA's) could be applied to metropolitan area networks. An experimental optical DCS system has been designed and fabricated which incorporates both LiNbO₃ switch matrices and TWA's, and with it, line-failure restoration, a fundamental operation of optical DCS, has been successfully demonstrated     

Reliability analysis of an optical ATM switch based on wavelength routing

Reliability studies of a demonstrated asynchronous transfer mode (ATM) switch with all-optical packet routing are presented. Calculations are based on available reliability data for commercial components. An additional inherent redundancy is shown to improve switch availability. Our calculation results further show that a proposed multiplane switch satisfies the general reliability requirement for switching systems.     

Terahipas: a modular and expandable terabit/second hierarchicallymultiplexing photonic ATM switch architecture

A terabit/second hierarchically multiplexing photonic asynchronous transfer mode (ATM) switch network architecture, called Terahipas, is proposed. It combines the advantages of photonics (a large bandwidth for transport of cells) and electronics (advanced logical functions for controlling, processing, and routing). It uses a hierarchical photonic multiplexing structure in which several tens of channels with a relatively low bit rate, say 2.4 Gb/s, are first time-multiplexed on an optical highway by shrinking the interval between optical pulses, then a number of optical highways are wavelength-multiplexed (or space-division multiplexed). As a result, the switch capacity can be expanded from the order of 100 Gb/s to the order of 10 Tb/s in a modular fashion. A new implementation scheme for cell buffering is used for eliminating the bottleneck when receiving and storing concurrent optical cells at bit rates as high as 100 Gb/s. This new architecture can serve as the basis of a modular, expandable, high-performance ATM switching system for future broad band integrated service digital networks (B-ISDN's)