低电压低功耗CMOS采样保持电路

设计了一个用于流水线型模数转换器的低压采样保持电路。为降低采保电路中运放的功耗,本文采用了增益补偿的采样保持电路结构,从而用简单的低增益运放达到高精度的效果。并从运放输出建立时间的角度对其输入电流进行优化。为了提高精度,降低采样开关的电阻并减小非线性误差,设计了信号相关自举电压控制的开关。仿真结果表明在1．8V的电源电压下,达到10bit的精度和50Mbit的采样率,整个采保电路的功耗仅为2．3mW。     

快速稳定的CMOS电荷泵电路的设计

基于交叉耦合NMOS单元,提出了一种低压、快速稳定的CMOS电荷泵电路.一个二极管连接的NMOS管与自举电容相并联,对电路进行预充电,从而改善了电荷泵电路的稳定建立特性.PMOS串联开关用于将信号传输到下一级.仿真结果表明,4级电荷泵的最大输出电压为7.41 V,建立时间为0.85 μs.     

The Impact of Gate-Oxide Breakdown on Common-Source Amplifiers With Diode-Connected Active Load in Low-Voltage CMOS Processes

The influence of gate-oxide reliability on common-source amplifiers with diode-connected active load is investigated with the nonstacked and stacked structures under analog application in a 130-nm low-voltage CMOS process. The test conditions of this work include the dc stress, ac stress with dc offset, and large-signal transition stress under different frequencies and signals. After overstresses, the small-signal parameters, such as small-signal gain, unity-gain frequency, phase margin, and output dc voltage levels, are measured to verify the impact of gate-oxide reliability on circuit performances of the common-source amplifiers with diode-connected active load. The small-signal parameters of the common-source amplifier with the nonstacked diode-connected active-load structure are strongly degraded than that with the stacked diode-connected active-load structure due to a gate-oxide breakdown under analog and digital applications. The common-source amplifiers with diode-connected active load are not functionally operational under digital application due to the gate-oxide breakdown. The impact of soft and hard gate-oxide breakdowns on the common-source amplifiers with nonstacked and stacked diode-connected active-load structures has been analyzed and discussed. The hard breakdown has more serious impact on the common-source amplifiers with diode-connected active load.     

Design of Mixed-Voltage-Tolerant Crystal Oscillator Circuit in Low-Voltage CMOS Technology

In the nanometer-scale CMOS technology, the gate-oxide thickness has been scaled down to provide higher operating speed with lower power supply voltage. However, regarding compatibility with the earlier defined standards or interface protocols of CMOS ICs in a microelectronics system, the chips fabricated in the advanced CMOS processes face the gate-oxide reliability problems in the interface circuits due to the voltage levels higher than normal supply voltage (1$,times,$ VDD) required by earlier applications. As a result, mixed-voltage I/O circuits realized with only thin-oxide devices had been designed with advantages of less fabrication cost and higher operating speed to communicate with the circuits at different voltage levels. In this paper, two new mixed-voltage-tolerant crystal oscillator circuits realized with low-voltage CMOS devices are proposed without suffering the gate-oxide reliability issues. The proposed mixed-voltage crystal oscillator circuits, which are one of the key I/O cells in a cell library, have been designed and verified in a 90-nm 1-V CMOS process, to serve 1-V/2-V tolerant mixed-voltage interface applications.      

低压低功耗电流模CMOS带隙基准电路

提出了一种解决电流模带隙基准电路的第三简并态问题的处理方法,设计了一个完整的低压低功耗带隙电路.通过在电路启动时关断导致产生第三简并态的电流通道并监测电路关键节点电压的方法,控制电路的启动过程,使电路在启动时避开第三简并态,进入正常工作状态.HSPICE仿真结果显示,该电路的输出基准电压为793.6 mV,温度漂移系数可低达10 ppm/℃,电源电压大于1 V即可正常工作;在电源电压为1.5 V时,功耗小于5 μW.     

Low-Voltage Linearly Tunable CMOS Transconductor With Common-Mode Feedforward

This paper presents a new low-voltage pseudodifferential continuous-time CMOS transconductor for wide-band applications. The proposed cell is based on a feedforward cancellation of the input common-mode signal and keeps the input common mode voltage constant, while the transconductance is easily tunable through a continuous bias voltage. Linearity is preserved during the tuning process for a moderate range of transconductance values. Measurements results for a 0.35-m CMOS design show a 1:2 tuning range with total harmonic distortion figures at 10 MHz below 58 dB over the whole range up to a 200- differential output current. The proposed cell consumes less than 1.1 mW from a single 1.8-V supply.     

Low-Voltage Bootstrapped CMOS Drivers With Efficient Conditional Bootstrapping

In this paper, a set of low-voltage bootstrapped CMOS drivers are presented to reduce power consumption and improve switching speed for driving a large capacitive load. The proposed drivers can reduce the power consumption by making bootstrap operations conditional to input statistics. They also improve switching speed by providing larger bootstrap voltages for the same amount of integrated bootstrap capacitance as compared with conventional bootstrapped drivers. The proposed drivers were designed using 0.18- CMOS technology. The comparison results indicate that the proposed drivers achieve power savings up to 97% with 13%-22% improvements on switching speed as compared with the conventional design.     

一种高性能CMOS电荷泵的设计

设计了一种用于电荷泵锁相环的CMOS电荷泵电路。电路中采用3对自偏置高摆幅共源共栅电流镜进行泵电流镜像,增大了低电压下电荷泵的输出电阻,实现了上下两个电荷泵的匹配。为消除单端电荷泵存在的电荷共享问题,引入了带宽幅电压跟随的半差分电流开关结构,使电荷泵性能得以提高。设计采用0.18μm标准CMOS工艺。电路仿真结果显示,在0.35～1.3V范围内泵电流匹配精度达0.9%,电路工作频率达250MHz。     

一种基于电荷泵的CMOS图像传感器

提出一种基于电荷泵的CMOS图像传感器.使用一个基本的电荷泵电路提高重置脉冲信号的幅值至5.8 V,使像素单元中的充电节点电压在充电周期可以达到电源电压;同时调整像素单元中的源极跟随器的参数,降低充电节点电压在积分周期的摆动范围下界,充电节点电压的摆幅提高了53.8%,传感器的动态范围提高了3.74 dB.这种方案也减小了充电时间常数,使充电周期减小到10 ns,有效地提高了传感器的图像采集帧率.     

一种低功耗射频CMOS电荷泵锁相环的设计

描述了基于P型CSL(Current Steer Logic)架构压控振荡器的低功耗射频锁相环设计.其鉴频鉴相器模块采用预充电模式,具有高速、无死区等特点;电荷泵模块在提高开关速度的基础上,改进了拓扑结构,使充放电电流的路径深度相同,更好地实现了匹配;为了达到宽调谐范围的目的,电荷泵模块采用1.8 V电源电压,而压控振荡器模块采用3.3 V,这样可充分利用电荷泵的输出电压范围实现宽调谐.电路设计基于0.18μm 1P6M CMOS工艺,芯片实测结果显示,锁相环工作在940 MHz～2.23 GHz的频率范围内,功耗低于15.2mW,芯片面积为750μm×400μm(不包括10).     

一种高性能CMOS电荷泵的设计

设计了一种用于电荷泵锁相环的CMOS电荷泵电路。电路中采用三对自偏置高摆幅共源共栅电流镜进行泵电流镜像,增大了低电压下电荷泵的输出电阻,并实现了上下两个电荷泵的匹配。为了消除单端电荷泵存在的电荷共享问题,引入了带宽幅电压跟随的半差分电流开关结构,使电荷泵性能得以提高。设计采用0．18-μm标准CMOS工艺。电路仿真结果显示,在0．35V到1．3V范围内泵电流匹配精度达0．9％,电路工作频率达250MHz。     

电荷泵电路的动态分析

详细分析了电荷泵的动态工作特性 ,给出了电荷泵电压上升时间及瞬态电流与电路的关系。基于这些分析 ,可以得到电荷泵的功耗来源和电压上升与充电电容的关系 ,同时还对电荷泵电路的电压产生的限制作出了分析。文末给出了整个分析结果与 SPICE模拟结果的对照 ,从结果可以看出整个分析大致反应了电荷泵的实际工作情况 ,正确地体现了电荷泵的工作原理。     

一种CMOS低压带隙基准电路的分析与设计

不同于常规电压求和带隙基准,电流求和是实现低压基准的主要方法.文章重点分析了一种负温度系数电流的生成方法,基于电流求和模式,设计了一种简单且无运放的电压基准结构,其输出最大基准值为1.1V,功耗为7μA.     

一种采用齐纳管作为开关器件的Dickson电荷泵电路

文章提出了一种基于Dickson原理的电荷泵电路,采用齐纳管作为开关器件。该电路克服了采用MOS管作为开关器件的Dickson电路在多级级联时的转换效率急剧下降问题,并且可以利用齐纳管来稳定输出电压。Spice仿真结果显示,五级齐纳电荷泵可以轻松在3V电源电压下实现10V左右的稳定电压输出。该电路结构简单,与标准CMOS工艺兼容,具有较高的应用价值和经济价值。     

一种锁相环中高性能电荷泵电路

设计了一种新型电荷泵电路.该电荷泵电路采用可调节共源共栅结构增大输出阻抗,具有结构简单、速度快、充放电电流匹配性好、抑制了电荷注入等特点.采用0.18μmCMOS工艺模型以及Hspice仿真工具的仿真结果显示,输出电压在0.4~1.3V之间变化时,电荷泵的充放电电流处处相等.     

一种用于LCD驱动的电荷泵电路

基于GSMC0.18μm±9VCMOS三阱工艺,设计了一种用于LCD驱动的正、负压电荷泵电路。该电荷泵采用共享耦合电容的结构并,结合了一种新的衬底偏置技术,在较小的面积代价下,可达到较强的驱动能力和较高的效率。测试结果表明,该电荷泵在1mW的输出功率下,效率可达到60%,而电路面积仅为0.51mm2。     

基于低压CMOS工艺的新型负电压型电荷泵电路

采用UMC 0.18 μm 1.8 V/3.3 V CMOS工艺设计并流片验证了一个应用于生医刺激器的新型负电压型电荷泵电路.介绍了几种典型的负电压型电荷泵电路,比较其优缺点,在此基础上设计了一个新型4级交叉耦合型负电压电荷泵.和现有的结构相比,该电路在启动过程和工作过程中都不存在过压问题,器件任意两端口之间的电压均小于电源电压VDD,同时降低了MOS器件衬底效应、反向漏电流对电荷泵效率的影响.电荷泵的电容采用MIM电容,升压电容为50 pF,输出电容为100 pF.芯片面积为2.3 mm×1.3 mm,测试结果表明负电压型电荷泵电路输出电压为-10.3 V,系统最高效率为56％.当输出电流为3.5 mA时,输出电容为100 pF时,纹波电压为150 mV.     

CMOS电荷泵锁相环中鉴频鉴相器的研究与设计

介绍了鉴频鉴相器(PFD)在其发展过程中产生的结构,并对每一种结构的优缺点进行了比较。通过对原有PFD电路结构进行重新设计,在传统D触发器PFD的基础上提出了两种新型PFD:传输门D触发器型PFD和基于锁存器的PFD。电路设计基于TSMC公司的0.18μm CMOS工艺,仿真环境为Candence Spectre,仿真结果显示电路可以工作在2GHz以上频率的应用环境下。相对于传统的PFD,新型PFD工作频率高、几乎无死区,而且具有噪声低、速度快的优点,在高速、低抖动、低噪声PLL中将有广泛的应用前景。     

A Sub-Micron CMOS Programmable Charge Pump for Implantable Pacemaker

In pacemaker design the mainconcerns are reliability, functionality,operating life and miniaturization. Afundamental role in miniaturization is dueto the increased circuit integration; hencelow power circuit solutions that can beintegrated in sub-micron CMOS technology arehighly desirable. This work proposes avoltage multiplier suitable for pulse outputgeneration in an implantable pacemaker,implemented in a standard, low-cost CMOS 0.8 m technology. The circuit can operatewithin a supply voltage range of 2.8 V to 2V, corresponding to the voltage capabilityprovided by the single lithium iodine cell,ubiquitously used in pacemaker. Fineprogrammability of the output has beenachieved, thus allowing the choice of theoptimum tradeoff between stimulationefficacy and battery longevity. Moreover theproposed solution takes care of minimizingthe parasitic coupling and disturbancesbetween the charge pump and other blocks inthe system. Finally the measured steady statecurrent consumption is smaller than .     

基于物理并适用于电路仿真的多晶硅薄膜晶体管薄层电荷模型

本文利用薄层电荷理论,建立了一个基于表面势的、物理的多晶硅薄膜晶体管(Polysilicon Thin-Film Transistors,poly-Si TFTs)的电流模型,且该模型适用于电路仿真.推导了 poly-Si TFTs 表面势的近似解法,该求解法非迭代的计算大大地提高了计算效率,且精确度高并得到实验验证.基于物理的迁移率方程考虑了晶界势垒高度,和由于声子散射与表面粗糙散射引起的迁移率退化.基于 Brews 的薄层电荷模型和上述非迭代计算表面势,本电流模型同时考虑了漏致势垒降低(DIBL)效应、kink 效应和沟道长度调制效应.对不同沟长的器件实验数据比较发现,提出的模型在很广的工作电压内与实验数据符合得非常好.同时本模型的所有方程都具有解析形式,电流方程光滑连续,适用于电路仿真器如 SPICE.