A bio-physically inspired silicon neuron

The physical principles governing ion flow in biological neurons share interesting similarities to electron flow through the channels of MOSFET transistors. Here, is described a circuit which exploits the similarities better than previous approaches to build an elegant circuit with electrical properties similar to real biological neurons. A two-channel model is discussed including sodium (Na/sup +/) and potassium (K/sup +/). The Na/sup +/ channel uses four transistors and two capacitors. The K/sup +/ channel uses two transistors and one capacitor. One more capacitor simulates the neuron membrane capacitance yielding a total circuit of four capacitors and six transistors. This circuit operates in real-time, is fabricated on standard CMOS processes, runs in subthreshold, and has a power supply similar to that of real biology. Voltage and current responses of this circuit correspond well with biology in terms of shape, magnitude, and time.     

Multiphysics neuron model for cellular volume dynamics

Even though cellular volume dynamics has been linked to cell apoptosis and intrinsic optical signals, there is no quantitative model for describing neuronal volume dynamics on the millisecond time scale. This study introduces a multiphysics neuron model, where the cell volume is a time-varying variable and multiple physical principles are combined to build governing equations. Using this model, we analyzed neuronal volume responses during excitation, which elucidated the variety of optical signals observed experimentally across the literature. Several physiological conditions were examined to investigate their effect on the pattern of volume response. In addition, we analyzed volume responses on a longer time scale with repetitive stimulation to study the characteristics of slow cell swelling. This multiscale analysis of the multiphysics model will provide not only a novel quantitative elucidation of physiologically important issues related with cellular volume dynamics but also a chance for further studies, such as the interesting possibility of inferring the balance of ion flux from plateau volume changes.     

Artificial neuron synapse transistor based on silicon nanomembrane on plastic substrate

Silicon nanomembrane (SiNM) transistors gated by chitosan membrane were fabricated on plastic substrate to mimic synapse behaviors. The device has both a bottom proton gate (BG) and multiple side gates (SG). Electrical transfer properties of BG show hysteresis curves different from those of typical SiO₂ gate dielectric. Synaptic behaviors and functions by linear accumulation and release of protons have been mimicked on this device:excitatory post-synaptic current (EPSC) and paired pulse facilitation behavior of biological synapses were mimicked and the paired-pulse facilitation index could be effectively tuned by the spike interval applied on the BG. Synaptic behaviors and functions, including short-term memory and long-term memory, were also experimentally demonstrated in BG mode. Meanwhile, spiking logic operation and logic modulation were realized in SG mode.     

A sensitivity matched multicarrier modulation

We develop a multicarrier modulation scheme for transmission of compressed data. The energy allocation among subcarriers is optimized by minimizing a modified symbol error function in either AWGN or Rayleigh fading channels. It is observed that our sensitivity matched multicarrier modulation significantly outperforms the conventional multi carrier modulation. The performance gain in Rayleigh fading channels varies from 0.58 to 3.26 dB depending upon the relative sensitivity of bit groups associated with subchannels     

Dislocation-mediated plasticity in silicon during nanometric cutting: A molecular dynamics simulation study

The nucleation and propagation of dislocations and its consequence on the defect structure in silicon during nanometric cutting are not well known, although the amorphization and high pressure phase transformation studies on silicon have remained at the epicentre of research across various disparate disciplines for over a decade. This paper proposes a new mechanism of crystal plasticity identified by a fully automated dislocation extraction algorithm in molecular dynamics simulations of nanometric cutting of silicon for different cutting planes/directions at a wide range of temperatures (300–1500 K). Alongside amorphization of silicon, our simulations revealed nanoscale stochastic nucleation of dislocations and stacking faults, which serve as mediators of microscopic plasticity during various contact loading operations and manufacturing processes of silicon. Of interest is that, irrespective of the cutting temperature, the stacking faults, which were not formed for either the (010)[100] or (111)[$\bar{1}1$0] crystal setups, were generated with three atomic layers in the (110)[00$\bar{1}$] cutting.     

A two-dimensional RAKE receiver architecture with an FFT-based matched filtering

This work proposes a two-dimensional (2-D) RAKE receiver, which is a spatial-temporal matched filter implemented in the frequency domain. To form a beam pattern, we calculate the spatial frequency spectra of received signals on the antenna array using fast Fourier transform (FFT). After FFT beamforming, a bank of FFT-based matched filters is used to perform code matching. Afterward, the code-matched signals are summed up with maximal-ratio combining through a spatial-temporal channel-matched filter implemented in the frequency domain. This 2-D RAKE receiver includes a channel sounder that is used to estimate the spatial and temporal channel impulse response parameters, such as delays, directions of arrivals, and complex gains of multipath components. Monte Carlo simulations have been used to evaluate the receiver bit-error rate performance in both static channel and mobile radio channel environments. Simulation results show that the RAKE receiver performs well in both kinds of channels.     

A family of pulse-shaping filters with ISI-free matched andunmatched filter properties

The raised-cosine pulse-shaping filter plays an important role in digital communications due to its intersymbol interference (ISI)-free property. The ISI-free property holds after matched filtering is performed. In this letter, we propose a new family of pulse-shaping filters. These filters are ISI free with or without matched filtering. Using these new pulse-shaping filters, the computational load, and therefore the hardware cost in demodulation for modem design, might be reduced in some applications     

A study of frequency response in silicon heterojunction bipolartransistors with amorphous silicon emitters

A detailed physical model of amorphous silicon (a-Si:H) is incorporated into a two-dimensional device simulator to examine the frequency response limits of silicon heterojunction bipolar transistors (HBT's) with a-Si:H emitters. The cutoff frequency is severely limited by the transit time in the emitter space charge region, due to the low electron drift mobility in a-Si:H, to 98 MHz which compares poorly with the 37 GHz obtained for a silicon homojunction bipolar transistor with the same device structure. The effects of the amorphous heteroemitter material parameters (doping, electron drift mobility, defect density and interface state density) on frequency response are then examined to find the requirements for an amorphous heteroemitter material such that the HBT has better frequency response than the equivalent homojunction bipolar transistor, We find that an electron drift mobility of at least 100 cm² V^-1 s^-1 is required in the amorphous heteroemitter and at a heteroemitter drift mobility of 350 cm ² V^-1 s^-1 and heteroemitter doping of 5×10¹⁷ cm^-3, a maximum cutoff frequency of 52 GHz can be expected     

Virtual assembly with biologically inspired intelligence

This paper investigates the introduction of biologically inspired intelligence into virtual assembly. It develops a approach to assist product engineers making assembly-related manufacturing decisions without actually realizing the physical products. This approach extracts the knowledge of mechanical assembly by allowing human operators to perform assembly operations directly in the virtual environment. The incorporation of a biologically inspired neural network into an interactive assembly planner further leads to the improvement of flexible product manufacturing, i.e., automatically producing alternative assembly sequences with robot-level instructions for evaluation and optimization. Complexity analysis and simulation study demonstrate the effectiveness and efficiency of this approach.     

飞秒激光与硅的相互作用过程理论研究

理解超短激光与材料的相互作用过程与机理是开展超短激光加工等工程应用的基础。首先引入电子激发项、双光子吸收、俄歇复合项等改进双温,使其较准确地适应于飞秒激光与半导体硅材料的相互作用过程。然后,分析了热损伤效应和非热损伤效应的影响。最后,开展了双脉冲飞秒激光与硅的相互过程研究,并分析了电子密度、晶格温度对于损伤积累效应的影响。理论模型得到单脉冲激光损伤阈值为0.25 J/cm2,此时主要表现为热损伤;当入射能量密度大于0.53 J/cm2 时,主要表现为非热损伤。双脉冲激光作用表明,脉冲间隔不大于100 ns（激光重频10 MHz）表现出明显的热积累效应,并显著降低损伤阈值。此时,第一个脉冲造成的电子密度升高（1026/m3）对损伤的贡献较小;而第一个脉冲引起的晶格温升将导致极高的电子激发以及晶格温升（800 K）,对损伤起主要贡献作用。该研究对于激光微加工、激光防护等领域具有参考意义。     

A matched filter design by charge-domain operations

This paper describes a novel matched filter (MF) design and its basic operations. The MF is based on the charge-domain operations that have a very simple structure compared to ordinary designs. To investigate the charge transfer characteristics and operations of correlator circuits that compose the MF, prototype designs are made by standard CMOS and fabricated by MOSIS 1.5 u, double overlapping poly, and double metal technology. The power consumption of the fabricated design was 7.0 pJ/Sample/tap. This value should be 1/10 of that of the current state of the art switched capacitor MF design, given that the same process technology was applied to both. Circuit area was 0.151 mm2/tap and this is also 1/2 of that of switched capacitor designs of the same technology. The correlator circuit of the new MF is composed of several steps of charge transfer operations. Hence, no special fabrication process such as those used for CCD imager is required. The detailed structure and operation of the correlator is explained.     

A silicon integrated strain-gage transducer with high linearity

The disadvantages of semiconductor strain-gage transducers are nonlinearity and temperature sensitivity. Using a monolithic integrated circuit Wheatstone bridge on a silicon cantilever enables linearization by variation of the location or width of the sensing devices. Excellent temperature stability is achieved by the integration itself and an additional external resistor.     

Multilayer microstrip structure analysis with matched loadsimulation

This paper presents a generalized approach to the full-wave analysis of multilayer microstrip structures. One of the structures studied is a new kind of microstrip bandpass filter realized in a double-layer dielectric substrate configuration. This filter demonstrates the use of the third (vertical) dimension in the design of microstrip devices. The approach involves the mixed potential integral equation technique, the Method of Moments, and an S-parameter extraction technique based on a simple form of Matched Load Simulation. Simulated and measured results for various microstrip structures are presented and show good agreement. The approach is demonstrated in detail for 2-port structures, with an outline of how it can readily be extended to the n-port case     

A mode-preserving perfectly matched layer for optical waveguides

For numerical simulation of wave propagation in optical waveguides, we develop a mode-preserving boundary condition for the popular perfectly matched layer, which truncates the unbounded transverse plane. The method is particularly useful for single-mode longitudinally varying wave-guiding structures and it is easy to use for step-index planar waveguides. With this boundary condition, accurate numerical solutions can be obtained in a much smaller computational window. Numerical results based on the beam propagation method for a tapered waveguide are used to demonstrate the capacity of this boundary condition.     

A graphic design method for matched low-noise amplifiers

A graphic design method for matched low-noise amplifiers is presented in which all necessary design information is given in the load plane. It is possible to work exclusively in the load plane, as the input-matching requirement makes the source admittance dependent on the load admittance. As a consequence of the bilinear transformation involved, all parameters may be presented by circles. Analytic equations giving the centers and the radii of the circles in the load plane are presented. Two kinds of amplifier configurations are considered: a single-stage amplifier with an input-match requirement and a two-stage cascade amplifier. The latter is required to have an output match and noise-optimized second stage, in addition to an input match. For the single-stage case the noise figure, the power gain, the stability, and the input network are treated. In the cascade design, the total noise figure, the interstage network, and the available gain are treated as well. A design example for the case of lossless feedback is presented     

A silicon phototransistor with a MIS tunnel junction emitter

We have fabricated a silicon phototransistor using low-temperature processing. The emitter of the bipolar transistor is an Al-SiO2-p-Si tunnel junction. The quantum efficiency gain is 200 at λ = 0.6328 µm. The common-emitter current gain of the analogous three-terminal metal-insulator-semiconductor (MIS) transistor also is 200. This demonstrates the high minority-carrier injection efficiency of the MIS emitter.     

A polycrystalline silicon thin-film transistor with a thinamorphous buffer

We have developed a novel, low off-state leakage current polycrystalline silicon (poly-Si) thin-film transistor (TFT) by introducing a very thin hydrogenated amorphous silicon (a-Si:H) buffer on the poly-Si active layer. The a-Si:H buffer is formed on the whole poly-Si and thus no additional mask step is needed. With an a-Si:H buffer on poly-Si, the off-state leakage current of a coplanar TFT is remarkably reduced, while the reduction of the on-state current is relatively small. The poly-Si TFT with an a-Si:H buffer exhibited a field effect mobility of 12 cm²/Vs and an off-state leakage current of 3 fA/μm at the drain voltage of 1 V and the gate voltage of -5 V     

A 2.4-GHz silicon bipolar oscillator with integrated resonator

A 2.4 GHz fully-monolithic silicon-bipolar oscillator circuit implemented in a 12 GHz BiCMOS technology is presented. The integrated resonator circuit uses three different versions of a 2 nH multilevel inductor and a wideband capacitive transformer. The measured Q factor is 9.3 for the three-level inductor. An oscillator phase noise of -78 dBc/Hz is achieved at 20 kHz offset. The circuit dissipates 50 mW from a 3.6 V supply     

A silicon quantum wire transistor with one-dimensional subband effects

A silicon quantum wire transistor, in which electrons are transported through a very narrow wire, has been fabricated using silicon-on-insulator technology, electron beam lithography, anisotropic dry etching, and thermal oxidation. We have obtained the quantum wire with a width of 65 nm, which is fully embedded in silicon dioxide. This narrow dimension of the wire and large potential barrier between silicon and silicon dioxide make the electrons moving through the wire experience one-dimensional confinement. The step-like structure in the conductance versus gate voltage curve, which is a typical evidence of one-dimensional conductance, has been observed at temperatures below 4.2 K. A period of step appearance and a step size have been analyzed to compare experimental characteristics with theoretical calculation.     

A 1.9-GHz silicon receiver with monolithic image filtering

A 1.9-GHz fully monolithic silicon superheterodyne receiver front-end is presented; it consists of a low noise amplifier (LNA), a tunable image reject filter, and a Gilbert cell mixer integrated in one die. The receiver was designed to operate with a 1.9-GHz RF and a 2.2-GHz local oscillator (LO) for a 300-MHz IF. Two chip versions were fabricated on two different fabrication runs using a 0.5-μm bipolar technology with 25 GHz transit frequency (f_T). Measured performance for the receiver front-end version 1, packaged and without input matching, was: conversion gain 33.5 dB, noise figure 4.9 dB, input IP3 -28 dBm, image rejection 53 dB (tuned to reject a 2.5-GHz image frequency), and 15.9 mA current consumption at +3 V. The image rejection was tunable from 2.4-2.63 GHz by means of an on-chip varactor. Version 2 had increased mixer degeneration for improved linearity. Its measured performance for the packaged receiver with its input matched to 50 Ω was: conversion gain 24 dB, noise figure 4.8 dB, input IP3 -19 dBm, and 65 dB image rejection for a 2.5-GHz image with an image tuning range from 2.34-2.55 GHz