平板显示器中应用ACF的驱动IC封装技术

文章叙述了ACF（Anisotropic Conductive Film,各向异性导电膜）与驱动IC（Integrated Circuit,集成电路）芯片封装的历史,并强调了驱动IC封装在实现显示器微型化、高分辨率、低成本及高显示质量等方面的重要性。文章还对微细间距COF（Chip on Flex）连接用ACF的材料设计进行了介绍。文章指出低温固化ACF可以改善LCD（Liquid Crystal Display,液晶显示屏）模块的生产效率,降低大型LCD模块表面的热应力;同时指出COG（Chip on Glass）连接后LCD面板的翘曲变形引起LCD模块漏光事故。ACF焊接温度的降低可以有效减少翘曲变形,避免在应用COG封装大型LCD模块的驱动IC时所产生漏光。     

简单类COG产品电显异常的一种成因分析

通过严格的失效分析步骤,借助于切片分析手段,找到了IC的一种设计或制造缺陷。原因是IC切割线外的测试焊盘在切割不良时会有毛刺,毛刺在COG邦定过程中通过ACF的导电粒子与ITO电极发生了短路,从而导致显示异常。     

高密度封装进展之一元件全部埋入基板内部的系统集成封装（上）

将无源元件及IC等全部埋入基板内部的三维封装,不仅能提高电子设备的整体性能,有利于轻薄短小化,而且 由于钎焊连接部位减少,可提高可靠性并能有效降低封装的总价格。     

电子元件的复合化和印制板埋置元件化发展

当前，电子设备向轻薄小型化和多功能高性能化发展，使电子元件与印制板发生了很大变化．具体体现在IC封装尺寸微型化和三维化，无源元件小型贴片化、复合化和埋置于印制扳内，埋置无源与有源元件印制板被开发应用等。     

用于电子元件装联自动化的焊接技术

最近,随着组成电子设备的印制板装联技术的FA化,出现了总价格降低的倾向。此外,装联技术等周边技术的发展使印制板焊接处理需求多样化。这样焊接技术和装置的革新更加强烈了。在印制电路板上元件的片状化、混合IC化的进展,SMT的出现加快了电子设备的轻薄短小化,复合功能化和高可靠性化的步伐。此外,正如以大型计算机为主的高速数字化技术受多层板技术所支配那样,印制电路和基板的综合技术的发展,以及     

IC载板的制造工艺与设备特征

1 设计因素 IC载板的设计完全是为符合芯片与封装方式的要求,有关电路布线与互连是由IC设计师们所完成的,对于制造者更关注的是与IC载板制造密切相关的设计因素。在当前数字化时代所追求的PCB(包括常规PCB和IC载板)是轻薄短小、高速化、高密度化和多功能化,具体为薄型、细线、小孔、尺寸精确与性能稳定以及低成本化。 设计考虑因素主要为板子功能性、可生产     

PCB印制电路板的安全稳定性设计

在电子行业中PCB是一个不可缺少的重要支柱,先进电路板设计技术将向着安全、稳定性、高密度、高可靠性和轻薄精小化迈进,PCB是高端电子设备的最关键技术,因而PCB电路板的安全稳定性设计对高端电子设备性能起到决定性的作用。     

第五代电路安装技术—CAIT

市场的要求促进了电子设备的发展,使电子学进入了全盛时期,“轻薄短小化”这个词形象地表达了电于产品开发的一个重要动向,这就是高密度化.在过去的十年里,上述目的主要是依靠半导体芯片微细加工技术的进步来实现的.目前,IC的大规模化仍以惊人的速度发展着,微机的功能和处理容量也在急剧扩大,在ASIC方面也取得了令人嘱目的进展.可以说,用微细加工技术提高芯片集成规模是高密度安装的第一个层次.     

视觉系统在全自动COG热压焊机中的应用

COG组装工艺技术是IC与LCD连接的主要方式.采用这种连接方式可大大减小整个LCD模块的体积、提高组装密度,实现规模化生产.针对视觉系统在全自动COG热压焊机中的应用进行分析.     

IC封装无芯基板的发展与制造研究

手持电子产品的薄型化催生了IC封装无芯基板,它不仅比IC封装有芯基板更薄,而且电气性能更加优越。介绍了IC封装无芯基板的发展趋势和制造中面临的问题。IC封装无芯基板以半加成法制造,翘曲是目前制程中的首要问题。翘曲改善主要依靠改变绝缘层材料和积层结构,可用云纹干涉法进行量测,并以模拟为指导加快开发周期。     

Optimizing the controller IC for micro HDD process based on Taguchi methods

The future trend of controller integrated circuit (IC) for micro hard disk driver (HDD) is to be lighter, thinner, shorter and smaller. The storage capacity and unit cost of micro HDD is lower than of flash memory card. The optimal packaging manufacturing process for driver IC for micro HDD is Chip Scale Package (CSP). However, the production and assemble process for CSP is much more difficult. Especially, the warpage problem on modeling results in non-conforming products. This research is to discover the optimal production levels for control factors based on the orthogonal array in Tachugi method. The product size used in the study is the driver IC package overall height less than 0.65 mm for micro HDD with CSP manufacturing process.     

Development of a mathematical model for thermal-compression bonding of the COG packaging process using NCA

In this decade, many new techniques have been introduced into the integrated circuit (IC) packaging industry. Packaging technology used in liquid crystal displays (LCDs) has requirements related to critical issues such as high density interconnects, thinner packaging size, and environmental safety. Driver IC chips are directly attached to LCD panels using flip chip technology with adhesives in the so called chip on glass (COG) packaging processes. To investigate the dependence of the bonding force on the bump deformation during packaging, this study established a mathematical model to analyze COG packaging processes with non-conductive adhesives (NCAs). The plastic deformation of the bumps and the NCA flow between the chip and substrate are taken into account in this model. With this model, the contact resistance and the gap height after bonding can be estimated for different bonding force.     

新一代层叠封装(PoP)的发展趋势及翘曲控制

便携式移动设备是当今半导体集成电路行业的主要发展动力。其对封装的挑战,除电性能的提高外,还强调了小型化和薄型化。层叠封装(PoP)新的趋势,包括芯片尺寸增大、倒装技术应用、超薄化等,进一步增加了控制封装翘曲的难度。超薄封装的翘曲大小及方向与芯片尺寸、基板和塑封层厚度,以及材料特性密切相关。传统的通用封装方案已不再适用,需要根据芯片设计及应用,对封装设计、材料等因素加以优化,才能满足翘曲控制要求。另外,基板变薄后,来自不同供应商的基板可能出现不同的封装翘曲反应,需要加强对基板设计公差及供应链的管控。     

Understanding of Delamination Mechanism of Anisotropic Conductive Film (ACF) Bonding in Thin Liquid Crystal Display (LCD) Module

The chip-on-glass (COG) technique using anisotropic conductive film (ACF) has been developed for liquid crystal display (LCD) panels with excellent resolution and high quality for several years. However, many serious manufacturability and reliability issues were observed from previous studies. In those, delamination occurring at the ACF interface is one of the common concerns. Few works presented analysis of delamination mechanism through the whole COG bonding process with the combination of LCD module scale and ACF interconnect scale. In this paper, the delamination mechanism of COG/ACF interconnection was studied by using finite element analysis. Equivalent block and global-local modeling methods were implemented with nonlinear elastic-plastic and sequential coupled thermal-mechanical analysis. The critical parameters of the COG bonding process and geometry of integrated circuit (IC) and glass were investigated to understand the mechanism of ACF delamination. It was found that the delamination could be reduced by decreasing the temperature difference between bonding head and glass substrate or using thin and short IC. The local model analysis revealed that the interface of glass/ACF epoxy encountered the higher stress than that in the interface of IC/ACF epoxy and had the higher possibility to delaminate. Therefore, increasing the bonding-strength between glass and ACF epoxy is the direction to reduce the probability of ACF delamination.     

A Study of Process-Induced Deformations of Anisotropic Conductive Film (ACF) Assembly

The warpage of glass substrate in chip-on-glass (COG) assemblies were believed to be the main cause of the so-called “Mura” phenomenon in thin-film transistor liquid crystal display (TFT–LCD) panels. The main objective of the study is to characterize the process-induced deformations of an anisotropic conductive film (ACF) type of COG assembly during the ACF bonding process. For effectively modeling the process-dependent thermal–mechanical behaviors of the ACF assembly, a process-dependent simulation methodology that integrates both thermal and thermal–mechanical finite element (FE) analyses and a “death–birth” meshing scheme is proposed. In the investigation, two various types of mirobump bonding technologies, i.e., the Au alloy and composite bumps, are explored. To substantiate the validity of the proposed methodology, the modeled results are extensively compared against experimental data. Moreover, the alternative goal of the study is to provide a design guideline through the exploration of the individual or combined effect of some essential parameters on the process-induced deformations. Both the modeled and experimental results reveal that in addition to the coefficient of thermal expansion (CTE) mismatch between the die and substrate, the process-induced temperature gradient appears to be the key factor causing the deformation of the assembly, and the deformed shape of the substrate is totally opposed to that obtained from isothermal modeling. Evidence also suggests that a preheated substrate could effectively ease the maximum process-induced warpage of the substrate, while the ACF fillet would unfortunately enlarge it. Besides, it is not surprising to find that an increase of the die length would enhance the maximum process-induced warpage of the substrate, but what surprises many is that an increase of the die width would diminish it.     

An accommodative approach designed for TCP gold-to-gold inner lead bonding

This paper proposes an approach that resolves the tradeoff between bond pad crack, the passivation crack, and lead lift failure modes in gold-to-gold inner lead bonding. The bonding head temperature, stage temperature, and bonding force are addressed as three critical recipes. The proposed scenario determines the bonding head temperature according to the maximum compensation flatness, followed by the corresponding stage temperature and required bonding force in sequence. The relevant gold bump hardness, chip warpage, and flatness variation in the bonding tool were evaluated using the finite-element method. The corresponding bonding force was determined using semianalytical equations with empirical factors. A gate driver IC with 280 I/O pins was adopted to conduct the experimental verification in the engineering pilot run. With the optimal recipes, the obtained results demonstrated success in diminishing these three failure modes. The feasibility of proposed approach was verified experimentally.     

移动通讯类HDI板的弯翘研究

由于近几年移动通讯类产品向轻、薄的迅猛发展，而承载部件主板的重量、厚度、体积等起到决定性的作用，故适合此类产品的新型材料薄布基材应用而生，本文主要阐述PCB制造端对板弯翘的预防、改善及矫正方法。