A parallel built-in self-diagnostic method for nontraditional faults of embedded memory arrays

In this paper, we propose a built-in self-diagnostic march-based algorithm that identifies faulty memory cells based on a recently introduced nontraditional fault model. It is developed based on the DiagRSMarch algorithm, which is a diagnostic algorithm to identify traditional faults for embedded memory arrays. A minimal set of additional operations is added to DiagRSMarch for identifying the nontraditional faults without affecting the diagnostic coverage of the traditional faults. The embedded memory arrays are accessed using a bidirectional serial interfacing architecture which minimizes the routing overhead introduced by the diagnosis hardware. Using the concepts of the bidirectional interfacing technique, parallel testing, and redundant-tolerant operations, the diagnostic process can be accomplished efficiently at-speed with minimal hardware overhead.     

Built-in self-test for phase-locked loops

An effective built-in self-test (BIST) structure of a phase-locked loop (PLL) in digital applications is presented in this paper. The proposed BIST structure can identify possible faults in any block such as the phase detector, charge pump, loop filter, voltage-controlled oscillator and divide-by-N of the PLL. The key advantage of this approach is that it uses all existing blocks in PLL for measuring and testing, reducing the chip area overhead. Restated, the proposed approach does not alter any existing analog circuits. Rather, the proposed approach only adds some small circuits to the PLL and requires a slight modification of the digital part. The final test outputs are digital values which can increase the reliability of the proposed BIST structure. Physical chip design and fault simulation results indicate the characteristics of the proposed BIST structure, namely, high fault coverage (97.2%) and low area overhead (2.78%).     

Reliability measurement of mass storage system for onboard instrumentation

Advances in spaceborne vehicular technology have made possible the long-life duration of the mission in harsh cosmic environments. Reliability and data integrity are the commonly emphasized requirements of spaceborne solid-state mass storage systems, because faults due to the harsh cosmic environments, such as extreme radiation, can be experienced throughout the mission. Acceptable dependability for these instruments has been achieved by using redundancy and repair. Reconfiguration (repair) of memory arrays using spare memory lines is the most common technique for reliability enhancement of memories with faults. Faulty cells in memory arrays are known to show spatial locality. This physical phenomenon is referred to as fault clustering . This paper initially investigates a quadrat-based fault model for memory arrays under clustered faults to establish a reliable foundation of measurement. Then, lifelong dependability of a fault-tolerant spaceborne memory system with hierarchical active redundancy, which consists of spare columns in each memory module and redundant memory modules, is measured in terms of the reliability (i.e., the conditional probability that the system performs correctly throughout the mission) and mean-time-to-failure (i.e., the expected time that a system will operate before it fails). Finally, minimal column redundancy search technique for the fault-tolerant memory system is proposed and verified through a series of parametric simulations. Thereby, design and fabrication of cost-effective and highly reliable fault-tolerant onboard mass storage system can be realized for dependable instrumentation.     

Configurable two-dimensional linear feedback shifter registers for parallel and serial built-in self-test

A configurable two-dimensional (2-D) LFSR based test generator and an automated synthesis procedure are presented. Without storage of test patterns, a 2-D LFSR based test pattern generator can generate a sequence of precomputed test patterns (detecting random-pattern-resistant faults) and followed by random patterns (detecting random-pattern-detectable faults). The hardware overhead is decreased considerably through configuration. The configurable 2-D LFSR test generator can be adopted in two basic BIST execution options: test-per-clock (parallel BIST) and test-per-scan (serial BIST). Experimental results of test-per-clock and test-per-scan BIST of benchmark circuits demonstrate the effectiveness of the proposed technique. The configurable 2-D LSFR can also be adopted in chip-level and system-on-a-chip (SoC) BIST.     

Analysis and measurement of fault coverage in a combined ATE and BIST environment

This paper analyzes an environment which utilizes built-in self-test (BIST) and automatic test equipment (ATE), and presents closed-form expressions for fault coverage as a function of the number of BIST and ATE test vectors. This requires incorporating the time to switch from BIST to ATE (referred to as switchover time), and utilizing ATE generated vectors to finally achieve the desired level of fault coverage. For this environment, we model fault coverage as a function of the testability of the circuit under test and the numbers of vectors which are supplied by the BIST circuitry and the ATE. A novel approach is proposed; this approach is initially based on fault simulation using a small set of random vectors; an estimate of the so-called detection profile of the circuit under test is established as the basis of the test model. This analytical model effectively relates the testable features of the circuit under test to detection using both BIST and ATE as related testing processes.     

Space compactor design in VLSI circuits based on graph theoretic concepts

The realization of a space-efficient support hardware for built-in self-testing (BIST) is of immense significance in the synthesis of very large scale integration (VLSI) circuits. This paper presents a new zero-aliasing compaction approach of test data outputs with an application specifically targeted to digital embedded cores-based system-on-chips (SOCs), which facilitates the design of such space-efficient BIST support hardware. The suggested technique takes advantage of some well-known concepts of conventional switching theory, together with those of strong and weak compatibilities of response data outputs in the selection of specific gates for merger of an arbitrary but optimal number of output bit streams from the module under test (MUT), based on optimal generalized sequence mergeability, as developed and applied by the authors in earlier works. This is novel in the sense that zero aliasing is realized without any modification of the MUT, while a maximal compaction is achieved in almost all cases in reasonable time utilizing some simple heuristics. The method is illustrated with design details of space compactors for ISCAS 85 combinational benchmark circuits using simulation programs ATALANTA, FSIM, and COMPACTEST, confirming the usefulness of the approach for its simplicity, resulting low area overhead, and full fault coverage for single stuck-line faults, thereby making it suitable in a VLSI design environment. With advances in computational resources in the future, the heuristics adopted in the design algorithm may be further improved upon to significantly lower the simulation CPU time and storage.     

Analysis and evaluation of multisite testing for VLSI

This paper deals with multisite testing of VLSI chips in a manufacturing environment. Multisite testing is analyzed and evaluated using device-under-test (DUT) parameters (such as yield and average number of faults per DUT) as well as test process features (such as number of channels, fault coverage, and touchdown time for the head). The presence of idle time periods and their impact on the multisite test time is analyzed in depth. Two hybrid testing scenarios which combine built-in self-test (BIST) and automatic test equipment (ATE) are proposed and analytical models are provided to establish the corresponding multisite test time. It is shown that a hybrid approach based on screening chips through a BIST stage improves the performance of multisite test and allows a better utilization of channels in the head of an ATE.     

A new low-cost RF built-in self-test measurement for system-on-chip transceivers

This paper presents a new RF built-in self-test (BIST) measurement and a new automatic-performance-compensation network for a system-on-chip (SoC) transceiver. We built a 5-GHz low noise amplifier (LNA) with an on-chip BIST circuit using 0.18-/spl mu/m SiGe technology. The BIST-measurement circuit contains a test amplifier and RF peak detectors. The complete measurement setup contains an LNA with a BIST circuit, an external RF source, RF relays, 50-/spl Omega/ load impedance, and a dc voltmeter. The proposed BIST circuit measures input impedance, gain, noise figure, input return loss, and output signal-to-noise ratio of the LNA. The test technique utilizes the output dc-voltage measurements, and these measured values are translated to the LNA specifications such as the gain through the developed equations. The performance of the LNA was improved by using the new automatic compensation network (ACN) that adjusts the performance of the LNA with the processor in the SoC transceiver.     

Using a Square-Wave Signal for Fault Diagnosis of Analog Parts of Mixed-Signal Electronic Embedded Systems

This paper presents a new approach to the detection and localization of single hard and soft faults of analog parts in embedded mixed-signal electronic systems controlled with microcontrollers, DSPs, or Systems-on-a-Chip (SoCs) (generally control units). The approach consists of three stages: a pretesting stage of creation of the fault dictionary using identification curves, a measurement stage based on stimulating the tested circuit by a square-wave signal generated by the control unit, and measurements of voltage samples of the circuit response by the internal ADC of the control unit. In the final stage, fault detection and localization are performed by the control unit. The measurement microsystem [the built-in self test (BIST)] consists only of internal devices of the control unit already existing in the system. Hence, this approach simplifies the structure of BISTs, which allows reduction of test costs. The results of experimental verification of the approach are included in this paper.      

Embedded test control schemes using iBIST for SOCs

This paper presents novel control schemes for testing embedded cores in a system-on-a-chip. It converts a traditional built-in self-test (BIST) scheme into an externally controllable scheme to achieve high test quality within optimal test execution time without inserting test points. Interactive BIST promotes design and test reuse without revealing IP information by using a pattern matching technique instead of fault simulation.     

Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with nonexhaustive test sets

The design of efficient time compression support hardware for built-in self-testing (BIST) is of great importance in the design and manufacture of VLSI circuits. The test data outputs in BIST are ultimately compressed by time compaction hardware, commonly called a response analyzer, into signatures. Several output response compaction techniques to aid in the synthesis of such support circuits already exist in literature, and parity bit signature coupled with exhaustive testing is already well known to have certain very desirable properties in this context. This paper reports new time compaction techniques utilizing the concept of parity bit signature that facilitates implementing such support circuits using nonexhaustive or compact test sets, with the primary objective of minimizing the storage requirements for the circuit under test (CUT) while maintaining the fault coverage information as best as possible.     

A method for evaluating fault coverage using simulated fault injection for digitalized systems in nuclear power plants

The fault coverage for digital system in nuclear power plants is evaluated using a simulated fault injection method. Digital systems have numerous advantages, such as hardware elements share and hardware replication of the needed number of independent channels. However, the application of digital systems to safety-critical systems in nuclear power plants has been limited due to reliability concerns. In the reliability issues, fault coverage is one of the most important factors. In this study, we propose an evaluation method of the fault coverage for safety-critical digital systems in nuclear power plants. The system under assessment is a local coincidence logic processor for a digital plant protection system at Ulchin nuclear power plant units 5 and 6. The assessed system is simplified and then a simulated fault injection method is applied to evaluate the fault coverage of two fault detection mechanisms. From the simulated fault injection experiment, the fault detection coverage of the watchdog timer is 44.2% and that of the read only memory (ROM) checksum is 50.5%. Our experiments show that the fault coverage of a safety-critical digital system is effectively quantified using the simulated fault injection method.     

基于KS检验的智能故障诊断方法研究

提出了一种利用KS检验对机械故障进行分类的新方法。通过仿真试验和齿轮故障诊断，说明该方法在数据样本含有一定噪声时也能正确判断故障。在利用少量轴承时域故障数据样本建立多故障分类系统后，仅仅需要极短时间就能准确分类多种故障。结果表明，该方法具有很好的分类能力和较高的计算效率，完全可以满足智能故障诊断的要求。     

A built-in self-testing method for embedded multiport memory arrays

With recent advances in semiconductor technologies, the design and use of memories for realizing complex system-on-a-chip (SoC) is very widespread. The growing need for storage in computer, communication, and network appliances has motivated new advancements in faster and more efficient ways to test memories. Efficient testing schemes for single-port memories have been readily available. Multiport memories are widely used in multiprocessor systems, telecommunication application-specific integrated circuits (ASICs), etc. Research papers which define multiport memory fault models and give march tests for the same are currently available. However, little work has been done to use the power of serial interfacing for testing multiport memories. In this paper, we develop a powerful test architecture for two-port memories using the serial interfacing technique. Based on the serial testing mechanism, we propose new march algorithms which can prove effective to reduce hardware cost considerably for a chip with many two-port memories. Once we understand how serial interfacing helps test two-port memories, one possible extension is to use serial interfacing for p-port memories (p > 2). The proposed method based on the serial interfacing technique has the advantages of high fault coverage, low hardware overhead, and tolerable test application time.     

Built-in self-test (BIST) structures for analog circuit faultdiagnosis with current test data

In order to increase the number of test points, while still keeping low pin overhead, a built-in self-test (BIST) structure has been proposed for analog circuit fault diagnosis with voltage test data. The authors present alternative BIST structures for fault diagnosis with current test data using current copiers. The current copiers make a practically identical copy of the current without the need of well-matched components. Thus the proposed BIST structure requires less chip area. The proposed structure allows simultaneous sampling of current test data at various test points and shifting of the data to the output portion for fault diagnosis. Results have also shown that the proposed BIST structure is fully testable     

Assessment of redundant systems with imperfect coverage by means of binary decision diagrams

In this article, we study the assessment of the reliability of redundant systems with imperfect fault coverage. We term fault coverage as the ability of a system to isolate and correctly accommodate failures of redundant elements. For highly reliable systems, such as avionic and space systems, fault coverage is in general imperfect and has a significant impact on system reliability. We review here the different models of imperfect fault coverage. We propose efficient algorithms to assess them separately (as k-out-of-n selectors). We show how to implement these algorithms into a binary decision diagrams engine. Finally, we report experimental results on real life test cases that show on the one hand the importance of imperfect coverage and on the other hand the efficiency of the proposed approach.     

Decoupling features for diagnosis of reversing and check valve faults in heat pumps

Recently, a decoupling-based (DB) fault detection and diagnosis (FDD) method was developed for diagnosing multiple-simultaneous faults in air conditioners (AC) and was shown to have very good performance. The method relies on identifying diagnostic features that are decoupled (i.e., insensitive) to other faults and operating conditions. The current paper extends the DB FDD methodology to heat pumps. Heat pumps have all the same faults as occur for air conditioners with additional faults associated with components that accommodate heating mode, including reversing valve leakage and check valve leakage. Decoupling features were developed for these additional faults and laboratory evaluations were performed to evaluate diagnostic performance. It was found that check valve leakage could be detected and diagnosed before the heating capacity degradation reached 5% for a system with a fixed orifice expansion (FXO) device and 3% for the same system retrofit with a thermal expansion valve (TXV). Furthermore, the feature for check valve leakage is very insensitive to other faults and operating conditions. The decoupling feature for reversing valve leakage could successfully detect and diagnose faults for a TXV system before the heating capacity degraded 6% and was also insensitive to other faults and operating conditions. However, this feature did not work well for a system with an FXO in heating mode because the refrigerant exiting the evaporator and entering the reversing valve was typically a two-phase mixture. Fortunately, it was possible to diagnose this particular fault at many operating conditions in cooling mode for the system with an FXO.     

嵌入式DRAM的BIST测试方法的研究

通过对比分析了嵌入式DRAM的传统测试方法和内建自测试(BIST)方法，提出了嵌入式DRAM的内建自测试（BIST）方案，该方案具有测试生成快，节约测试成本等优点，对其它类型电路的测试也有很好的借鉴价值。     

Multi-state systems with multi-fault coverage

The paper introduces a new model of fault level coverage for multi-state systems in which the effectiveness of recovery mechanisms depends on the coexistence of multiple faults in related elements. Examples of this effect can be found in computing systems, electrical power distribution networks, pipelines carrying dangerous materials, etc. For evaluating reliability and performance indices of multi-state systems with imperfect multi-fault coverage, a modification of the generalized reliability block diagram (RBD) method is suggested. This method, based on a universal generating function technique, allows performance distribution of complex multi-state series–parallel system with multi-fault coverage to be obtained using a straightforward recursive procedure. Illustrative examples are presented.