Reduced-sample-rate sigma–delta modulation using recursive deconvolution

A reduced-sample-rate sigma–delta modulation method using a recursive deconvolution technique for application in digital-to-analogue conversion is proposed and analysed. The method allows the sigma–delta modulators to operate at a sampling rate which is lower than the output bitstream rate by an integer factor. With the proposed in-loop mapping algorithm to map an m-bit sample to qb-bit samples, the total system inherits the advantages of a multilevel quantization conventional ΣΔ modulator in the digital part with regard to suppression of tones, improved stability and low power, while its output remains single-bit. The effectiveness of the technique is illustrated using simulations for second-and third-order modulators. © by John Wiley & Sons, Ltd.     

Dynamic OSR dithered sigma–delta modulation in solid state light dimming

Pulse width modulation (PWM) is the most common way to control switching regulation and digital dimming. This paper presents a way to implement digital dimming by means of a dithered sigma–delta modulator with dynamic oversampling ratio. The system has been modeled in SystemC‐WMS and implemented in a board using a commercial microcontroller. Simulation results show conducted electromagnetic interference reduction compared to PWM and flickering reduction with respect to classic sigma‐delta modulation. Copyright © 2011 John Wiley & Sons, Ltd.     

On the transposition of Gm–C filters to DC stabilized log‐domain filters

High‐order log‐domain filters could be designed by transposing the already known linear‐domain G_m–C filter topologies to the corresponding topologies in the log‐domain. This is achieved by using a non‐linear transconductor configuration, where the output current is exponentially related to its input and output voltages. A drawback of the non‐linear transconductor configuration already introduced in the literature is that a number of the transposed log‐domain filter topologies suffer from DC instability, while in some others a DC offset current appears at their output. In order to eliminate the aforementioned problems a modified non‐linear transconductor configuration for transposing G_m–C filter topologies to log‐domain filter topologies is introduced in this paper. The achieved improvements are demonstrated through a number of log‐domain filter configurations derived using the already introduced and the proposed transposition schemes. Copyright © 2006 John Wiley & Sons, Ltd.     

On hyperbolic laws of capacitor discharge through self‐timed digital loads

A new model to predict the dynamic behavior of a self‐timed autonomous digital system powered by a capacitor is derived. The model demonstrates the hyperbolic shape of the discharging process on the capacitor. It allows a symbolic analysis of the discharging process for complex digital loads comprised of series (stack) and parallel configurations of digital circuits. For example, for a stack configuration, important non‐trivial relationships between the hyperbolic discharging rates have been derived based on the knowledge of the velocity saturation index (alpha) of the semiconductor devices used in the digital part. For a realistic (modern complementary metal oxide semiconductor (CMOS) devices) value of alpha = 1.5, the discharging process for a stack of two identical circuits proceeds nearly three times slower than that of any of the stand‐alone circuits. This shows a potential way of extending the lifetime of the energy sources by means of stacking self‐timed circuits. Although the analysis is based on configurations consisting of ring oscillators in CMOS technology, the analysis method can be extended to other types of self‐timed systems and other semiconductor technologies in which the instantaneous switching activity of the digital load is determined by the instantaneous voltage levels provided by the capacitive power transfer mechanism. The analytical derivations have been validated by simulations and experiments carried out with real hardware. © 2014 The Authors. International Journal of Circuit Theory and Applications published by John Wiley & Sons, Ltd.     

Current‐mode filters based on current mirror arrays

A technique is proposed for obtaining current‐mode filters based on current mirror arrays that operate as unity gain current amplifiers. These amplifiers by properly driving capacitors realize active lossless integrators which are the basic active elements for the derivation of filters according to the leapfrog method. Due to the fact that both the structure of the amplifiers and the adapted method for filter design are simple, the proposed technique is attractive for filter design and implementation. A design and the implementation of two third‐order low‐pass filters are presented. The array of the amplifiers has been implemented in a 0.8 µm CMOS technology. Copyright © 2007 John Wiley & Sons, Ltd.     

Ultra‐low voltage fractional‐order circuits using current mirrors

Fractional‐order blocks, including differentiators, lossy and lossless integrators as well as filters of order 1 + a (0 < a < 1), are presented in this paper. The proposed topologies offer the benefit of ultra low‐voltage operation; in addition, reduced circuit complexity is achieved compared to the corresponding companding schemes, which have been already introduced in the literature. The ultra‐low voltage operation is performed through the employment of metal oxide semiconductor transistors biased in the subthreshold region. The reduction of circuit complexity is achieved through the utilization of current mirrors as active elements for realizing the required building blocks. The performance of the proposed fractional‐order circuits has been evaluated through the Analog Design Environment of the Cadence software and the design kit provided by the Taiwan Semiconductor Manufacturing Company (TSMC) 180 nm complementary metal oxide semiconductor process. Copyright © 2015 John Wiley & Sons, Ltd.     

0.5‐V fractional‐order companding filters

Novel configurations of fractional‐order filter topologies, realized through the employment of the concept of companding filtering, are introduced in this paper. As a first step, the design procedure is presented in a systematic algorithmic way, while in the next step, the basic building blocks of sinh‐domain and log‐domain integrators are presented. Because of the employment of metal–oxide–semiconductor (MOS) transistors operated in the subthreshold region, the derived filter structures offer the capability for operation in an ultra‐low‐voltage environment. In addition, because of the offered resistorless realizations, the proposed topologies are reconfigurable, in the sense that the order of the filter could be chosen through appropriate bias current sources. The performance of the derived fractional‐order filters has been evaluated through simulation and comparison results using the Analog Design Environment of the Cadence software and MOS transistor parameters provided by the Taiwan Semiconductor Manufacturing Company (TSMC) 180‐nm complementary MOS (CMOS) process. Copyright © 2014 John Wiley & Sons, Ltd.     

1.2 V Sinh‐Domain allpass filter

A first‐order Sinh‐Domain allpass filter topology is introduced in this paper. It is constructed from a class‐AB current mirror and appropriately configured non‐linear transconductor cells. Due to the inherent class‐AB nature of Sinh‐Domain filters, the proposed topology offers the capability for handling currents at levels greater than that of the dc bias current level. Also, it offers the well‐known features of companding filters such as electronic adjustment of its frequency characteristics and the capability for operation in a low‐voltage environment. In addition, a four‐phase sinusoidal oscillator design example has been provided. The behaviour of the proposed topology has been evaluated and compared with other already known configurations, where the most important performance factors have been considered. Copyright © 2013 John Wiley & Sons, Ltd.     

Realization of log‐domain high‐order transfer functions using first‐order building blocks and complementary operators

High‐order log‐domain filters could be easily designed by using the functional block diagram (FBD) representation of the corresponding linear prototype and a set of complementary operators. For this purpose, lossy and lossless integrator blocks have been already introduced in the literature. Novel first‐order log‐domain highpass and allpass filter configurations, which are fully compatible with the already published integrator blocks, are introduced in this paper. These are realized using integration and subtraction blocks or a novel differentiation configuration. As a result, a complete set of first‐order building blocks would be available for synthesizing any arbitrary high‐order transfer function. In order to verify the correct operation of the proposed structures, the performance of the introduced highpass filters was evaluated through simulation results. In addition, a fifth‐order log‐domain bandpass filter was designed and simulated using one of the introduced first‐order highpass filter configurations. Copyright © 2006 John Wiley & Sons, Ltd.     

Fractional‐order electronically controlled generalized filters

Novel topologies of fractional‐order generalized filters are introduced in this paper. These offer the following benefits: (1) realization of lowpass, highpass, bandpass, allpass, or bandstop filter functions by the same topology; (2) resistorless realizations; (3) electronic adjustment of their frequency characteristics as well as their order; and (4) employment of only grounded capacitors. All the above have been achieved using Operational Transconductance Amplifiers as active elements and appropriate multi‐feedback topologies. The behavior of the proposed designs is verified through simulation results using the Cadence IC design suite and the Design Kit provided by the Austrian Micro Systems 0.35‐µm complementary metal–oxide–semiconductor process. Copyright © 2016 John Wiley & Sons, Ltd.     

A DC stabilized log‐domain nth‐order multifunction filter based on the decomposition of nth‐order HP filter function to FLF topology

The design of high‐order log‐domain filters can be easily accomplished by transposing already known linear‐domain G_m‐C filter topologies to their counterparts in the log‐domain through the employment of a set of complementary operators. To achieve the G_m‐C filter topologies, the multiple feedback approach is widely used due to its accrued advantages. In this paper a synthesis approach for the development of an nth‐order multifunction log‐domain filter comprising lowpass (LP), highpass (HP) and bandpass (BP) filter functions is proposed. The approach is based on the decomposition of nth‐order HP filter function to follow‐the‐leader‐feedback (FLF) topology. The design is simple and simultaneously achieves nearly all of the chief advantages. The design offers superior performance factors vis‐à‐vis the ones recently reported. To verify the high‐order behavior of the topology, a 5th‐order multifunction filter was designed and the achieved simulated results verify the theory. Copyright © 2008 John Wiley & Sons, Ltd.     

Low‐power,low‐noise,active‐RC band‐pass filters using a ‘lossy’ LP–BP transformation

A new and straightforward design procedure for simple canonical topologies of allpole, active‐RC, low‐selectivity band‐pass (BP) filters, with low sensitivity to component tolerances is presented. The procedure is primarily intended for discrete‐component, low‐power filter applications using just one amplifier for relatively high‐order filters. The design procedure starts out with an ‘optimized’ low‐pass (LP) prototype filter, yielding an ‘optimized’ BP filter, whereby the wealth of ‘optimized’ single‐amplifier LP filter designs can be exploited. Using a so‐called ‘lossy’ LP–BP transformation, closed‐form design equations for the design of second‐ to eighth‐order, single‐amplifier BP filters are presented. The low sensitivity, low power consumption, and low noise features of the resulting circuits, as well as the influence of the finite gain‐bandwidth product and component spread, are demonstrated for the case of a fourth‐order filter example. The optimized single‐opamp fourth‐order filter is compared with other designs, such as the cascade of optimized Biquads. Using PSpice with a TL081 opamp model, the filter performance is simulated and the results compared and verified with measurements of a discrete‐component breadboard filter using 1% resistors, 1% capacitors, and a TL081 opamp. Copyright © 2011 John Wiley & Sons, Ltd.     

Explicit design formulas for current‐mode leap‐frog OTA‐C filters and 300 MHz CMOS seventh‐order linear phase filter

The leap‐frog (LF) configuration is an important structure in analogue filter design. Voltage‐mode LF OTA‐C filters have recently been studied in the literature; however, general explicit formulas do not exist for current‐mode LF OTA‐C filters and there is also need for current‐mode LF‐based OTA‐C structures for realization of arbitrary transmission zeros. Three current‐mode OTA‐C structures are presented, including the basic LF structure and LF filters with an input distributor or an output summer. They can realize all‐pole characteristics and functions with arbitrary transmission zeros. Explicit design formulas are derived directly from these structures for the synthesis of, respectively, all‐pole and arbitrary zero filter characteristics of up to the sixth order. The filter structures are regular and the design formulas are straightforward to use. As an illustrative example, a 300 MHz seventh‐order linear phase low‐pass filter with zeros is presented. The filter is implemented using a fully differential linear operational transconductance amplifier (OTA) based on a source degeneration topology. Simulations in a standard TSMC 0.18µm CMOS process with 2.5 V power supply have shown that the cutoff frequency of the filter ranges from 260 to 320 MHz, group delay ripple is about 4.5% over the whole tuning range, noise of the filter is 420nA/√Hz, dynamic range is 66 dB and power consumption is 200 mW. Copyright © 2008 John Wiley & Sons, Ltd.     

Balanced Gm‐C filters with improved linearity and power efficiency

A novel G_m‐C filter design technique is presented. It is based on floating‐gate metal oxide semiconductor (FGMOS) transistors and consists in a topological rearrangement of conventional fully differential G_m‐C structures without modifying the employed transconductors at transistor level. The proposed method allows decreasing the number of active elements (transconductors) of the filter. Moreover, high linearity is obtained at low and medium frequencies of the pass band. Drawbacks inherent to the use of FGMOS transistors are analyzed, such as large occupied area, high sensitivity to mismatch, or parasitic zeros in transfer functions. The features of the proposed technique are fully exploited in all‐pole G_m‐C filter design, specially implementing unity gain Butterworth transfer functions. Thus, two low‐power second‐order Butterworth G_m‐C filters have been designed and fabricated to compare the proposed FGMOS technique with their equivalent topologies obtained by a conventional design method. Measurement results for a test chip prototype in a 0.5‐µm standard complementary MOS process are presented, confirming the advantages of the proposed FGMOS design technique. Copyright © 2014 John Wiley & Sons, Ltd.     

Square‐root domain wave filters

In this paper the wave method is used for designing high‐order square‐root domain filters, which emulate the topology of the corresponding LC ladder prototypes. This is achieved by transposing the signal flow graph that corresponds to the wave equivalent of the elementary two‐port subnetwork in the linear domain to the corresponding one in the square‐root domain, by employing an appropriate set of complementary operators. As the equivalents of the other reactive elements are derived from the wave equivalent of the elementary subnetwork, by interchanging the terminals of the appropriate wave signals and/or using inverters, an advantage offered by the proposed technique is the modularity of the derived filter configurations. As an example, a fifth‐order lowpass square‐root domain wave filter was designed and its behaviour was studied through simulation results in order to demonstrate the validity of the proposed design technique. Copyright © 2006 John Wiley & Sons, Ltd.     

Square‐root domain linear transformation filters

A new systematic method for designing square‐root domain (SRD) linear transformation (LT) filter is introduced in this paper. For this purpose, a substitution table containing the SRD LT equivalent of each passive element has been introduced. The proposed equivalents have been realized by employing appropriate SRD building blocks with low‐voltage operation capability. As a design example, a 3rd‐order SRD LT filter has been realized and its performance has been evaluated through simulation results. In addition, the most important performance factors of the SRD filter have been compared with those achieved by the SRD filters derived according to the leapfrog, wave, and topological emulation methods. Copyright © 2010 John Wiley & Sons, Ltd.     

Design of current‐mode MOSFET‐C filters using OTRAs

In this paper, third‐order current‐mode MOSFET‐C filters that use operational transresistance amplifiers (OTRAs) with little parasitic capacitance effects are presented. On the basis of the proposed systematic method and design procedure, we can efficiently synthesize third‐order active filters with OTRAs along with simplified MOSFET resistor circuits, and all virtually grounded capacitors. Third‐order current‐mode Chebychev low‐pass and high‐pass filters are realized to verify the validity of the theoretical analysis. Experimental results employing commercially available current feedback amplifiers are also given. Copyright © 2008 John Wiley & Sons, Ltd.     

A 13 bit 10 MHz bandwidth MASH 3–2 Σ∆ modulator in 90 nm CMOS

In this paper, a new multi loop sigma‐delta (ΣΔ) modulator is proposed which employs one order redundant noise shaping in the first stage so the effect of the quantization noise leakage is minimized. Thus, analog circuit requirements are considerably relaxed compared to the conventional Multi‐stAge‐noise‐SHaping (MASH) structures. This enhancement makes the structure appropriate for low voltage and broadband applications. The proposed architecture is compared with traditional high‐order structures, and the advantages are demonstrated by both the analysis and behavioral system level simulations. As a prototype, the proposed MASH 3–2 sigma‐delta modulator is designed, and the detailed design procedure is presented from the system level to the circuit level in a 90 nm CMOS technology. Circuit level simulation results show that the modulator achieves a peak signal‐to‐noise and distortion ratio of 79.4 dB and 79 dB dynamic range over a 10 MHz bandwidth with a sampling frequency of 160 MHz. It consumes 35.4 mW power from a single 1 V supply. Copyright © 2012 John Wiley & Sons, Ltd.     

Three novel improved CMOS C‐multipliers

Three novel improved CMOS capacitance scaling schemes are presented and compared with some conventional schemes. The novel topologies that use a modified second‐generation current conveyor, an improved cascode current mirror and an OTA with two outputs connected in current steering configuration provide higher values of Q and better frequency responses than conventional structures using basic current mirror schemes, as the simple current mirror or cascode current mirrors. Simulation results and some measurements of a chip prototype are presented. Copyright © 2011 John Wiley & Sons, Ltd.     

Switched‐capacitor‐voltage‐multiplier boost DC–AC inverter with adaptive stages

A multistage switched‐capacitor‐voltage‐multiplier inverter (SCVMI) is proposed with a variable‐conversion‐ratio phase generator and a sinusoidal pulse‐width‐modulation controller for boost DC–AC conversion and high‐efficiency regulation. Its power unit contains: SCVM booster and H‐bridge. The SCVM booster includes two m_c‐stage switched‐capacitor cells and two n_c‐stage switched‐capacitor cells in the interleaving operation to realize DC–DC boost gain of m_c × n_c at most. Here, the variable‐conversion‐ratio phase generator is suggested and adopted to change the running stage number and topological path for a suitable gain level of m × n (m = 1, 2, ?,m_c, n = 1, 2, ?,n_c) to improve efficiency, especially for the lower AC output. The H‐bridge is employed for DC–AC conversion, where four switches are controlled by sinusoidal pulse‐width‐modulation not only for full‐wave output but also for output regulation as well as robustness to source/loading variation. Some theoretical analysis and design include: SCVMI model, steady‐state/dynamic analysis, conversion ratio, power efficiency, stability, capacitance selection, output filter, and control design. Finally, the closed‐loop SCVMI is simulated, and the hardware circuit is implemented and tested. All the results are illustrated to show the efficacy of this scheme. Copyright © 2011 John Wiley & Sons, Ltd.