Analysis and design of highly linear triode‐mode based OTA and its application to a wide tunable Gm‐C filter

In this paper, a new highly linear operational transconductance amplifier (OTA) based on triode‐mode input transistors is introduced. An analysis based on theoretical relations and simulation results is presented that aims to obtain the best operating points of triode‐mode and cascode transistors to achieve the highest linearity. The proposed analysis is utilized to design a linear pseudo‐differential OTA, benefiting a linear common mode feedforward and an appropriate common mode feedback circuit. The common mode feedforward circuit is also regulated in the same manner as main the transconductor to stabilize the output common mode voltage during tuning action and achieve higher common mode rejection ratio. Proposed OTA is used to implement a tunable low‐power linear Gm‐C filter. The cutoff frequency of the filter is tunable from 2.7 to 44 MHz while its power consumption changes from 3.5 to 8.5 mW in the entire tuning range. By applying input voltages up to 1.1 Vp‐p, the filter's IM3 remains less than −48 dB for various cutoff frequencies. The proposed OTA and filter are simulated in 0.18‐μ m CMOS technology with Hspice simulator. Copyright © 2017 John Wiley & Sons, Ltd.     

Design methodology for common‐mode stability of OTA‐based gyrators

This paper presents a design methodology for common‐mode (CM) stability of operational transconductance amplifier (OTA)‐based gyrators. The topology of g_m ? C active inductors is briefly reviewed. Subsequently, a comprehensive mathematical analysis on the CM stability of OTA‐based gyrators is presented. Sufficient requirements for the gyrator's CM stability, which easily can be considered during the design process of common‐mode feedback (CMFB) amplifiers, are defined. Based on these stability requirements, a design methodology and a design procedure are proposed. Finally, in order to validate the proposed procedure, a resonator with 20 MHz resonance frequency and a quality factor of 20 is fabricated with UMC 180 nm complementary metal‐oxide‐semiconductor technology, and its CM stability is examined. Copyright © 2015 John Wiley & Sons, Ltd.     

Common‐mode gain reduction technique and its applications

This paper proposes a common‐mode gain reduction technique and a new approach for a balanced‐type system design. Two design examples of a balanced‐type operational transconductance amplifier and a balanced‐type filter are given. The proposed scheme employs the proposed common‐mode gain reduction technique together with the common‐mode feedback (CMFB) network, which is used only to set a bias, to meet requirements of common‐mode rejection. Compared with the conventional method, which uses the CMFB that has a higher gain than the one used in the proposed scheme, the proposed method shows reduction in design complexities and relaxation of the stability conditions. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Design and analysis of power‐CMOS‐gate‐based switched‐capacitor DC–DC converter with step‐down and step‐up modes

A unified multi‐stage power‐CMOS‐transmission‐gate‐based quasi‐switched‐capacitor (QSC) DC–DC converter is proposed to integrate both step‐down and step‐up modes all in one circuit configuration for low‐power applications. In this paper, by using power‐CMOS‐transmission‐gate as a bi‐directional switch, the various topologies for step‐down and step‐up modes can be integrated in the same circuit configuration, and the configuration does not require any inductive elements, so the IC fabrication is promising for realization. In addition, both large‐signal state‐space equation and small‐signal transfer function are derived by state‐space averaging technique, and expressed all in one unified formulation for both modes. Based on the unified model, it is all presented for control design and theoretical analysis, including steady‐state output and power, power efficiency, maximum voltage conversion ratio, maximum power efficiency, maximum output power, output voltage ripple percentage, capacitance selection, closed‐loop control and stability, etc. Finally, a multi‐stage QSC DC–DC converter with step‐down and step‐up modes is made in circuit layout by PSPICE tool, and some topics are discussed, including (1) voltage conversion, output ripple percentage, and power efficiency, (2) output robustness against source noises and (3) regulation capability of converter with loading variation. The simulated results are illustrated to show the efficacy of the unified configuration proposed. Copyright © 2003 John Wiley & Sons, Ltd.     

All‐pass sections with rich cascadability and IC realization suitability

In this paper, two new circuit configurations for realizing voltage‐mode (VM) all‐pass sections (APSs) are presented. The proposed circuits employ only two differential voltage current conveyors (DVCCs) and are cascadable with other VM circuits due to their high‐input and low‐output impedances. The first configuration uses a grounded resistor and a grounded capacitor without requiring matching constraints, whereas the second employs two grounded resistors and a grounded capacitor with a single matching condition. While the first configuration can realize only one all‐pass response, the second can provide inverting and non‐inverting all‐pass responses with selection of appropriate input port. Adding two grounded resistors to the proposed filters, variable gain APSs can also be obtained. As applications, two quadrature oscillators, each of which using one of the proposed all‐pass circuits, one grounded resistor and one grounded capacitor are presented. SPICE simulation results are included to verify the theory. Copyright © 2010 John Wiley & Sons, Ltd.     

A mixed‐mode KHN‐biquad using DVCC and grounded passive elements suitable for direct cascading

In this paper a mixed‐mode (input and output signals can be current or voltage) Kerwin–Huelsman–Newcomb (KHN) biquad with low/high input impedance and high/low output impedance depending on the type of the corresponding signal (current/voltage) is presented. The circuit is constructed using three differential voltage current conveyors (DVCCs), two grounded capacitors and three grounded resistors. The circuit simultaneously provides bandpass (BP), highpass (HP) and lowpass (LP) responses when the output is current and notch, BP and LP responses when the output is voltage. The notch and allpass responses can be obtained by connecting appropriate output currents directly without using additional active elements. Because of the low input and high output impedance of the circuit for current signals and the high input and low output impedance for voltage signals, it can be used in cascade for realizing higher‐order filters. SPICE simulation results are given to verify the theoretical analysis. Copyright © 2008 John Wiley & Sons, Ltd.     

A 0.6 V, 2.11 MHz, 62 dB SFDR active‐RC filter in 0.13µm CMOS process

Active‐RC biquad is proposed, which allows the DC level of the input of operational amplifier (op‐amp) to be different from that of the op‐amp output, enabling the low‐voltage operation. The proposed biquad realizes a second‐order transfer function with only one op‐amp, rendering even lower power consumption. By cascading two biquads, a 0.6 V fourth‐order filter is realized in a 0.13µm CMOS technology. While dissipating only 0.42 mW, the filter shows 2.11 MHz cut‐off frequency and 62 dB spurious‐free dynamic range. Copyright © 2008 John Wiley & Sons, Ltd.     

Analysis and design of an active‐clamping zero‐voltage‐switching isolated inverse‐SEPIC converter

This paper presents an active‐clamping zero‐voltage‐switching (ZVS) isolated inverse‐SEPIC converter. The high voltage spikes when turning off the switches are eliminated. The energies stored in the parasitic elements can be recycled to achieve the ZVS of switches. Therefore, the conversion efficiency increases substantially, yet with a reduced circuit cost. Detailed analysis and design of the proposed topology are described. Experimental results are recorded for a prototype converter with a DC input voltage ranging from 130 to 180 V, an output voltage of 12 V and a rated output power of 120 W, operating at a switching frequency of 65 kHz. The average active‐mode efficiency is above 88%. Copyright © 2010 John Wiley & Sons, Ltd.     

Low‐voltage bulk‐driven input stage with improved transconductance

A low‐voltage input stage constructed from bulk‐driven PMOS transistors is proposed in this paper. It is based on a partial positive feedback and offers significant improvement of both input transconductance and noise performance compared with those achieved by the corresponding already published bulk‐driven structures. The proposed input stage offers also extended input common‐mode range under low supply voltage in relevant to a gate‐driven differential pair. A differential amplifier based on the proposed input stage is also designed, which includes an auxiliary amplifier for the output common‐mode voltage stabilization and a latch‐up protection circuitry. Both input stage and amplifier circuits were implemented with 1 V supply voltage using standard 0.35µm CMOS process, and their performance evaluation gave very promising results. Copyright © 2010 John Wiley & Sons, Ltd.     

Low‐voltage high‐performance current mirrors: Application to linear voltage‐to‐current converter

Current mirror is one of the basic building blocks of analog VLSI systems. For high‐performance analog circuit applications, the accuracy and bandwidth are the most important parameters to determine the performance of the current mirror. This paper presents an efficient implementation of a CMOS current mirror suitable for low‐voltage applications. This circuit combines a shunt input feedback, a regulated cascade output and a differential amplifier to achieve low input resistance, high accuracy and high output resistance. A comparison of several architectures of this scheme based on different architectures of the amplifier is presented. The comparison includes: input impedance, output impedance, accuracy, frequency response and settling time response. These circuits are validated with simulation in 0.18µm CMOS TSMC of MOSIS. In this paper, a linear voltage to current converter, based on the adapted current mirror, is proposed. Its static and dynamic behaviour is presented and validated with the same technology. Copyright © 2009 John Wiley & Sons, Ltd.     

Parameter identification of simplified common‐mode equivalent circuit for inverter‐fed motor drive systems by applying computer‐aided optimization software

This paper deals with common‐mode (CM) electromagnetic interference (EMI) in an inverter‐fed motor drive system. A simplified CM equivalent circuit including π‐type equivalent circuit for the motor winding is proposed by using the waveform of the common‐mode current flowing in the ground conductor. Moreover, a parameter identification method applying the computer‐aided software modeFRONTIER is proposed to decide objectively the circuit parameters of the proposed simplified equivalent circuit. Validity and effectiveness of the proposed equivalent circuit are confirmed by comparing the measured impedance characteristics with the calculated ones. Finally, the possibility of a nonlinear phenomenon is discussed in this system. It is shown that the accuracy of simulation result can be improved by introducing the nonlinear element. © 2015 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A single‐stage phase‐shifted full‐bridge AC/DC converter with variable frequency control

This letter presents a single‐stage soft‐switched full‐bridge AC/DC converter for low‐voltage/high‐current output applications. A phase‐shifted method with a variable frequency control is used to regulate the DC bus voltage and the output voltage of the single‐stage AC/DC converter. The proposed circuit topology and control scheme exhibit superior performances (i.e. high power factor, high‐efficiency, and ring‐free features). Correspondingly, a laboratory prototype, 500 W 5V/100A AC/DC converter, is implemented to verify the feasibility of the proposed design. Copyright © 2009 John Wiley & Sons, Ltd.     

Current‐mode dual‐output ICCII‐based tunable universal biquadratic filter with low‐input and high‐output impedances

A new tunable current‐mode (CM) biquadratic filter with three inputs and three outputs using three dual‐output inverting second‐generation current conveyors, three grounded resistors and two grounded capacitors is proposed. The proposed circuit exhibits low‐input impedance and high‐output impedance which is important for easy cascading in the CM operations. It can realize lowpass, bandpass, highpass, bandreject and allpass biquadratic filtering responses from the same topology. The circuit permits orthogonal controllability of the quality factor Q and resonance angular frequency ω_o, and no component matching conditions or inverting‐type input current signals are imposed. All the passive and active sensitivities are low. Hspice simulation results are based on using TSMC 0.18 µm 1P6M process complementary metal oxide semiconductor technology and supply voltages ±0.9 V to verify the theoretical analysis. Copyright © 2012 John Wiley & Sons, Ltd.     

0.5‐V bulk‐driven differential amplifier

A new 0.5‐V fully differential amplifier is proposed in this article. The structure incorporates a differential bulk‐driven voltage follower with conventional gate‐driven amplification stages. The bulk‐driven voltage follower presents differential gain equal to unity while suppressing the input common‐mode voltage. The amplifier operates at a supply voltage of less than 0.5 V, performing input transconductance almost equal to a gate transconductance and relatively high voltage gain without the need for gain boosting. The circuit was designed and simulated using a standard 0.18‐µm CMOS n‐well process. The low‐frequency gain of the amplifier was 56 dB, the unity gain bandwidth was approximately 3.2 MHz, the spot noise was 100 nV/√Hz at 100 kHz and the current consumption was 90 μΑ. Copyright © 2012 John Wiley & Sons, Ltd.     

A common‐mode replica compensated inductor–capacitor voltage‐controlled oscillator for mixed‐signal system‐on‐chip applications

A novel 1.57 GHz complementary metal–oxide semiconductor inductor–capacitor voltage‐controlled oscillator with the common‐mode replica compensation is introduced for mixed‐signal system‐on‐chip applications. In order to alleviate power line disturbances, the center tap node of differential symmetric inductor and the replica biasing circuit are adopted in the differential voltage regulating unit to reduce power supply sensitivity. In addition, this proposed design also leads to low tuning gain and low power dissipation. The post‐layout simulation results under the Taiwan Semiconductor Manufacturing Company's mixed‐signal 0.18 µm 1P6M process show that the proposed design achieves power supply rejection of ?68.6 dB at low frequencies and 1.2 MHz/V pushing sensitivity. It exhibits phase noise of ?130.6 dBc/Hz at a 1 MHz offset from a 1.57 GHz carrier yet dissipates only 5.58 mW under a 1.8 V power supply. Copyright © 2011 John Wiley & Sons, Ltd.     

High‐efficiency grid‐connected inverter topology for low‐power photovoltaic applications

For low‐power applications, such as household photovoltaic panels, the efficiency and reliability of the distributed generation system is an important issue. A high‐efficiency inverter topology derived from the normal full‐bridge circuit is proposed for grid‐connected photovoltaic applications. In the proposed topology, a couple of diodes are added in parallel with the grid‐frequency switches as freewheeling diodes working during the positive and negative half‐cycles of the utility voltage, respectively, thus preventing the output current from flowing through the body diodes of switches. Because of its natural configuration, simple operation, and three‐level function, the proposed topology features a high level of efficiency and reliability over a wide voltage range, and allows the best cost–effective ratio. These characteristics are compared with those of other existing advanced topologies, followed by a theoretical analysis on the output filter and the implemented circuit of modulation scheme. Experimental results from a 3 kW hardware prototype verify the feasibility of the proposed solution. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A minimum five‐component five‐term single‐nonlinearity chaotic jerk circuit based on a twin‐jerk single‐op‐amp technique

A minimum 5‐component 5‐term single‐nonlinearity chaotic jerk circuit is presented as the first simplest chaotic jerk circuit in a category that a single op‐amp is employed. Such a simplest circuit displays 5 simultaneous advantages of (1) 5 minimum basic electronic components, (2) 5 minimum algebraic terms in a set of 3 coupled first‐order ordinary differential equations (ODEs), (3) a single minimum term of nonlinearity in the ODEs, (4) a simple passive component for nonlinearity, and (5) a single op‐amp. The proposed 5‐term single‐nonlinearity chaotic jerk circuit and a slightly modified version of an existing 6‐term 2‐nonlinearity chaotic jerk circuit form mirrored images of each other. Although both mirrored circuits yield 2 different sets of the ODEs, both sets however can be recast into a pair of twin jerk equations. Both mirrored circuits are therefore algebraically twin 5‐component chaotic jerk circuits, leading to a twin‐jerk single‐op‐amp approach to the proposed minimum chaotic jerk circuit. Two cross verifications of trajectories of both circuits are illustrated through numerical and experimental results. Dynamical properties are also presented.     

A non‐isolated high step‐up DC‐DC converter with integrated 3 winding coupled inductor and reduced switch voltage stress

In this paper, a non‐isolated high step‐up dc‐dc converter based on coupled inductor is proposed. The proposed converter can be used in renewable energy applications. In suggested converter, the high voltage is achieved using 3‐winding coupled inductor, which leads to low voltage rate of the switch. A clamp circuit is used to recycle the leakage inductance energy. Also, the clamp circuit prevents the creation of voltage spikes on semiconductor devices and causes the voltage stress of elements are limited to less than the output voltage. The presented theoretical analyses show that the operation of suggested converter in continuous conduction mode needs to small magnetic inductor. Therefore, the size of coupled inductor's core is reduced, and so the size and cost of presented converter will be decreased. Analysis of the proposed converter is provided with laboratory results to verify its performance.     

CMOS high‐precision loser‐take‐all circuit

This paper presents a new current‐mode CMOS loser‐take‐all circuit. The proposed circuit consists of a basic cell that allows implementation of a multi‐input configuration by repeating the cell for each additional input. A high‐speed feedback structure is employed to determine the minimum current among the applied inputs. The significant feature of the circuit is its high accuracy and high‐speed operation. Additionally, the input dynamic range of the circuit can be efficiently controlled via the biasing current. HSPICE simulation results are presented to verify the performance of the circuit, where under a supply voltage of 2.5 V, bias current of 100 µA, and frequency of 10 MHz, the input dynamic range increases within 0–100 µA and the corresponding error remains as low as 0.4%. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Analytical synthesis of voltage‐mode even/odd‐nth‐order differential difference current conveyor and fully differential current conveyor II‐grounded resistor and capacitor universal filter structures

A complete definition of an odd/even‐nth‐order notch or band‐reject filter transfer function is presented. Based on the differences between the input voltage and (i) an nth‐order high‐pass; (ii) a traditional nth‐order notch; and (iii) an nth‐order all‐pass filtering transfer function, a systematic method has been proposed to derive a universal filter structure that can realize voltage‐mode odd/even‐nth‐order low‐pass, band‐pass, high‐pass, all‐pass and traditional notch filters. The intrinsic capability of voltage‐mode addition and subtraction of the two active elements, differential difference current conveyors and fully differential current conveyors, is used to advantage in the aforementioned synthesis procedure. Based upon the definition of an nth‐order notch or band‐reject filter transfer function proposed in this paper, the aforementioned universal one has been further extended to the newly defined nth‐order band rejection filter. The voltage and current tracking errors of the two active elements are compensated by varying the resistances of the proposed filter. Filtering feasibility, stability, component sensitivities, linear and dynamic ranges, power consumption, and noise are simulated using H‐Spice with 0.35 µm process. Compared to some of the recently reported universal biquads, the new one is shown to enjoy the lowest component sensitivities and the best output accuracy for all‐pass signals. Moreover, Monte Carlo and two‐tone tests for intermodulation linearity simulations are also investigated. Copyright © 2014 John Wiley & Sons, Ltd.