Realization of log‐domain high‐order transfer functions using first‐order building blocks and complementary operators

High‐order log‐domain filters could be easily designed by using the functional block diagram (FBD) representation of the corresponding linear prototype and a set of complementary operators. For this purpose, lossy and lossless integrator blocks have been already introduced in the literature. Novel first‐order log‐domain highpass and allpass filter configurations, which are fully compatible with the already published integrator blocks, are introduced in this paper. These are realized using integration and subtraction blocks or a novel differentiation configuration. As a result, a complete set of first‐order building blocks would be available for synthesizing any arbitrary high‐order transfer function. In order to verify the correct operation of the proposed structures, the performance of the introduced highpass filters was evaluated through simulation results. In addition, a fifth‐order log‐domain bandpass filter was designed and simulated using one of the introduced first‐order highpass filter configurations. Copyright © 2006 John Wiley & Sons, Ltd.     

Analysis and implementation of a fourth‐order bandpass filter for R‐wave detection of an implantable cardiac microstimulator

This paper presents an ultra‐low‐power fourth‐order bandpass operational transconductance amplifier‐C (OTA‐C) filter for an implantable cardiac microstimulator used to detect the R‐wave of intracardiac electrograms. The OTA‐C filter fabricated by TSMC 0.35‐µm complementary metal–oxide–semiconductor (CMOS) technology is operated in the subthreshold region to save power under a supply voltage of 1 V. The current cancellation technique is adopted to reduce the transconductance of the amplifier. Through this, the low‐frequency OTA‐C filter can be realized by ultra‐low transconductance with on‐chip capacitors. Direct comparison to conventional RLC ladders replaced by OTA‐C circuits shows that the method of reducing the number of OTAs further diminishes power consumption. Design issues, including ultra‐low transconductance, linearity, and noise, are also discussed. Measurement results show that the low‐voltage, low‐power filter has a bandwidth between 10 and 50 Hz, third inter‐modulation distortion of ?40 dB, dynamic range of 43 dB, and power consumption of only 12 nW. The real electrocardiography signal is fed into the bandpass filter to verify the function of signal processing with the distribution of the R‐wave. Copyright © 2012 John Wiley & Sons, Ltd.     

Convergence of discrete‐time cellular neural networks with interlaced block‐sequential dynamics

Some interlaced block‐sequential modes of operation are introduced for discrete‐time cellular neural networks (DTCNN), and the corresponding convergence conditions are investigated. It is proved that DTCNNs, under some block‐sequential updating rules, result to be convergent when the feedback templates satisfy some restrictions rather milder than reciprocity or dominance, as required in synchronous mode. Moreover, the set of fixed points of the network results to be independent of the particular updating rule adopted. The drawback of desynchronization is a reduced speed of convergence, which however is tolerable in the usual case when the neighbourhood radius is small. Copyright © 1999 John Wiley & Sons, Ltd.     

1.5 V square‐root domain universal biquad filters

Square‐root domain universal biquad topologies are introduced in this paper. One of them is single input multiple output, while the other one is multiple input single output biquad. Important benefits offered by the proposed topologies are the electronic adjustment of the resonant frequency and the capability for operating in a low‐voltage environment; also, the resonant frequency could be adjusted without disturbing the Q factor and vice‐versa. Simulation results using the Spectre simulator of the Analog Design Environment of Cadence software validate the correct operation of the proposed topologies and provide important performance characteristics. Copyright © 2011 John Wiley & Sons, Ltd.     

High input impedance voltage‐mode first‐order all‐pass sections

This paper proposes six new first‐order voltage‐mode all‐pass sections (VM‐APSs) based on three general topologies. Each circuit uses two differential voltage current conveyors and three grounded passive components. All the circuits possess high input impedance and easy control of pole frequency either by a simple matching of resistors (two equal‐valued resistors) for the three canonical circuits or by a single resistor for three non‐canonical circuits. PSPICE simulation results using real device 0.5µ CMOS parameters are given to validate the proposed circuits. Copyright © 2007 John Wiley & Sons, Ltd.     

Analytical synthesis and comparison of voltage‐mode Nth‐order OTA‐C universal filter structures

Complementary single‐ended‐input operational transconductance amplifier (OTA)‐based filter structures are introduced in this paper. Through two analytical synthesis methods and two transformations, one of which is to convert a differential‐input OTA to two complementary single‐ended‐input OTAs, and the other to convert a single‐ended‐input OTA and grounded capacitor‐based one to a fully differential OTA‐based one, four distinct kinds of voltage‐mode nth‐order OTA‐C universal filter structures are proposed. TSMC H‐Spice simulations with 0.35µm process validate that the new complementary single‐ended‐input OTA‐based one holds the superiority in output precision, dynamic and linear ranges than other kinds of filter structures. Moreover, the new voltage‐mode band‐pass, band‐reject and all‐pass (except the fully differential one) biquad structures, all enjoy very low sensitivities. Both direct sixth‐order universal filter structures and their equivalent three biquad stage ones are also simulated and validated that the former is not absolutely larger in sensitivity than the latter. Finally, a very sharp increment of the transconductance of an OTA is discovered as the operating frequency is very high and leads to a modified frequency‐dependent transconductance. Copyright © 2010 John Wiley & Sons, Ltd.     

All‐MOS implementation of RC networks for time‐controlled Gaussian spatial filtering

This paper addresses the design and VLSI implementation of MOS‐based RC networks capable of performing time‐controlled Gaussian filtering. In these networks, all the resistors are substituted one by one by a single MOS transistor biased in the ohmic region. The design of this elementary transistor is carefully realized according to the value of the ideal resistor to be emulated. For a prescribed signal range, the MOSFET in triode region delivers an interval of instantaneous resistance values. We demonstrate that, for the elementary 2‐node network, establishing the design equation at a particular point within this interval guarantees minimum error. This equation is then corroborated for networks of arbitrary size by analyzing them from a stochastic point of view. Following the design methodology proposed, the error committed by an MOS‐based grid when compared with its equivalent ideal RC network is, despite the intrinsic nonlinearities of the transistors, below 1% even under mismatch conditions of 10%. In terms of image processing, this error hardly affects the outcome, which is perceptually equivalent to that of the ideal network. These results, extracted from simulation, are verified in a prototype vision chip with QCIF resolution manufactured in the AMS 0.35µm CMOS‐OPTO process. This prototype incorporates a focal‐plane MOS‐based RC network that performs fully programmable Gaussian filtering. Copyright © 2011 John Wiley & Sons, Ltd.     

Compact CMOS implementation of a low‐power,current‐mode programmable cellular neural network

We report on the design and characterization of a full‐analog programmable current‐mode cellular neural network (CNN) in CMOS technology. In the proposed CNN, a novel cell‐core topology, which allows for an easy programming of both feedback and control templates over a wide range of values, including all those required for many signal processing tasks, is employed. The CMOS implementation of this network features both low‐power consumption and small‐area occupation, making it suitable for the realization of large cell‐grid sizes. Device level and Monte Carlo simulations of the network proved that the proposed CNN can be successfully adopted for several applications in both grey‐scale and binary image processing tasks. Results from the characterization of a preliminary CNN test‐chip (8×1 array), intended as a simple demonstrator of the proposed circuit technique, are also reported and discussed. Copyright © 2001 John Wiley & Sons, Ltd.     

A class of digitally programmable nth‐order filters

A family of new high‐order filters capable of providing all filter functions without changing the circuit topology is proposed for integrated circuit applications. The proposed filters are based on simple active elements, namely, digitally controlled current amplifiers (DCCAs) and unity gain voltage buffers (VBs). Gains of DCCAs are digitally programmed to adjust the coefficients of transfer functions. R2R ladders are also utilized to increase the tuning flexibility of the proposed filters. A filter replicating the famous KHN biquad is extended to realize general nth‐order filters. Comparison with the recent works shows that the proposed approach results in more efficient realizations compared with its counterparts based on other current‐mode active elements. Experimental results obtained from a fourth‐order filter implemented using devices fabricated in a 0.35‐µm CMOS process are provided. Copyright © 2011 John Wiley & Sons, Ltd.     

Function‐in‐layout: a demonstration with bio‐inspired hyperacuity chip

Below 100 nm a new scenario is emerging in VLSI design: floorplanning and function are inherently interrelated. Using mainly local connectivity, wire delay and crosstalk problems are eliminated. A new design methodology is proposed, called function‐in‐layout, that possesses: regular layout, mainly local connectivity, functional ‘parasitics’. A bio‐inspired demonstration is presented, a hyperacuity chip, with 30 ps time difference detection using 0.35 mm complementary metal‐oxide semiconductor (CMOS) technology. Copyright © 2006 John Wiley & Sons, Ltd.     

FDCCII‐based electronically tunable voltage‐mode biquad filter

In this work, a voltage‐mode biquad filter realizing low‐pass, band‐pass and high‐pass characteristics is presented. The proposed filter, which employs two FDCCIIs, two grounded capacitors and two NMOS transistors, provides electronic tunability with the control voltage applied to the gate. NMOS transistors act as linear resistor. Furthermore, the proposed circuit still enjoys realization using a low number of active and passive components, no requirement with the component choice conditions to realize specific filtering functions, high input impedance, and low active and passive sensitivities performance. Simulation results using SPICE program are given to show the performance of the filter and verify the theory. Copyright © 2010 John Wiley & Sons, Ltd.     

Analytical synthesis of odd/even‐nth‐order elliptic Cauer filter structures using OTRAs

The operational transresistance amplifier (OTRA), the dual of the well‐known operational transconductance amplifier, is an attractive element for use in circuit design. One odd‐nth‐order and two even‐nth‐order OTRA‐R‐C or OTRA‐MOS‐C elliptic Cauer filter structures are presented using new analytical synthesis methods (ASMs). Because it is assumed in the synthesis procedure that the transresistance R_m → ∞, but in view of the fact that R_m is finite in practice, the more the number of OTRAs employed, the worse the precision of the output signals. By studying the sensitivity of the output to component variations, more precise output may be obtained by selecting one or two appropriate capacitance(s)/resistance(s) and adjusting their values suitably. H‐spice simulations are given to validate and demonstrate the theoretical predictions. Copyright © 2012 John Wiley & Sons, Ltd.     

Design of a CMOS multi‐rate adaptive continuous‐time equalizer based on power spectrum estimation

An adaptive continuous‐time equalizer for reliable short‐haul high‐speed serial communications is described in this paper. The adaptive equalizer uses the spectrum‐balancing technique to adapt its response to changes in the bandwidth, amplitude, and bit rate of the input signal. In this way, it is able to compensate the frequency response of a 1‐mm diameter step‐index plastic optical fiber, for lengths up to 50 m, and bit rates ranging from 400 Mb/s to 2.5 Gb/s. Experimental results are shown to demonstrate its feasibility. Copyright © 2017 John Wiley & Sons, Ltd.     

Performance analysis of velocity–pressure smoothing for direction‐of‐arrival estimation of coherent signals

In this paper, we consider the problem of direction‐of‐arrival (DOA) estimation of coherent signals by using a number of identically oriented acoustic vector‐sensors, wherein source decorrelation can be achieved by velocity–pressure smoothing. We examine the effect of velocity–pressure smoothing on the performance of MUSIC‐type methods in terms of the overall root mean‐square errors (RMSE) of DOA estimates. The closed‐form expression for the overall RMSE is derived and analyzed. We also compare velocity–pressure smoothing with the conventional spatial smoothing technique. Simulation results are given to confirm the analyses. Copyright © 2009 John Wiley & Sons, Ltd.     

Adaptive homo‐backstepping tracking control for strict‐feedback systems in presence of unknown dead‐zones

An adaptive homo‐backstepping control for nonlinear strict‐feedback systems subjected to unknown actuator dead‐zone and disturbance is investigated. A sliding‐mode‐based integral filter is constructed and used to approximate the desired feedback control in the backstepping‐like recursive design technique. Subsequently, the problem of “explosion of complexity” is solved by obviating the analytic derivatives deduction for virtual control in the conventional backstepping technology. The actuator dead‐zone dynamic is modeled as the combination of a line and a disturbance‐like term, which makes the controller design simpler. The interconnected control module and filter module in the resulting closed‐loop system satisfy the input‐to‐state practically stability‐modularity condition, provided that the small‐gain theorem is exploited to ensure the stability of closed‐loop system. The proposed approach cannot only mitigate the effect of dead‐zone but also solve the problem of explosion of complexity in the previous literature. Numerical simulations performed on a manipulator with a brushed DC motor are introduced to illustrate the effectiveness of underlying control scheme.     

Design of Sinh‐Domain filters using complementary operators

A new systematic method for designing Sinh‐Domain filters is introduced in this paper. This is achieved by employing an appropriate set of complementary operators, in order to transpose the conventional functional block diagram representation of each linear operation to the corresponding one into the Sinh‐Domain. The proposed method offers the benefits of facilitating the design procedure of high‐order Sinh‐Domain filters and of the absence of any restriction concerning the type and/or the order of the realized filter function. As an example, a third‐order Sinh‐Domain leapfrog filter is designed by employing the proposed set of operators. Two possible realizations are given and their performance has been evaluated and compared through simulation results. Copyright © 2011 John Wiley & Sons, Ltd.     

A wideband time‐based continuous‐time sigma‐delta modulator with 2nd order noise‐coupling based on passive elements

Embedding the time encoding approach inside the loop of the sigma‐delta modulators has been shown as a promising alternative to overcome the resolution problems of analog‐to‐digital converters in low‐voltage complementary metal‐oxide semiconductor (CMOS) circuits. In this paper, a wideband noise‐transfer‐function (NTF)‐enhanced time‐based continuous‐time sigma‐delta modulator (TCSDM) with a second‐order noise‐coupling is presented. The proposed structure benefits from the combination of an asynchronous pulse width modulator as the voltage‐to‐time converter and a time‐to‐digital converter as the sampler to realize the time quantization. By using a novel implementation of the analog‐based noise‐coupling technique, the modulator's noise‐shaping order is improved by two. The concept is elaborated for an NTF‐enhanced second‐order TCSDM, and the comparative analytical calculations and behavioral simulation results are presented to verify the performance of the proposed structure. To further confirm the effectiveness of the presented structure, the circuit‐level implementation of the modulator is provided in Taiwan Semiconductor Manufacturing Company (TSMC) 90 nm CMOS technology. The simulation results show that the proposed modulator achieves a dynamic range of 84 dB over 30 MHz bandwidth while consuming less than 25 mW power from a single 1 V power supply. With the proposed time‐based noise‐coupling structure, both the order and bandwidth requirements of the loop filter are relaxed, and as a result, the analog complexity of the modulator is significantly reduced. Copyright © 2015 John Wiley & Sons, Ltd.     

Low‐voltage low‐power CMOS receiver front‐end for gigabit short‐reach optical communications

This article presents a new CMOS receiver analog front‐end for short‐reach high‐speed optical communications, which compensates the limited product bandwidth length of 1‐mm step‐index plastic optical fiber (SI‐POF) channels (45 MHz · 100 m) and the required large‐diameter high‐capacitance Si PIN photodetector (0.8 mm–3 pF). The proposed architecture, formed by a transimpedance amplifier and a continuous‐time equalizer, has been designed in a standard 0.18‐µm CMOS process with a single supply voltage of only 1 V, targeting gigabit transmission for simple no‐return‐to‐zero modulation consuming less than 23 mW. Experimental results validate the approach for cost‐effective gigabit SI‐POF transmission. Comparative analysis with previously reported POF receivers has been carried out by introducing a useful figure of merit. Copyright © 2012 John Wiley & Sons, Ltd.     

A simulation study of high‐order CMOS hyperbolic‐sine filters

This paper advances the field of externally linear–internally nonlinear (ELIN) filters by introducing a synthesis method that enables the design of high‐order class‐AB sinh filters by means of complementary metal–oxide semiconductor (CMOS) weak‐inversion sinh integrators comprising only one type of devices in their translinear loops. The proposed transistor‐level synthesis approach is demonstrated through the examples of (1) a biquadratic and (2) a fifth‐order filter, and their simulated performance is studied. The biquadratic filter achieves a dynamic range of 94 dB and has a tunable quality factor Q up to the value of 8, whereas its natural frequency can be tuned for four orders of magnitude. Its static power consumption amounts to 6.2 μW for Q = 1 and f_o = 2 kHz. The fifth‐order Chebyshev sinh CMOS filter with a cut‐off frequency of 100 Hz, a pass band ripple of 1 dB, and a power consumption of ~300 nW is compared head‐to‐head with its pseudo‐differential class‐AB CMOS log domain counterpart. The sinh filter achieves similar or better signal‐to‐noise ratio (SNR) and signal‐to‐noise‐plus‐distortion ratio (SNDR) performances with half the capacitor area but at the expense of higher power consumption from the same power supply level. All three presented filter topologies are novel. Cadence design framework simulations have been performed using the commercially available 0.35 µm AMS (austriamicrosystems) process parameters. Copyright © 2013 John Wiley & Sons, Ltd.     

All‐pass dispersion synthesis using microwave C‐sections

A closed‐form iterative procedure for synthesizing quasi‐arbitrary phase responses with cascaded microwave C‐section all‐pass phasers is presented. The synthesis consists in mapping the transmission poles of the cascaded C‐section structure onto the transmission poles of the specified transfer function, where the latter poles are computed using a closed‐form polynomial generation method. The real and complex transmission poles of the specified transfer function are realized using C‐sections of different lengths and different couplings coefficients. The proposved synthesis is validated by both full‐wave analysis and measured multilayer prototypes. Copyright © 2013 John Wiley & Sons, Ltd.