A minimum five‐component five‐term single‐nonlinearity chaotic jerk circuit based on a twin‐jerk single‐op‐amp technique

A minimum 5‐component 5‐term single‐nonlinearity chaotic jerk circuit is presented as the first simplest chaotic jerk circuit in a category that a single op‐amp is employed. Such a simplest circuit displays 5 simultaneous advantages of (1) 5 minimum basic electronic components, (2) 5 minimum algebraic terms in a set of 3 coupled first‐order ordinary differential equations (ODEs), (3) a single minimum term of nonlinearity in the ODEs, (4) a simple passive component for nonlinearity, and (5) a single op‐amp. The proposed 5‐term single‐nonlinearity chaotic jerk circuit and a slightly modified version of an existing 6‐term 2‐nonlinearity chaotic jerk circuit form mirrored images of each other. Although both mirrored circuits yield 2 different sets of the ODEs, both sets however can be recast into a pair of twin jerk equations. Both mirrored circuits are therefore algebraically twin 5‐component chaotic jerk circuits, leading to a twin‐jerk single‐op‐amp approach to the proposed minimum chaotic jerk circuit. Two cross verifications of trajectories of both circuits are illustrated through numerical and experimental results. Dynamical properties are also presented.     

A low distortion CMOS continuous‐time common‐mode feedback circuit

In high‐gain fully differential operational amplifier (FD op‐amp) design, the output common‐mode (CM) voltage of the FD op‐amp is quite sensitive to device properties and mismatch. It is, therefore, necessary to add an additional control circuit, referred to as the common‐mode feedback (CMFB) circuit, to stabilize the output CM voltage at some specified voltage. In this paper, we present a high linear CMOS continuous‐time CMFB circuit based on two differential pairs and the source degeneration using MOS transistors. Theoretical analysis and SPICE simulation results are provided to validate our proposed ideas. Finally, we present two design applications of the proposed configuration, one is the FD folded‐cascode op‐amp and the other is the Multiply‐by‐Two circuit which is the key component in the popular 1.5 bit/stage pipelined analog‐to‐digital converter. Comparison with conventional topologies shows that the new configuration has attractive characteristics concerning their implementation in high linear analog integrated circuits. Copyright © 2010 John Wiley & Sons, Ltd.     

A new efficient SC integrator scheme for high‐speed low‐power applications

A new solution to implement efficient switched‐capacitor (SC) integrators is presented. In the proposed scheme, voltage buffers are opportunely introduced in order to prevent direct connection between the output and the capacitive feedback network of the circuit that characterizes classical SC integrator topologies during the charge transfer phase. Design guidelines to optimize the settling performances of the proposed circuit are also given. To demonstrate the possible advantages of the new solution, the proposed integrator is designed in a commercial 0.35?µm CMOS technology. It is shown that compared with classical SC integrator topologies, the proposed configuration allows a significant improvement of the integrator speed to be achieved for a given power budget. Copyright © 2010 John Wiley & Sons, Ltd.     

Design approach for high‐bandwidth low‐power three‐stage operational amplifiers

A new design approach to optimize the frequency compensation network of three‐stage operational amplifiers (op‐amps) is presented. The proposed criterion is aimed at maximizing the bandwidth of well‐established three‐stage op‐amps using Nested‐Miller Compensation with feedforward tranconductance stage and nulling resistor (NMCFNR). As shown by design examples in a commercial 0.35‐µm CMOS technology, the proposed approach allows the amplifier bandwidth to be enhanced significantly with respect to that resulting from using existing design strategies for NMCFNR op‐amps. It is also demonstrated that NMCFNR op‐amps, designed according to the proposed method, even guarantee larger values of the gain‐bandwidth product than three‐stage amplifiers using more complicated frequency compensation techniques, such as AC boosting compensation or damping‐factor control frequency compensation. Copyright © 2010 John Wiley & Sons, Ltd.     

Three‐stage nested‐Miller‐compensated operational amplifiers: Analysis,design, and optimization based on settling time

In analog signal‐processing applications, settling performance of the employed operational amplifiers (opamps) is usually of great matter. Under low‐voltage environment of modern technologies where only a few transistors are allowed to be stacked, three‐stage amplifiers are gaining more interest. Unfortunately, design and optimization of three‐stage opamps based on settling time still suffer from lack of a comprehensive analysis of the settling behavior and closed‐form relations between settling time/error and other parameters. In this paper, a thorough analysis of the settling response of three‐stage nested‐Miller‐compensated opamps, including linear and non‐linear sections, is presented. This analysis leads to a design methodology which determines the circuit requirements for desired settling time/error. Based on settling time, it allows optimizations in power consumption and area. Copyright © 2010 John Wiley & Sons, Ltd.     

Linear circuits: a measurement‐based approach

This paper proposes a new measurement‐based approach that can solve synthesis problems in unknown linear circuits. The method makes use of a small number of measurements to determine the functional dependency of any circuit signal or variable on any set of design variables. Once the functional dependency is obtained, the design requirements can be applied to find the design parameter values. The results are described for linear direct current and alternating current circuits. Copyright © 2013 John Wiley & Sons, Ltd.     

Robust design of CMOS amplifiers oriented to settling‐time specification

In this paper, we propose a new approach for the robust design of complementary metal‐oxide‐semiconductor amplifiers based on settling‐time specifications. The approach is based on the definition of the separation factors and on the analysis of their role in the settling time. We define a design strategy for being certain that an OTA satisfies the settling‐time constraint under any statistical variation of process or design parameters. The proposed strategy is applied to the transistor level design of a two‐stage amplifier and a three‐stage one. Simulation results, in good agreement with theory, confirm the validity of the proposed approach. Copyright © 2016 John Wiley & Sons, Ltd.     

Direct analysis and synthesis of multiphase switched-current networks using signal-flow graphs

A by-inspection analysis and synthesis method for multiphase switched-current (SI) circuits using signal-flow graph (SFG) techniques is presented. The SFG is derived on the transistor level and the method is primarily useful for the hand analysis and design of small and medium-size SI circuits (e.g. SI filters, decimators, interpolators). Tables of commonly used SI circuits, in which the corresponding SFGs and circuits are given, make the derivation easy and fast. From the SFGs, not only the overall discrete-time transfer function, but also those in-between individual switching phases, are obtainable. With the proposed method it is straightforward to include non-ideal effects, such as finite output resistance of MOS transistors, clock-feedthrough and settling error. The method is also a useful tool for the synthesis of new SI circuits. It is shown that every low-sensitivity switched-capacitor (SC) circuit can be mapped directly into a low-sensitivity SI circuit with a corresponding topology. Examples of transformed SC circuits are given and two new double sampling integrators are introduced. © 1998 John Wiley & Sons, Ltd.     

νMOS cellular‐automaton circuit for picture thinning and shrinking

In this study we propose a design for an LSI circuit that implements a cellular automaton. The cellular automaton is a parallel and distributed architecture device suitable for high‐speed image processing. To develop a cellular automaton LSI circuit, it is necessary to design small‐size unit cell circuits that can operate according to cell–cell interaction rules. We propose to use νMOSFET devices for such cell circuits. Template matching is implemented by combining multiple input νMOSFET circuits and inverters. A cell circuit was designed for image thinning and shrinking, and its operation was analyzed using a circuit simulator. It was demonstrated that high speed operation (up to 100 MHz clock frequency) can be obtained. © 1999 Scripta Technica, Electr Eng Jpn, 126(3): 41–48, 1999     

Soft computing‐based approach for optimal design of on‐chip comparator and folded‐cascode op‐amp using colliding bodies optimization

This paper presents an efficient approach for the optimal designs of two analog circuits, namely complementary metal oxide semiconductor) two‐stage comparator with p‐channel metal oxide semiconductor input driver and n‐channel input and folded‐cascode operational amplifier using a recently proposed meta‐heuristic‐based optimization algorithm named as colliding bodies optimization (CBO). It is a multi‐agent algorithm that does not depend upon any internal control parameter, making the algorithm extremely simple. The main objective of this paper is to optimize the metal oxide semiconductor (MOS) transistors' sizes using CBO in order to reduce the areas occupied by the circuits and to get better performance parameters of the circuits. Simulation Program with Integrated Circuit Emphasis simulation has been carried out by using the optimal values of MOS transistors' sizes and other design parameters to validate that CBO‐based design is satisfying the desired specifications. Simulation results demonstrate that the design specifications are closely met and the required functionalities are achieved. The simulation results also confirm that the CBO‐based approach is superior to the other algorithms in terms of MOS area and performance parameters like gain, power dissipation, etc., for the examples considered. Copyright © 2016 John Wiley & Sons, Ltd.     

Design‐oriented model for power‐driven design optimization of SC‐ΣΔ modulators

A behavioral model for switched‐capacitors sigma‐delta modulators, suitable for power‐driven design, is presented. Because of the oversampling behavior of this kind of analog‐to‐digital converters, transistor‐level simulations are extremely time consuming. Thus, accurate behavioral models are mandatory in the preliminary design steps to cut the development time. However, when the power consumption of the modulator is pushed down to the absolute minimum level, second‐order effects affecting the settling behavior of the switched‐capacitor integrator must be taken into account. Furthermore, by means of an accurate noise model, based on a second‐order transfer function of the amplifier, a global power minimization is achieved, and the optimum partitioning between the switch and op‐amp noise is obtained. In spite of the improved accuracy, the proposed model requires only a few parameters of the amplifier in the integrator. This allows to easily link the model to an external set of circuit equations, to be derived for the specific amplifier used in the modulator. The model was used in the design of a third‐order modulator in an STM 90‐nm technology. The silicon samples exhibit an effective resolution of 15.2‐b with a 500‐Hz output rate, an oversampling ratio of 500, and a Schreier figure‐of‐merit of 162 dB, with a 38‐μW power consumption at 1.2‐V supply.     

Four‐segment oscillator circuit for piezoelectric sensing devices

Novel circuit design is proposed for a low‐frequency quartz crystal oscillator circuit that consists of four segments. The characteristics of the negative resistance in a low‐frequency Complementary Metal Oxide Semiconductor (CMOS)‐inverter quartz oscillator were reviewed for the two modes of SC (stress‐compensated) cut mode and the overtone of low‐frequency mode; separation of two modes and suppression of overtone oscillation were demonstrated successfully. Experimental results and an estimate of the absolute value of the negative resistance are presented for the four‐segment oscillator circuit and the conventional Colpitts circuit and two new types of oscillator circuits. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Bessel‐like compensation of three‐stage operational transconductance amplifiers

In this paper, we introduce a simple and well‐defined approach for the design of fast settling amplifiers suitable for switched‐capacitor circuits and characterized by low capacitive loads, in the order of few pico‐farad. In the specific, the design is based on a new Bessel‐like compensation that sets the phase of the closed‐loop amplifier to be linearly related to the frequency, thus emulating the behavior of an ideal delay, like in a Bessel filter. The proposed Bessel‐like approach is validated through the design and the simulation of two 3‐stage amplifiers in a 65‐nm CMOS process.     

Modeling of dipole–dipole‐coupled,electric field‐driven,protein‐based computing architectures

In the present study, we propose a novel approach for the realization of protein‐based logic circuits potentially suitable for nanoscale digital signal processing and computing architectures. Electric field‐induced switching of Dronpa, an artificial protein, is demonstrated through simulations with the NAMD molecular dynamics simulation software, and a circuit model that describes such switching behavior is presented. Simulations suggest that digital signal propagation and the majority gate can be realized by the utilization of such proteins if they are dipole–dipole coupled and are driven by proper electric fields. Copyright © 2013 John Wiley & Sons, Ltd.     

±0.18‐V supply voltage gate‐driven PGA with 0.7‐Hz to 2‐kHz constant bandwidth and 0.15‐μW power dissipation

A simple gate‐driven scheme to reduce the minimum supply voltage of AC coupled amplifiers by close to a factor of two is introduced. The inclusion of a floating battery in the feedback loop allows both input terminals of the op‐amp to operate very close to a supply rail. This reduces essentially supply requirements. The scheme is verified experimentally with the example of a PGA that operates with ±0.18‐V supply voltages in 0.18‐μm CMOS technology and a power dissipation of about 0.15 μW. It has a 4‐bit digitally programmable gain and 0.7‐Hz to 2‐kHz true constant bandwidth that is independent on gain with a 25‐pF load capacitor. In addition, simulations of the same circuit in 0.13‐μm CMOS technology show that the proposed scheme allows operation with ±0.08‐V supplies, 7.5‐Hz to 8‐kHz true constant bandwidth with a 25‐pF load capacitor, and a total power dissipation of 0.07 μW.     

Accurate design‐oriented simulation‐driven modeling of miniaturized microwave structures

One of the important prerequisites for efficient design optimization of microwave structures is availability of fast yet reliable replacement models (surrogates) so that multiple evaluations of the structure at hand can be executed in reasonable timeframe. Direct utilization of full‐wave electromagnetic (EM) simulations for handling optimization‐related tasks is often prohibitive. A popular approach to construction of fast surrogates is data‐driven modeling. Unfortunately, it normally requires a large number of training samples, and it is virtually infeasible for structures that exhibit highly nonlinear responses (e.g. filters or couplers). In this work, a design‐oriented modeling technique is proposed where good accuracy is achieved by careful non‐uniform design space sampling that accounts for nonlinear relationship between the operating frequency of the structure and its geometry parameters, as well as carrying out the modeling process only for selected characteristic points of the structure responses (those that determine satisfaction/violation of given design specifications). Our approach is demonstrated using a miniaturized microstrip rat‐race coupler modeled in a wide range of geometry parameters and compared to conventional data‐driven modeling using kriging interpolation. Design optimization examples are also provided. Copyright © 2016 John Wiley & Sons, Ltd.     

Stability analysis of wideband linear bipolar varactor‐controlled oscillator with two‐coupled resonant circuits

Theoretical analysis of the stability conditions of the steady‐state operation modes and tuning bandwidth characteristics of bipolar self‐biased varactor‐controlled oscillator (VCO) with two‐coupled resonant circuits are presented. The recommendations at the choice of the circuit and varactor parameters for a linearization of the wideband tuning frequency characteristics under free‐running stable oscillation conditions are given. Highly linear octave‐band tuning operation was found to be possible using hyper‐abrupt varactors in two‐coupled resonant circuits VCO. Numerical and experimental results verify the validity of the design approach described. Copyright © 1999 John Wiley & Sons, Ltd.     

Realistic model for the multiple‐input floating‐gate transistor

Multiple‐input floating‐gate transistor (FGMOS) circuit designers face a serious problem along the design process: the lack of a realistic simulation model. For this reason, a solution that properly predicts the initial voltage at the floating gates is presented in this paper. In order to assess the performance of the proposal, a comparison is made against a test circuit fabricated in a 0.5‐µm On‐Semiconductor CMOS process. Based on this comparison, the proposed model is shown to be a fundamental tool in the design of FGMOS circuits. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Noise‐tolerant dynamic CMOS circuits design by using true single‐phase clock latching technique

In this paper, a true‐single‐phase clock latching based noise‐tolerant (TSPCL‐NT) design for dynamic CMOS circuits is proposed. A TSPCL‐NT dynamic circuit can isolate and filter noise before the noise enters into the dynamic circuit. Therefore, it cannot only greatly enhance the noise tolerance of dynamic circuits but also release the signal contention between the feedback keeper and the pull‐down network effectively. As a result, noise tolerance of dynamic circuits can be improved with lower sacrifice in power consumption and operating speed. In the 16‐bit TSPCL‐NT Manchester adder, the average noise threshold energy can be enhanced by 3.41 times. In the meanwhile, the power‐delay product can be improved by 5.92% as compared with the state‐of‐the art 16‐bit XOR‐NT Manchester adder design under TSMC 90 nm CMOS process. Copyright © 2014 John Wiley & Sons, Ltd.