2.5 Gb／s 16：1 MUX IC Design with CMOS

A low--power and high--speed 16.-1 MUX IC designed for optical fiber communication based on TSMC 0.25μm CMOS technology is presented. A tree—type architecture was utilized. The output data bit rate is 2.5 Gb/s at input clock rate of 1.25 GHz. The simulation results show that the output signal has peak—to—peak amplitude of 400 mV, the power dissipation is less than 200 mW and the power dissipation of core circuit is less than 20 mW at the 2.5 Gb/s standard bit rate and supply voltage of 2.5 V. The chip area is 1.8mm^2.     

一种应用于串行链路的5Gb/s低功耗电流模预加重发送器

A multi-standard compatible transmitter with pre-emphasis for high speed serial links is presented. Based on the comparison between voltage mode(VM) and current mode(CM) output driver architectures,a low power CM output driver with reverse scaling and bias current filtering technique is proposed.A 2-tap pre-emphasis filter is used to reduce the intersymbol interference caused by the low-pass channel,and a high speed,low power combined serializer is implemented to convert 10 bit parallel data into a serial data stream.The whole transmitter is fabricated in 65 nm 1.2 V/2.5 V CMOS technology.It provides an eye height greater than 800 mV for data rates of both 2.5 Gb/s and 5 Gb/s.The output root mean square jitter of the transmitter at 5 Gb/s is only 9.94 ps without pre-emphasis.The transmitter consumes 41.2 mA at 5 Gb/s and occupies only 240×140μm~2.     

A speaker driver for a single phase supply class G & I

A speaker driver applied to class G/classⅠwith a single phase power supply is presented.Gain expanding and compressing technology are employed in the signal processing circuit to optimize power dissipation.The circuit is implemented in 0.18μm N-well CMOS.Experimental results show that the speaker driver has a good audio sound quality and power efficiency.Less than 0.006%THD at a low power range and less than 0.4%at a medium power range can be obtained with a 1 kHz sine wave signal.Maximum output power of 360 mW can be gained at a load of 8Ω.The power efficiency is about twice that of a traditional class AB driver at the power range of 80 mW and shows more than 18%improvement at the higher output power range.     

A High Efficiency Fully Integrated OOK Transmitter for WBAN

A 2.4 GHz high efficiency radio frequency(RF) transmitter for wireless body area network(WBAN) in medical applications is presented in this paper. The transmitter architecture with high energy efficiency is proposed to achieve a high data rate with low power consumption. In conventional transmitters,the oscillator and power amplifier are turned off when the transmitter sends 0. The required time for turning oscillator ON/OFF is longer than the other blocks of the transmitter. In the proposed transmitter, the low power oscillator is on all the time while the power amplifier and modulator are turned off when "0" data is sent. The transmitter consumes 3.2 mW at 0.5 dBm output by 285 Mbps data rate and the energy consumption per transmitted bit with 0.5 dBm output power is 10pJ/(bitmW). The proposed transmitter was designed in0.18 μm CMOS technology.     

A dual mode charge pump with adaptive output used in a class G audio power amplifier

A dual mode charge pump to produce an adaptive power supply for a class G audio power amplifier is presented.According to the amplitude of the input signals,the charge pump has two level output voltage rails available to save power.It operates both in current mode at high output load and in pulse frequency modulation (PFM) at light load to reduce the power dissipation.Also,dynamic adjustment of the power stage transistor size based on load current at the PFM mode is introduced to reduce the output voltage ripple and prevent the switching frequency from audio range.The prototype is implemented in 0.18μm 3.3 V CMOS technology.Experimental results show that the maximum power efficiency of the charge pump is 79.5%@ 0.5x mode and 83.6%@ lx mode.The output voltage ripple is less than 15 mV while providing 120 mA of the load current at PFM control and less than 18 mV while providing 300 mA of the load current at current mode control.An analytical model for ripple voltage and efficiency calculation of the proposed PFM control demonstrates reasonable agreement with measured results.     

An ultraviolet laser communication system using frequency-shift keying modulation scheme

A communication system based on an ultraviolet(UV) laser at 266 nm is presented to improve the communication distance. The pulse frequency-shift keying(FSK) modulation scheme is studied and improved in order to reduce the bit error rate(BER), and is put into practice on a field programmable gate array(FPGA). The mathematical models of the modulation and demodulation are established. A test platform is set up to measure the energy density and pulse response under different distances and receiver elevation angles. It is shown that the omnibearing communication can be realized, and the bit rate is limited to 12.5 Mbit/s. The BER is estimated to be less than 10-7 at distance of 300 m in line-of-sight(LOS) communication model and to be less than 10-6 at distance of 80 m in non-line-of-sight(NLOS) communication model.     

Wavelength injection locking actively Q-switched random fiber laser based on random phase-shifted fiber Bragg grating and electro-optic modulator

In this paper, an actively Q-switched wavelength injection locking random fiber laser (RFL) based on random phase-shifted fiber Bragg grating (RPS-FBG) is proposed, and the performance of the laser is verified by experiments. Within the reflection bandwidth range of RPS-FBG, spanning from 1 549.2 nm to 1 549.9 nm, different laser modes with stable central wavelength and peak power can be selectively chosen by varying the injected light wavelength. The power fluctuation within 1 h is less than 0.1 dBm, and the central wavelength drift is less than 0.02 nm. When the pump power increases from 90 mW to 300 mW, the pulse width decreases from 3.2 μs to 1.5 μs, and the pulse repetition frequency is 20 kHz. The RFL can reach a stable locking state at the lowest pump power of 100 mW and the lowest injection power of 3 dBm. When the wavelength is locked, the output pulse is a single pulse. On the contrary, the unlocked output pulse is multi-pulse. The laser has the characteristics of high wavelength tunability in the reflection range of RPS-FBG and it can be an ideal light source in the fields of laser imaging and pulse coding.     

A Clock Generator for High-Speed High-Resolution Pipelined A/D Converter Zhao Lei(赵磊) , Yang Yintang(杨银堂), Zhu Zhangming(朱樟明), Liu Lianxi(刘帘羲)

A clock generator circuit for a high-speed high-resolution pipelined A/D converter is presented.The circuit is realized by a delay locked loop(DLL),and a new differential structure is used to improve the precision of the charge pump.Meanwhile,a dynamic logic phase detector and a three transistor NAND logic circuit are proposed to reduce the output jitter by improving the steepness of the clock transition.The proposed circuit,designed by SM1C 0.18μm 3.3 V CMOS technology,is used as a clock generator for a 14 bit 100 MS/s pipelined ADC.The simulation results have shown that the duty cycle ranged from 10%to 90%and can be adjusted.The average duty cycle error is less than 1%.The lock-time is only 13 clock cycles.The active area is 0.05 mm2 and power consumption is less than 15 mW.     

A 20-Gb/s 1 ： 2 demultiplexer in 0.18-μm CMOS

A 1 ： 2 demultiplexer （DEMUX） has been designed and fabricated in SMIC＇s standard 0.18-μm CMOS technology, based on standard CML logic and current-density-centric design philosophy. For the integrity of the DEMUX and the reliability of the internal operations, a data input buffer and a static latch were adopted. At the same time, the static latch enables the IC to work in a broader data rate range than the dynamic latch. Measurement results show that under a 1.8-V supply voltage, the DEMUX can operate reliably at any data rate in the range of 5-20 Gb/s. The chip size is 875×640μm^2 and the power consumption is 144 mW, in which the core circuit has a share of less than 28%.     

一种用于单相电源G类和I类音频功放的扬声器驱动电路

A speaker driver applied to class G/classⅠwith a single phase power supply is presented.Gain expanding and compressing technology are employed in the signal processing circuit to optimize power dissipation.The circuit is implemented in 0.18μm N-well CMOS.Experimental results show that the speaker driver has a good audio sound quality and power efficiency.Less than 0.006%THD at a low power range and less than 0.4%at a medium power range can be obtained with a 1 kHz sine wave signal.Maximum output power of...     

A NEW GRID-CONTROLLED PULSE TWT WITH DEPRESSED COLLECTOR

A grid-controlled pulse TWT with depressed collector and PPM focusing system is reported inthis paper.It operates at X-band and delivers peak output power of 1 kW with saturation gain of47 dB.The duty cycle is 3%.The electron beam transmission is 95% with RF output at saturatedcondition.The efficiency is not less than 30%(excluding the heater power).     

2.5Gb/s Monolithic IC of Clock Recovery,Data Decision，and 1∶4 Demultiplexer

A high integrated monolithic IC，with functions of clock recovery,data decision,and 1∶4 demultiplexer，is implemented in 0.25μm CMOS process for 2.5Gb/s fiberoptic communications.The recovered and frequency divided 625MHz clock has a phase noise of －106.26dBc/Hz at 100kHz offset in response to a 2.5Gb/s PRBS input data (2~31-1).The 2.5Gb/s PRBS data are demultiplexed to four 625Mb/s data.The 0.97mm×0.97mm IC consumes 550mW under a single 3.3V power supply (not including output buffers).     

基于90nm CMOS工艺的一种10位低功耗SAR A/D转换器

Traditional and some recently reported low power,high speed and high resolution approaches for SAR A/D converters are discussed.Based on SMIC 65 nm CMOS technology,two typical low power methods reported in previous works are validated by circuit design and simulation.Design challenges and considerations for high speed SAR A/D converters are presented.Moreover,an R–C combination based method is also addressed and a 10-bit SAR A/D converter with this approach is implemented in SMIC 90 nm CMOS process.The DNL and INL are measured to be less than 0.31 LSB and 0.59 LSB respectively.With an input frequency of 420 kHz at 1 MS/s sampling rate, the SFDR and ENOB are measured to be 67.6 dB and 9.46 bits respectively,and the power dissipation is measured to be just 3.17 mW.     

Design of a transversal equalizer for electronic dispersion compensation in optical communication links

A programmable transversal equalizer for electronic dispersion compensation(EDC) in optical fiber communication systems is developed.Based on the SiGe technology with a cut-off frequency of 80 GHz,the equalizer consists of 6 seriesparallel amplifiers as delay units and 7 Gilbert variable gain amplifiers as taps,which ensure that the equalizer can work at the bit rate of 10 Gb/s.With different tap gains,the forward voltage gain of the transversal equalizer varies,which demonstrates that the equalizer has various filtering characteristics such as low pass filtering,band pass filtering,band reject filtering,and notch filtering,so it can effectively simulate the inverse transfer function of dispersive channels in optical communications,and can be used for compensating the inter-symbol interference and other nonlinear problems caused by dispersion.The equalizer(including pads) occupies an area of 0.40 mm × 1.08 mm,and its total power dissipation is 400 mW with 3.3 V power supply.     

A 4 GS/s 4 bit ADC with 3.8 GHz analog bandwidth in GaAs HBT technology

An ultra-wideband 4 GS/s 4 bit analog-to-digital converter(ADC)which is fabricated in 2-level interconnect, 1.4μm InGaP/GaAs HBT technology is presented.The ADC has a-3 dB analog bandwidth of 3.8 GHz and an effective resolution bandwidth(ERBW)of 2.6 GHz.The ADC adopts folding-interpolating architecture to minimize its size and complexity.A novel bit synchronization circuit is used in the coarse quantizer to eliminate the glitch codes of the ADC.The measurement results show that the chip achieves larger than 3.4 ENOBs with an input frequency band of DC-2.6 GHz and larger than 3.0 ENOBs within DC-4GHz at 4 GS/s.It has 3.49 ENOBs when increasing input power by 4 dB at 6.001 GHz of input.That indicates that the ADC has the ability of sampling signals from 1st to 3rd Nyquist zones(DC-6 GHz).The measured DNL and INL are both less than±0.15 LSB. The ADC consumes power of 1.98 W and occupies a total area of 1.45×1.45 mm~2.     

一种带有混合平均式分布采样电路的低功耗CMOS全折叠型模数转换器

This paper describes an 8-bit 125 MHz low-power CMOS fully-folding analog-to-digital converter （ADC） A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchronization block to reduce the number of comparators for low power. This ADC is implemented in 0.5μm CMOS technology and occupies a die area of 2 × 1.5 mm^2. The measured differential nonlinearity and integral nonlinearity are 0.6 LSB/-0.8 LSB and 0.9 LSB/-1.2 LSB, respectively. The ADC exhibits 44.3 dB of signal-to-noise plus distortion ratio and 53.5 dB of spurious-free dynamic range for 1 MHz input sine-wave. The power dissipation is 138 mW at a sampling rate of 125 MHz at a 5 V supply.     

A novel auto-bias control scheme for stabilizing lithium niobate Mach-Zehnder modulator at any operating point

In this paper,we propose and experimentally demonstrate an auto-bias control scheme for stabilizing a lithium niobate（LN）Mach-Zehnder modulator（MZM）at any operating point along the power transmission curve.It is based on that the bias drift would change the operating point and result in varying the output optical average power of the Mach-Zehnder modulator and its first and second derivatives.The ratio of the first to the second derivative of the output optical average power is used in the proposed scheme as the key parameter.The experimental results show that the output optical average power of the LN MZM hardly changes at the desired operating point,and the maximum deviation of output optical average power is less than±4%.     

Sensitivity analysis of an HgCdTe based photovoltaic receiver for long-wavelength free space optical communication systems

We examine theoretically the performance of an Hg0.77Cd0.23Te based p-n photodetector/HFET optical receiver due to its possible application at 10.6 μm free space optical communication system at high bit rate.A rigorous noise model of the receiver has been developed for this purpose.We calculate the total noise and sensitivity of the receiver.The front-end of the receiver exhibits a sensitivity of -45 dBm at a bit rate of 1 Gb/s and -30 dBm at a bit rate of 10 Gb/s,and the total mean-square noise curren t〈i2...     

A High Power 320-356GHz Frequency Multipliers with Schottky Diodes

A 320-356GHz fixed-tuned frequency doubler is realized with discrete Schottky diodes mounted on 50μm thick quartz substrate.Influence of circuit channel width and thermal dissipation of the diode junctions are discussed for high multiplying effficiency.The doubler circuit is flip-chip mounted on gold electroplated oxygenfree copper film for grounding of RF and DC signals,and better thermal transportation.The whole multiplying circuit is optimized and established in Computer simulation technology (CST) suite.The highest measured multiplying efficiency is 8.0％ and its output power is 5.4mW at 328GHz.The measured typical output power is 4.0mW in 320-356GHz.     

A 12 bit 100 MS/s pipelined analog to digital converter without calibration

A 1.8 V 12 bit 100 MS/s pipelined analog to digital converter(ADC) in a 0.18μm complementary metal-oxide semiconductor process is presented.The first stage adopts a 3.5 bit structure to relax the capacitor matching requirements.A bootstrapped switch and a scaling down technique are used to improve the ADC's linearity and save power dissipation,respectively.With a 15.5 MHz input signal,the ADC achieves 79.8 dB spurious-free dynamic range and 10.5 bit effective number of bits at 100 MS/s.The power consumpt...