A silicon flexode an adaptive p−n junction device

The lithium flexode, a p−n junction device whose I–V characteristic is reversibly adjustable and which heretofore has been made only with germanium, has now been made with silicon. The silicon flexode was batch fabricated by doping a silicon wafer with lithium to about 8 × 10¹⁷ atoms/cm³ and then forming a shallow p−n alloy junction using aluminum.

Experimentally, the silicon flexode was evaluated primarily as a bistable switch operating between a rectifying or diode-state (D) and a conducting-state (C)). Electrical signals only (with their attendant Joulean heating) were used to obtain I–V adjustment. The largest change in back resistance obtained in the silicon flexode was about five orders of magnitude. Switching from the D- to C-states ordinarily took about 1 sec. However, the inverse C to D switching process required the input of substantial power (about 1 W) and usually took several minutes, although a switching time as low as 20 sec was measured. In addition, it was found that the silicon flexode can be switched in either direction to intermediate states which remain stable at room-temperature.

Lithium precipitation, after cooling from the diffusion temperature, was not observed in our experiments with both quartz-crucible and floating-zone silicon. This is at variance with previously published findings. The difference is probably related to an effect, perhaps lattice strain, introduced by our diffusion technique.     

Simulation and analysis of amorphous silicon image sensor having a p−i−n structure

The current-voltage characteristics of a p−i−n a-Si : H contact image sensor under dark and illuminated conditions have been simulated by solving the Poisson's equation and the continuity equations, and the results are correlated with the experiments. The dependence of the dark and photo-currents on the parameters such as the density of states in the gap, intrinsic layer width, dopant concentrations of p⁺ layer and n⁺ layer are discussed.     

Alteration of diffusion profiles in semiconductors due to p−n junctions

Concentration profiles of diffusing species in semiconductors are calculated including the effects of the electric fields at p− junctions. The junction electric field can significantly alter diffusion behavior near the junction at the growth temperature, and thus affect dopant uniformity and junction placement for some commonly occurring epitaxial growth conditions. The junction electric field affects diffusion in the same manner as the internal electric field that results from a dopant concentration gradient. The field can produce diffusion profiles with either enhanced or retarded diffusion rates at the junction and pile-up or depletion of the diffusing species near the junction. Several experimental examples for diffusion of Mg across a p−n junction in (Al,Ga)As during growth by liquid phase epitaxy are presented.     

The effect of spatially varying diffusion constant on the transient decay of short circuit current in electron irradiated p−n junctions

A Gaussian doped p−n junction has an E field in the diffused layer which increases linearly from the surface toward the junction. It will also have a diffusion constant which varies with doping density and thus with position in the diffused layer.

In this paper these two effects are taken into account in calculating the transient decay of short-circuit current when such a p−n junction is irradient by an electron beam. The Rayleigh-Ritz method is used to approximate the eigenvalues which determine the decay time constants. The limiting cases of zero and infinite surface recombination velocities are treated.

It is found that for typical doping the decay time is about a factor of 2 longer than would be expected if the diffusion constant were taken to be spatially invariant and to have a value equal to its spatial average value taken over the diffused layer.     

Schottky-barrier diodes of MBE-deposited antimony on n and p gallium arsenide

Sb---GaAs Schottky barrier diodes on n and p clean substrates have been prepared by in-situ metal deposition in a molecular beam epitaxy (MBE) system. The barrier heights for n and p specimens prepared on Ga-rich surfaces sum to the bandgap of the GaAs. Barriers prepared on As-rich surfaces are slightly lower and seem to sum to about 0.1 eV less than the bandgap. Reduction of the effective barrier heights on substrates with higher doping concentrations are in agreement with the theoretical predictions of Padovani and Stratton. Thermal annealings up to 250°C show changes in barrier heights that depend on whether the original surface was As- or Ga-rich.     

Current bistability in InGaAs quantum wire p-i-n heterostructures

We report a clear evidence of bistability in the current-voltage (I-V) characteristics of p-i-n heterostructures containing InGaAs V-shaped quantum wires. The observed phenomenon is explained in the framework of a single carrier transport model in which the quantum wires act like traps for the vertical current. The charge trapping phenomenon is indeed demonstrated by capacitance-voltage (C-V) and photocurrent experiments.     

Low temperature impurity diffusion in SiC: Planar quantum-size p-n junctions and n-p-n transistor structures

Low temperature diffusion of boron and phosphorus has been realized for the first time in monocrystalline SiC through controlled surface injection of silicon vacancies. By varying the parameters of the surface oxide overlayer during the boron/phosphorus diffusion process, it was possible to obtain the SiC planar quantum-size p-n junctions and transistor structures featuring low values for dark leakage currents. Use of the SiC quantum-size transistor structures in both bipolar and FET variations has been found to result in the generation of the negative resistance due to avalanche current processes.     

Electrical characteristics of B-implanted p-channelMNOS transistors

Boron ions (¹¹B⁺ of 3·7 to 7·4 × 10¹¹/cm² were implanted at 60–120 keV into the channel region of p-channel MNOS double layer insulated gate field effect transistors through 920–940 Å of SiO₂ and various thicknesses (300–1800 Å) of Si₃N₄ deposited on SiO₂. Subsequent annealing was performed in a nitrogen atmosphere at 1000°C for 30 min. Acceleration energy, implant dose and Si₃N₄ thickness dependences of the shift of the threshold voltage showed good agreement with the calculated results based on Ishiwara and Furukawa's theory for distribution of implanted atoms in the double layered substrate, using the projected ranges and standard deviations larger than LSS predictions by the factor of 1·2 for SiO₂ and 1·3 for Si₃N₄, respectively. The results on the gain terms and the breakdown voltages were qualitatively the same as those of ¹¹B⁺-implanted p-channel MOS transistors.     

n-Channel AlSb/GaSb modulation-doped field-effect transistors

We report the first fabrication of a GaSb n-channel modulation-doped field-effect transistor (MODFET) grown by molecular beam epitaxy. The modulation-doped structure exhibits a room temperature Hall mobility of 3140 cm² V⁻¹ s⁻¹ and 77 K value of 16000 cm² V⁻¹ s⁻¹, with corresponding sheet carrier densities of 1.3 × 10¹² cm⁻² and 1.2 × 10¹² cm⁻². Devices with 1 μm gate length yield transconductances of 180 mS mm⁻¹ and output of 5 mS mm⁻¹ at 85 K. The device characteristics indicate that electron transport in the channel occurs primarily via the L-valley of GaSb above 85 K. The effective electron saturation velocity is estimated to be 0.9 × 10⁷ cm s⁻¹. Calculations show that a complementary circuit consisting of GaSb n- and p-channel MODFETs can provide at least two times improvement in performance over AlGaAs/GaAs complementary circuits.     

From Long Infrared to Very Long Infrared Wavelength Focal Plane Arrays Made with HgCdTe n + n ?/ p Ion Implantation Technology

This paper aims at studying the feasibility of very long infrared wavelength (VLWIR) (12–18 μm) focal plane arrays using n-on-p planar ion-implanted technology. To explore and analyze the feasibility of such VLWIR detectors, a set of four Cd _x Hg_1−x Te LPE layers with an 18 μ cutoff at 50 K has been processed at Defir (LETI/LIR–Sofradir joint laboratory), using both our “standard” n-on-p process and our improved low dark current process. Several 320 × 256 arrays, 30-μm pitch, have been hybridized on standard Sofradir readout circuits and tested. Small dimension test arrays characterization is also presented. Measured photonic currents with a 20°C black body suggest an internal quantum efficiency above 50%. Typical I(V) curves and thermal evolution of the saturation current are discussed, showing that standard photodiodes remain diffusion limited at low biases for temperatures down to 30 K. Moreover, the dark current gain brought by the improved process is clearly visible for temperatures higher than 40 K. Noise measurements are also discussed showing that a very large majority of detectors appeared background limited under usual illumination and biases. In our opinion, such results demonstrate the feasibility of high-performance complex focal plane arrays in the VLWIR range at medium term.     

p-n heterojunctions

A classical kinetic emission model coupled with an assumed energy band diagram which includes the effects of a discontinuity in the electron affinity, effective mass, permittivity and the energy gap at the junction interface is used as the basis for an analysis of the static current-voltage characteristic of the abrupt p-n heterojunction. The derived characteristic is then used to determine regions of quasi-equilibrium within the depletion layer and to predict the position dependence of the quasi-Femri levels.

Two distinct modes of operation are predicted for the heterojunctions I–V characteristic: Metal-semiconductor type operation where the current is limited by the ability of the carriers to surmount the potential barrier at the junction interface and homojunction type operation where the current is limited by the ability of the carriers to diffuse away from the junction depletion region. The predicted extrapolated saturation current for the former type of operation, is in general, significantly less than that for the latter. The position dependence of the quasi-Fermi levels is also different for the two types of operation. For metal-semiconductor type operation a drop in the quasi-Fermi level across the depletion layer is expected, whereas for homodiode type operation there is a negligible variation of the quasi-Fermi level in this region.

The heterojunction I–V characteristic presented here, which differs significantly from previous models, agrees favourably with experimental data on Ge-GaAs heterojunctions reported in the literature and with others recently fabricated by the present authors.     

An accurate mobility model for the I–V characteristics of n-channel enhancement-mode MOSFETs with single-channel boron implantation

In this paper we develop an analytical mobility model for the I–V characteristics of n-channel enhancement-mode MOSFETs, in which the effects of the two-dimensional electric fields in the surface inversion channel and the parasitic resistances due to contact and interconnection are included. Most importantly, the developed mobility model easily takes the device structure and process into consideration. In order to demonstrate the capabilities of the developed model, the structure- and process-oriented parameters in the present mobility model are calculated explicitly for an n-channel enhancement-mode MOSFET with single-channel boron implantation. Moreover, n-channel MOSFETs with different channel lengths fabricated in a production line by using a set of test keys have been characterized and the measured mobilities have been compared to the model. Excellent agreement has been obtained for all ranges of the fabricated channel lengths, which strongly support the accuracy of the model.     

Predicting the process induced warpage of electronic packages using the P–V–T–C equation and the Taguchi method

A critical issue in the manufacturing of electronic packages is the warpage induced during the molding process as a result of differences in the shrinkage of the constituent materials. Package warpage causes serious problems such as the quality degradation of devices and yield loss in manufacturing processes. Loss of lead coplanarity happens due to package warpage and causes difficulty in device testing and surface mount assembly. Internal stresses associated with package warpage can also cause device failures such as die cracking, broken circuits and package cracking.Warpage in IC package has drawn intensive attention in the past. Although the effects of thermal shrinkage were extensively investigated in the literatures, the influence of the cure shrinkage on package warpage had received less attention. Accordingly, this study develops a numerical approach for generating more accurate predictions of the package warpage by taking the effects of both thermal shrinkage and cure shrinkage into account. A three-dimensional finite element model of the small outline package (TSOP) DBS-27P is constructed and the proposed numerical approach, which is based on the P–V–T–C (pressure–volume–temperature–conversion) equation and the CTEs (coefficients of thermal expansion) of the package materials, is employed to predict the warpage at each of its corners under various packaging processing conditions. Using the Taguchi method, the relative influences of the transfer pressure, the packing pressure, the mold temperature and the curing time on the degree of package warpage are identified and the optimal processing conditions are established. A series of experimental packaging trials are performed using the optimal processing conditions. It is found that the warpage of the actual package is in good agreement with that predicted numerically. Therefore, the accuracy of the proposed numerical approach is confirmed. Moreover, the results also demonstrate the capability of the Taguchi method to identify the optimal packaging processing parameters on the basis of a limited number of simulation runs.     

Study of LWIR and VLWIR Focal Plane Array Developments: Comparison Between p-on-n and Different n-on-p Technologies on LPE HgCdTe

The very long infrared wavelength (>14 μm) is a very challenging range for the design of mercury cadmium telluride (HgCdTe) large focal plane arrays (FPAs). The need (mainly expressed by the space industry) for very long wave FPAs appears very difficult to fulfil. High homogeneity, low defect rate, high quantum efficiency, low dark current, and low excess noise are required. Indeed, for such wavelength, the corresponding HgCdTe gap becomes smaller than 100 meV and each step from the metallurgy to the technology becomes critical. This paper aims at presenting a status of long and very long wave FPAs developments at DEFIR (LETI-LIR/Sofradir joint venture). This study will focus on results obtained in our laboratory for three different ion implanted technologies: n-on-p mercury vacancies doped technology, n-on-p extrinsic doped technology, and p-on-n arsenic on indium technology. Special focus is given to 15 μm cutoff n/p FPA fabricated in our laboratory demonstrating high uniformity, diffusion and shot noise limited photodiodes at 50 K.     

Implant dose monitoring by MOS C–V measurement

The most critical parameter for deep sub-micron MOS field effect transistors is the threshold voltage, which is highly dependent on processing specifically, the ion implanted channel dose. Monitoring the channel doping on product wafers is highly desirable and is a major issue for process engineers. MOS C–V methods are widely used for process ramp up and monitoring and MOS C–V doping profiling is an introduced method for monitoring of low dose implants. However, the failure of the depletion approximation in the near surface region implies that conventional MOS C–V measurements yield erroneous doping profiles in that region. Integrating MOS C–V doping profiles yields only a partial implant dose excluding the important near surface dose portion. Here, we report a new approach, which enables the determination of the entire implant dose, taking into account the crucial surface region. Moreover, the MOS threshold voltage can be obtained self-consistently. The method is also applicable to MOS structures with ultra thin gate oxides.     

Current/voltage relations in punchthrough transistors

Observations of punchthrough in narrow-base (?0.1 ?m) n-p-n transistors are reported that do not conform to conventional theory. A general theory of punchthrough current/voltage relations is developed that explains the experimental results.     

Reliability comparison of an n cascade system with the addition of an n strength system

In the present paper we are comparing the reliability of two models: (i) the cascade system and (ii) the system having n strengths on a single stress. In both the cases the system has n strengths and a single stress. In the first case n strengths are cascaded and for each attack the stress is decreased. Whereas in the second case n strengths act in combination on the stress component. From the results obtained we can observe that when the attenuation factor is less than 0.5 the cascade model is more reliable, otherwise the second one is more reliable. Hence we infer that, at each attack, if the stress decreases the cascade model is more reliable.     

The maximal PN sequences over GF(p)

In this paper analysis of the maximal pseudorandom sequences (PN sequences) over a Galois Field GF(p) is given. The first part of the paper deals with the properties of the sequences of vectors generated over GF(p). In the second part the autocorrelation function of the pseudorandom sequences is discussed.