基于0.25μm CMOS工艺的1.8V Rail-to-Rail运算放大器

采用TSMC0．25μm CMOS工艺，设计实现了一种低功耗、高增益带有恒跨导输入级的Rail—to—Rail运算放大器。基于BSIM3V3 Spice模型，采用Hspice对整个电路进行仿真，在1．8V的单电源电压工作条件下，直流开环增益达到108．6dB，相位裕度为57．2度，单位增益带宽为5MHz，功耗为0．23mW。     

中兴通讯携4G LTE for Rail解决方案完美亮相2014亚洲轨交展

正日前,在泰国BITEC展馆举办的2014年第1届亚洲轨交展会上,中兴通讯携4G LTE for Rail解决方案完美亮相,以"sharing with you"为主题,不仅在展会现场演绎了别开生面的智慧交通盛宴,更给亚洲客户带来了全球领先的4G LTE for Rail解决方案商用经验。业内人士预计,作为具备4GLTE for Rail解决方案商用经验的全球唯一方案提供者,中兴通讯的轨道通信解决方案将助推亚太乃至全球实现交通4G跨越式发展和应用。     

低电压CMOS模拟集成运算放大器输入级的研究

对于低电压CMOS模拟集成运算放大器输入级所面临的问题,我们提出了三种解决的方法,其中包括输出为Rail—to—Rail的差分输入放大电路,差分输入的互导为恒定值的差分输入电路(假设KN=KP)和差分输入的互导为常数的差分输入电路(KN≠KP)。分别对三种方法进行了详细的分析和讨论,最后,提出了低电压CMOS模拟集成运算放大器输入级还需要解决的问题。     

一种电流跟踪补偿的输入输出全摆幅运算放大器

介绍了一种工作在2.5V电压下、具有全摆幅输入与输出功能的两级CMOS运算放大器。通过一种简单有效的电流跟踪电路实现了输入跨导恒定的要求，这样使得频率补偿变得容易实现；为了降低功耗，输入级工作在弱反型区：输出级采用带有前馈控制电路的AB类输出电路，实现了输出信号的轨至轨。电路具有结构简单、功耗低、面积小、性能高等优点。     

跨域BGP MPLS VPN技术应用研究

以不同城市的城域网BGP MPLS VPN为基础，通过在ABSR上为VPN配置VRF的Import／Export Target和BGP等，实现了VRF to VRF、MP—EBGP、Multi—hop MP—EBGP三种跨域的组网方式，分析了三种跨域组网方式的优缺点。     

TD—LTE系统Reed—Muller译码的仿真及FPGA实现

主要基于FPGA实现TD—LTE系统中的Reed—Muller译码,包括Reed—Muller译码的介绍、方案的构成、FPGA实现流程、以及实现结果分析。并在Virtex-6芯片上,进行了仿真、综合、板级验证。实现结果表明,该Reed—Muller译码算法应用到TD—LTE射频一致性测试仪表中具有良好的高效性和可靠性。     

一种宽带恒定跨导轨对轨运算放大器的设计

介绍了一种具有轨对轨输入功能的CMOS输入级电路。该电路克服了一般运算放大器只能工作在一定共模输入范围的输入级的缺陷，在各种共模输入电平下有着几乎恒定的跨导，使频率补偿更容易实现，且由于其工作原理与MOS晶体管的C—V解析关系无关，对制造工艺依赖性小，适用于深亚微米工艺。在此基础上，设计出了一种宽带的运算放大器，该运算放大器具有轨对轨输入、输出能力，可以作为常用模拟电路的基本单元模块。它没有严格的共模输入限制，跨导和整体性能稳定，适于为更大规模的数字／模拟混合信号系统提供行为级模型。     

恒电压增益的低电压Rail—to—Rail运算放大器

基于 Alcatel的 0 .3 5μm标准 CMOS工艺 (VT=0 .6 5 V) ,模拟实现了工作电压低达 1 .8V、电压增益偏差仅为 3 % (整个输入共模偏置电压范围内 )的运算放大器 ;电路的设计也避免了差分输入对中 PMOS管和 NMOS管的 W/L的严格匹配 ,增强了电路对工艺的坚固性。对输入差分对偏置电流的控制电路、差分输入对的有源负载和 AB类 Rail- to- Rail输出级进行了整体考虑 ,确保电压增益恒定的新型结构 ,使该运放在 2 V电源电压下 ,电压增益达到 80 d B(1 0 kΩ 电阻和 1 0p F电容并联负载 ) ,单位增益带宽为 1 2 MHz,相位裕量 72°     

高速Berlekamp-Massey算法结构及电路实现

介绍了两种用于二进制BCH解码器的高速Berlekamp—Massey算法实现方案。在加入寄存器以减少关键路径的延时从而提高电路速度的基础上，一种方法是采用有限域乘法器复用的方法降低电路的复杂度；另一种方法则通过对有限域乘法器进行流水线设计，进一步提高电路的工作速度，实现超高速应用。设计中充分利用了二进制BCH码中Berlekamp—Massey算法迭代计算时修正值间隔为零的性质，用超前计算的方法减少了运算周期的增加。提出的方案可用于设计高速光通信系统的信号编解码芯片。     

电信级MS-EPON传输性能的监测

MS—EPON为用户提供电信运营级服务质量的电路业务和以太网数据业务的多业务宽带接入．作为电信级传输接入系统,MS—EPON的传输性能在线监测是必不可少的．文章应用比特间插奇偶校验原理,提出了一种利用以太网帧前导码的一个字节作为BIP校验以实现对MS—EPON系统传输性能在线监测的方法,并对监测性能进行了分析,证明了方案的可行性。     

A Low-Voltage Fully Differential Constant-Gm Rail-to-Rail CMOS Operational Amplifier

A low-voltage fully differential CMOS operational amplifier withconstant-g_mand rail-to-rail input and output stages ispresented. It is the fully differential version of a previously realizedsingle-ended operational amplifier where a novel circuit to ensure constanttransconductance has been implemented [1]. The input stage is a rail-to-railstructure formed by two symmetrical OTAs in parallel (the input transistorsare operating in weak inversion). The class-AB output stages have also afull voltage swing. A rail-to-rail input common mode feedback structureallows the output voltage control. Measurements in a 0.7 µ standardCMOS process with threshold voltages of about 0.7 V have been done. Theminimum experimental supply voltage is about 1.1 V. The circuit provides a60 dB low frequency voltage gain and about 1.5 MHz unity gain frequency fora total power consumption of about 0.72 mW at a 1.5 V supply voltage.     

Robust Design of LV/LP Low-Distortion CMOS Rail-to-Rail Input Stages

Two robust CMOS rail-to-rail OpAmp input stages are presented for low voltage ( 3 V) applications. The robust input stages are implemented using two recently reported universal approaches to achieve constant transconductance. Transconductance control circuit is also introduced to compensate for K _p , K _n mismatch of PMOS and NMOS differential pairs in the input stage. The input stages are designed for operation in the strong inversion and have a rail-to-rail common mode input voltage range. Compared with an OpAmp with simple complementary input pairs, a two stage rail-to-rail OpAmp design example exhibits lower total harmonic distortion (THD) levels over the entire common mode input voltage range.currently on leave as a visiting scholar at OSU     

低功耗轨至轨CMOS运算放大器设计

设计了一个1.5 V低功耗轨至轨CMOS运算放大器。电路设计中为了使输入共模电压范围达到轨至轨性能,采用了NMOS管和PMOS管并联的互补差动对输入结构,并采用成比例的电流镜技术实现了输入级跨导的恒定。在中间增益级设计中,采用了适合在低压工作的低压宽摆幅共源共栅结构;在输出级设计时,为了提高效率,采用了简单的推挽共源级放大器作为输出级,使得输出电压摆幅基本上达到了轨至轨。当接100 pF电容负载和1 kΩ电阻负载时,运放的静态功耗只有290μW,直流开环增益约为76 dB,相位裕度约为69°,单位增益带宽约为1 MHz。     

An Ultra-Low-Voltage Ultra-Low-Power CMOS Miller OTA With Rail-to-Rail Input/Output Swing

An ultra-low-voltage ultra-low-power CMOS Miller operational transconductance amplifier (OTA) with rail-to-rail input/output swing is presented. The topology is based on combining bulk-driven differential pair and dc level shifters, with the transistors work in weak inversion. The improved Miller OTA has been successfully verified in a standard 0.35-mum CMOS process. Experimental results have confirmed that, at a minimum supply voltage of 600 mV, lower than the threshold voltage, the topology presents almost rail-to-rail input and output swings and consumes only 550 nW.     

Effective parameter extraction using multiple-objective function for VLSI circuits

In this paper an input stage and an output stage are presented for application in low-voltage CMOS operational amplifiers. The input stage operates in strong inversion and has a rail-to-rail common-mode input voltage range. The transconductance (g _m ) is insensitive to the common-mode input voltage. The class AB output stage has a rail-to-rail output range. A class AB control circuit prevents any transistors in the output stage from switching off. This improves the large-signal high-frequency behavior and the step response of the amplifier. A complete two-stage Op Amp employing the proposed input and output stages was realized in a semi-custom CMOS process with minimum channel lengths of 10µm and transistor threshold voltages of approximately 0.7 V. The measured minimum supply voltage is 2.5 V. The measured input voltage range exceeds the supply rails and the output voltage reaches both rails within 130 mV. The unity-gain bandwidth of the complete Op Amp is severely limited by the long channel lengths. Simulations show that a unity-gain bandwidth of 7 MHz is feasible if 2.5µm channel lengths are used.     

A -90-dB THD rail-to-rail input opamp using a new local charge pumpin CMOS

This paper describes the principle and design of a CMOS rail-to-rail input operational amplifier with THD performance of -90 dB which is suited for high-quality audio systems. A new output stage has been used featuring an output suing that extends to either supply rail and is capable of driving a low ohmic load (32 Ω). The opamp, which is realized in a 0.5-μm 3.3-V digital CMOS process, uses a standard two-stage Miller configuration. The rail-to-rail input functionality is achieved with a new area-efficient on-chip charge pump which provides the local supply voltage for the input differential pair. THD levels below -90 dB have not yet been shown with existing rail-to-rail techniques. This rail-to-rail input configuration also behaves independently of the common mode level with respect to transconductance and slewing characteristics     

A 1-V BiCMOS rail-to-rail amplifier with n-channel depletion modeinput stage

A BiCMOS rail-to-rail operational amplifier capable of operating from supply voltages as low as 1 V is presented. The folded cascode input stage uses an nMOS depletion mode differential pair to provide rail-to-rail common mode voltage range while typically requiring only 40 fA of input bias current. The bipolar transistor differential-to-single-ended conversion network employs a low-voltage base current cancellation technique which provides high input stage voltage gain from a l-V supply yet allows a 3-V/μs slew rate capability. The bipolar transistor output stage uses a low-voltage translinear loop which maintains a low impedance signal path to the output common emitter power devices. This circuit topology enables the amplifier to achieve a 4-MHz bandwidth with 60° of phase margin. The output voltage can swing to within 50 mV of each supply rail. An “on-demand” base current boost technique will be presented which can provide up to 50 mA of output drive capability from a 5-V supply, yet consumes only a few microamps when the output is in the quiescent state. A low voltage level shift technique will be described which uses an n-channel depletion mode source follower to provide isolation between the input and output stages     

A low power and low distortion rail-to-rail input/output amplifier using constant current technique

A rail-to-rail amplifier with constant transconductance,intended for audio processing,is presented.The constant transconductance is obtained by a constant current technique based on the input differential pairs operating in the weak inversion region.MOSFETs working in the weak inversion region have the advantages of low power and low distortion.The proposed rail-to-rail amplifier,fabricated in a standard 0.35μm CMOS process,occupies a core die area of 75×183μm~2.Measured results show that the maximum power consumption is 85.37μW with a supply voltage of 3.3 V and the total harmonic distortion level is 1.2%at 2 kHz.     

An adaptive biasing one-stage CMOS operational amplifier fordriving high capacitive loads

An adaptive biasing one-stage CMOS operational amplifier for driving high capacitive loads has been developed. The amplifier has been designed to drive liquid-crystal-displays (LCDs) in battery-supplied devices. Contradictory features like low power dissipation and high driving capability at low supply voltage are required. Complementary differential input stages provide rail-to-rail common-mode input range. With a special cross-coupled double-to-single-end conversion, a full supply output range is achieved. These improvements solve a functional problem of some existing adaptive biasing amplifiers. Simulation and measurements demonstrate good correlation and show the expected results, especially in the critical operating area