Design of a sensorless commutation IC for BLDC motors

This paper presents the design and realization of a sensorless commutation integrated circuit (IC) for brushless DC motors (BLDCMs) by using mixed-mode IC design methodology. The developed IC can generate accurate commutation signals for BLDCMs by using a modified back-EMF sensing scheme instead of using Hall-effect sensors. This IC can be also easily interfaced with a microcontroller or a digital signal processor (DSP) to complete the closed-loop control of a BLDCM. The developed sensorless commutation IC consists of an analog back-EMF processing circuit and a programmable digital commutation control circuit. Since the commutation control is very critical for BLDCM control, the proposed sensorless commutation IC provides a phase compensation circuit to compensate phase error due to low-pass filtering, noise, and nonideal effects of back-EMFs. By using mixed-mode IC design methodology, this IC solution requires less analog compensation circuits compared to other commercially available motor control ICs. Therefore, high maintainability and flexibility can be both achieved. The proposed sensorless commutation IC is integrated in a standard 0.35-/spl mu/m single-poly four-metal CMOS process, and the realization technique of this mixed-mode IC has been given. The proposed control scheme and developed realization techniques provide illustrative engineering procedures for the system-on-a-chip solution for advanced digital motor control. Simulation and experimental results have been carried out in verification of the proposed control scheme.     

A board-mounted power supply module using a new low powerdissipation-control IC

A board-mounted power supply module for telecommunications systems is presented. The module uses a newly developed control IC to achieve higher efficiency and better compactness. The IC mainly consists of CMOSFETs to reduce power dissipation. The output driver for the main switch has been improved by regulating the swing voltage and optimizing the output-MOSFET channel width. The newly designed internal regulator in the IC has an extra input from a third winding on the transformer and supplies regulated voltage using either input. The IC consumes one-fourth of the power supply of a conventional control IC. To minimize the size of the power supply module, the IC integrates and perfectly isolates a primary circuit, a secondary circuit, a start-up, and an alarm activator using dielectric isolation. Using the IC, a 3 W power supply module with 80% efficiency is developed     

关于国家设立“集成电路设计人才培养专项基金”开展“中国芯片工程”的建议

阐述了在世界和我国的微电子特别是集成电路设计与制造方面的情况和趋势。讨论了集成电路设计人才的工程训练问题。介绍了无生产线集成电路设计问题和工业先进国家对集成电路设计人员的教育成功经验,从而对设立国家专项基金支持集成电路设计人才培养和实际“中国芯片工程”的实现方面提出了具体建议。     

非接触式IC读卡器的设计

非接触式IC卡又称为射频卡,是IC卡领域的一项新兴技术,它是射频识别技术和IC卡技术相结合的产物。非接触式IC卡读写器是非接触式IC卡应用系统的关键设备之一,设计一款更为方便有效的读写器对于构建一个便捷实用的应用系统来说有着重要的意义。本文设计是基于MFRC522射频芯片和STC11F32XE单片机的非接触式IC卡读卡器,并用该读卡器实现了对射频IC卡的读写操作。实际操作表明,本文设计的读写器能够实现对射频卡的制卡、扣费及充值功能,成本低廉,便于携带,且容易操作。     

Interference cancellation scheme with simple structure and betterperformance

The authors propose a new interference cancellation (IC) scheme which has a hybrid structure of the successive IC scheme and the parallel IC scheme. Based on computer simulation results, it is observed that the proposed IC scheme outperforms these two IC schemes for CDMA systems     

A GaAs HBT 16×16 10-Gb/s/channel crosspoint switch

A 16×16 crosspoint switch IC has been designed and implemented in a 2-μm GaAs heterojunction bipolar transistor (HBT) technology. The IC is a strictly nonblocking switch with broadcast capability and asynchronous data paths. The IC has fully differential internal circuitry and is packaged in a custom high-speed assembly. Test results confirmed that the IC achieves a 10-Gb/s/channel (or 160-Gb/s aggregate) capacity, the highest reported to date for a 16×16 crosspoint switch IC     

MOS IC crosspoint switch for space division digital switching networks

An MOS IC crosspoint switch for space division digital switching network is described. A sense amplifier for compensation of signal attenuation through the MOS IC switch is also considered. Transmission of a 50-100 Mbit/s bit rate digital signal seems a reasonable design objective on the basis of analysis of a preliminarily fabricated MOS IC switch and the design characteristics of a bipolar IC sense amplifier. The MOS switch and the SA are monolithic integrated. Dynamic test of the subsystem, in which MOS IC switches and bipolar IC SA's are connected in cascaded stages, has indicated that they are capable of 100 Mbit/s return to zero digital signal transmission and 46-dB signal-to-noise ratio.     

异步集成电路设计的研究与进展

回顾了异步集成电路设计发展的历史,阐述了当前异步集成电路重新引起重视的原因,总结了异步集成电路的优势,并对异步集成电路设计方法进行了简要地概括,介绍了实用的异步集成电路芯片,最后分析了异步集成电路面临的挑战,并揭示了它今后的发展方向.     

国际金融危机下封装测试行业面临的挑战

受国际金融危机影响,2008年国内集成电路产业增长率大幅度滑坡,封装测试行业也同样面临巨大挑战。文章分析了2008年国内集成电路产业尤其是江苏省集成电路产业的发展现状,封测业仍保持增长,但也出现明显下滑。原因不仅有国际环境的影响,还与国内集成电路产业特点有关。文章进一步探讨了金融危机的特点和对国内半导体行业的影响,以及国家目前为应对危机出台的各项政策。在此基础上,文章预测2009年半导体业将继续下降,但中国的半导体产业会先于全球半导体产业恢复,并高于全球半导体产业的增长幅度。最后,文章从技术、人才和资金三方面提出了封装测试业应对危机的措施,强调走出这次产业低谷的关键还是要依靠政府的强有力政策措施,即快速拉动国内需求。     

Fault Detection of Linear Analog Integrated Circuit in Network

This paper presents a novel network decomposition method that can detect faults of linear analog integrated circuit (IC) in network. The nodal admittance matrix (NAM) of linear analog IC is a function of its internal component values, which can be used for fault detection. However, it is difficult to obtain the NAM of linear analog IC in network. We propose a network decomposition based method to calculate the NAM of the IC under test in network. The IC under test is fault free, if its NAM lies inside the tolerance limit. Otherwise, it is faulty. The effectiveness of the proposed method is validated through benchmark circuits.     

Reliability evaluation of ultra-thin CSP using new flip-chip bonding technology––double-sided CSP and single-sided CSP

A high-density packaging technology has been developed that uses new flip-chip bonding technology with a thin IC and a thin substrate. Numerical analysis with the finite element method as well experiments clearly showed that deflection of the IC and reliability were affected by the IC thickness. Consequently, reliability could be improved by reducing IC thickness. The dependency of the life in single-sided chip-size packages (CSPs) could be expressed using a normal stress value in thickness, which is computed by the IC thickness and substrate type and thickness. The dependency of the life in double-sided CSPs could be expressed using a shear stress value in the vertical cross section, which is computed in IC thickness and substrate type and thickness, respectively.Moreover, a double-sided flip-chip approach solved the problem of warpage. A high-capacity memory card of 512 MB was put to practical use by applying these results. This increased the Si density by four times over that of a conventional CSP.     

STS-768 multiplexer with full-rate output data retimer in InP HBT

A 16:1 STS-768 multiplexer IC has been designed and fabricated using the Vitesse Semiconductor VIP-1 process. This IC is part of a complete chip-set solution for a 40-Gb/s STS-768 optical communication transceiver module. The multiplexer IC features a full-rate clock multiplication unit and a data retimer in the output stage to reduce duty-cycle distortion and jitter in the output data eye. Because of its strict timing requirements, this approach needs fast logic gates with a very low gate delay. The Vitesse VIP-1 process, with 150-GHz f/sub t/ and 150-GHz f/sub max/ heterojunction bipolar transistor, is an obvious choice to implement this IC. The multiplexer IC typically dissipates 3.6 W from -3.6-V and -5.2-V power supplies. This paper discusses the design and development of a 40-Gb/s 16:1 multiplexer IC including current-mode logic gate circuit design, divide-by-two, 40-GHz clock tree, voltage-controlled oscillator, clock multiplication unit, and output driver. Layout design and package design are also discussed due to their significant roles in the IC performance.     

集成电路市场及经营模式的分析与探讨

在分析全球集成电路形势的基础上，对通信、消费类电子、化合物半导体IC、MCU、Flash memory等IC市场进行了探讨。论述了IDM和Fabless、Foundry三种经营模式的特点与前途，并对我国集成电路产业的前景及发展模式进行了展望。     

基于横电磁波小室的IC辐射发射测试方法研究

集成电路(IC)的发展呈现出小型化和集成化的趋势,使得IC电磁辐射越来越强,准确测试出IC电磁辐射对于集成电路电磁兼容设计有重要意义。横电磁波(TEM)小室法是目前最常用的IC辐射测试方法,它使用方形测试板,测试四个角度(0°, 90°, 270°, 360°)的IC辐射值,然而IC电磁辐射具有角度效应,仅用四个角度无法准确测试出IC最大电磁辐射水平。文中基于TEM小室全波仿真模型,使用单根微带线,验证了角度对于IC辐射的影响。设计了基于STM32芯片的圆形测试板和方形测试板,利用TEM小室测试了不同角度、不同模式下的STM32芯片电磁辐射,测量结果证实了不同模式下圆形测试板的测试结果都要大于方形测试板,最大偏差达到16 d Bm,因此圆形测试板更能准确测出芯片的最大电磁辐射水平。     

400 Mbit/s Optical Regenerator Integrated Circuits

This paper discusses 400 Mbit/s optical regenerator integrated circuits, focusing on their circuit architecture and performance, and describes their application to a 400 Mbit/s optical regenerator. The basic design concepts for high-speed regenerator IC's are discussed and a new integrated circuit architecture based on these design concepts is proposed. The proposed architecture of regenerator IC's is used to fabricate five IC chips (Reshaping IC, Retiming IC, Decision IC, LD driver IC, and dc-to-dc converter IC) using a high-speed bipolar process with transistors having a unity gain bandwidth of 5 GHz. The combination of these IC's can achieve submarine and terrestrial long-haul optical transmission at bit rates up to 450 Mbits/s. These IC's are applied to a 400 Mbit/s IC optical regenerator. Experimental results show that the IC optical regenerator has an optical dynamic range of more than 27 dB without any adjustment and received average optical power required to maintain a 10^-11error rate is less than -38 dBm. Experimental results fully satisfy the system requirements, and the feasibility of commercial application is demonstrated.     

GaAs超高速模拟开关集成电路

本文首次报导了GaAs超高速模拟开关集成电路的设计、制备及主要结果。已制备出开启时间最好水平为0.7ns的实用开关集成电路是目前速度最快的模拟开关集成电路。     

IC优化设计及其成品率预测

IC成品率是与电路性能和制造成本及制造效益紧密相关的一个重要因素,在进行IC优化设计时,可将成品率与制造效益作为协调各性能指标的优化目标.针对这一问题,本文完善了IC成品率效益协调优化设计模型,提出了一种实现该模型的IC优化设计和成品率预测方法,并利用OrCAD/PSpice中的统计分析和电路性能分析的功能和特点,建立了相应的算法.实例表明,该方法及其实现算法是有效的.     

5 V, 10 Gbit/s optical receiver module using Si-bipolar IC

A 10 Gbit/s optical receiver module using a Si-bipolar IC has been developed. For low power and low cost, a pure Si-bipolar IC is used in place of a GaAs IC, which is commonly used for over 10 Gbit/s. To widen the frequency bandwidth, multifeedback techniques and a two-stage buffer configuration are used in the preamplifier IC. In addition, a differential circuit configuration is used for stable operation at high frequency. The IC was fabricated using 0.25 μm Si-bipolar technology. The module exhibits sensitivity of <-16 dBm for 10 Gbit/s data with an input dynamic range >15 dB. Small power consumption of 410 mW is achieved with the single power-supply voltage of +5 V     

IC设计网上合作研究中心的网络结构及应用

文章阐述了国内第一个将IC设计与网络很好结合的实验基地：IC设计网上合作研究中心的建设及应用情况，中心从技术上实现了IC设计资源的共享和项目的协同开发。文中详细论述了中心总体及局部结构、软件系统和网站结构，多项目晶圆工程（MPW）合作以及LMS集成电路测试验证系统网上应用共享。文章总结了IC设计与网络结合从而促进自身发展的模型，并对以后的发展规划进行了展望。