一种高效率F类功率放大器芯片的设计

介绍了一种简单的具有谐波调谐功能的输出匹配网络,可实现2次谐波短路和3次谐波开路。利用该输出匹配网络,基于InGaP/GaAs HBT工艺,设计了一个工作于2 GHz的高效率F类功率放大器,并通过搭载基板实现小型化芯片的研制。芯片测试结果表明,该功率放大器的小信号增益为35 dB,1 dB压缩点为34 dBm,饱和输出功率为35.3 dBm,效率为57%,并具有较好的谐波抑制性能。     

应用于4G-LTE无线通信系统的F类高PAE射频功率放大器

为了有效实现高谐波抑制并提高功率附加效率,提出了一种适用于4G-LTE无线通信系统的高效F类功率放大器。该功率放大器使用了低电压p-HEMT晶体管和小型微带抑制单元,能够在低射频输入功率下产生n次谐波抑制和较高的功率附加效率（power added efficiency,PAE）。采用谐波平衡法对提出的功率放大器进行了仿真分析,并对其进行了实际制造。通过实际测量对仿真结果进行了验证。测量结果显示,提出功率放大器的工作频率为1.8 GHz,带宽为100 MHz,平均PAE为76.9％,且具有2V的极低漏极电压。射频输入功率范围分别为0-12 dBm时,最大输出功率和增益分别为23.4和17.5 dBm。     

高效率低谐波失真宽带功率放大器设计

基于连续型功率放大器理论,提出一种高效低谐波失真宽带功率放大器的设计方法,并采用GaN高电子迁移率晶体管(HEMT)器件设计了验证电路。结合连续型功率放大器理论和多谐波双向牵引技术,找到一簇最佳负载阻抗值,并运用切比雪夫低通滤波器形式的阻抗变换器设计宽带匹配网络。偏置电路采用双扇形开路微带线和滤波电路相结合的方法进行设计,以减小电路尺寸和扩展具有高输入阻抗偏置电路的带宽。实验结果表明,在1.7~2.7 GHz工作频带内,功率附加效率为50%~60%,输出功率大于4 W,增益为(14±0.9)dB,二次谐波失真小于-25 dBc,三次谐波失真小于-60 dBc。     

应用于S频段的宽带高谐波抑制的F类功率放大器的设计

采用InGaP/GaAs HBT工艺设计了一个适用于S频段的宽带F类功率放大器,管芯大小为3×3×0.82mm3。为了同时实现高谐波抑制和宽带,在宽带匹配电路中使用了谐波陷波器。在1.8~2.5 GHz范围内,该匹配网络的输入阻抗约为一个常电阻,二次谐波阻抗约为零而三次谐波阻抗接近无穷大,因此提高了功率放大器的效率。输入测试信号为连续波,测试结果表明该功率放大器在1dB压缩点下的输出功率约为34dBm,PAE约为57%,2到4次谐波分量功率均小于-53dBc。     

温度补偿高谐波抑制功率放大器的设计

针对无线通信应用系统,采用了一种具有温度补偿特性的偏置电路和一种带有谐波抑制功能的输出匹配网络,设计了一款高线性高谐波抑制的功率放大器。该功率放大器采用InGaP/GaAs HBT工艺,工作频率为1.84 GHz,供电电压为4.5 V,偏置电压为2.85 V。测试结果表明,常温下,功率放大器的增益为32 dB,饱和输出功率可达33 dBm,二次、三次谐波分量都小于-55 dBc,在输出功率为24.5 dBm时,邻道抑制比为-47 dBc,在-40～85℃温度变化范围内,功率放大器增益与邻道抑制比基本不变。     

UHF宽带线性功率放大器设计

针对电磁环境模拟器应用设计了一个全固态UHF波段多级宽带线性高功率放大器。驱动放大器工作在A类，末级放大器以三个AB类功放模块频域分段覆盖工作频段，通过控制PIN开关切换。末级输出接低通滤波器改善谐波。实测从400MHz～1250MHz，功放的1dB压缩点功率为25W（44dBm），二次谐波低于-40dBc，输出功率在38dBm时双音测试三阶交调（IM3）优于-44dBc。     

基于平衡结构的高效率E类功率放大器设计

针对E类功率放大器输入输出回波损耗较大的缺陷,提出采用平衡结构的E类功率放大器的设计方法.仿真结果显示,在输入为28 dBm时,功率附加效率(PAE)达到最大(85.2％),集电极效率η为88.3％,输出功率为42.4 dBm;在320～360 MHz频率范围内,S11小于-19 dB,S22小于-15 dB,输入驻波系数小于1.3,输出驻波系数小于1.4;在325～355 MHz范围内,PAE达到60％以上,具有较大的高效率带宽.输出匹配网络采用二次谐波抑制技术,谐波失真得到较好的抑制,二次谐波失真达到-92.4 dBc.     

L频段低谐波失真功率放大器的设计

针对L频段低谐波失真功率放大器的设计,进行线性与非线性电路分析仿真和电路的优化设计。从理论上分析了甲乙类功率放大器的谐波失真特性,通过采用具有抑制谐波特性的输出匹配电路以降低功放产生的谐波失真。测试得到电路的关键技术指标为:工作频率范围1 390~1 510MHz,增益35 dB,1 dB压缩点33 dBm,并获得了满意的谐波抑制指标,在1 480 MHz、输出功率33dBm时,二、三次谐波分别为-70 dBc和-63 dBc。结果表明在功放设计中,优化设计输出匹配电路可以有效抑制功放的谐波失真。     

900MHz 低噪声功率放大器的仿真设计

低噪声放大器的特点是噪声系数小而输出功率较小,功率放大器的特点是输出功率较大而噪声系数较大。为了实现噪声系数小而输出功率较大的放大器,本文结合低噪放和功率放大器的设计方法,设计了一种用于谐波雷达发射机的低噪声功率放大器,该放大器由两级放大器组成,前级主要实现低噪声功能,后级主要实现功率增益。通过优化仿真设计,该放大器达到了比较理想的结果,具有良好的线性度和二次谐波抑制能力。     

一种连续F类/逆F类模式转换功率放大器

传统的F类和逆F类功率放大器的带宽不宽,且对于功放输出信号的谐波控制比较严格。在连续类功放理论的基础上,设计了一款在工作带宽内连续F类和连续逆F类模式转换的功率放大器。设计的功放采用了Cree 公司的CGH40010F GaN HEMT 晶体管。通过调整功放管输出端的谐波控制网络,控制谐波阻抗在Smith 圆图中位置分布,从而在带宽内同时实现连续F类和连续逆F类的工作模式。制作了测试板,结果表明在2.4～4.2GHz的带宽内,增益在11dB 以上,漏极效率为55%～82%,输出功率在39.5～41.9dBm。采用了10MHz 的LTE 单载波信号进行功放的数字预失真测试,功放的输出ACPR改善了6dB以上。     

A novel miniaturized power amplifier with nth harmonic suppression

In this paper, a novel miniaturized power amplifier (PA) matched by two proposed low pass filters (LPFs) with nth harmonics suppression is presented. In the proposed PA, the LPFs are employed as an output and input impedance transformer networks, which transform 50 Ω to the desired impedances. In the proposed PA the conventional output and input matching networks are eliminated, which results in 52% size reduction and 6% power added efficiency (PAE) improvement compared with the conventional PA. Moreover, using the LPFs at the output and input impressively suppress the unwanted harmonics (2nd–6th) with high level of attenuation. The proposed PA works at the 2.6 GHz, which is suitable for long term evolution (LTE) applications. The measured and simulated results are in the good agreement, which confirm the validity of the proposed method.     

Design of broadband class-F power amplifier for multiband LTE handsets applications

A broadband class-F power amplifier for multiband LTE handsets applications is developed across 2.3-2.7 GHz. The power amplifier maintains constant fundamental impedance at the output matching circuit which is operating for broadband. The nearly zero of second harmonic impedance and nearly infinity of third harmonic impedance are found for highly efficient class-F PA. The harmonic control circuits are immersed into the broadband output matching for fundamental frequency. For demonstration, the PA is implemented in InGaP/GaAs HBT process, and tested across the frequency range of 2.3-2.7 GHz using a long-term evolution signal. The presented PA delivers good performance of high efficiency and high linearity, which shows that the broadband class-F PA supports the multiband LTE handsets applications.     

基于悬置线双模谐振器谐波控制型滤波功放

为了实现高效率的射频滤波功率放大器（filtering power amplifier）,将基于悬置线的截线加载谐振器（stub-loaded resonator）带通滤波器的输入阻抗直接匹配到射频功放管CGH40010F的最佳基波阻抗和谐波阻抗,实现射频功率放大器与滤波器的联合设计,使滤波器同时实现了滤波、阻抗匹配和谐波控制的功能,避免了额外的输出匹配结构,实现了结构紧凑、具有滤波功能的高效率谐波控制型射频功放.实测结果表明在中心频率2.45GHz处,其输出功率约为40dBm,最大电源附加效率（power added efficiency）为76.9%,同时具有良好的滤波特性.     

基于双向牵引与谐波抑制的Doherty功率放大器设计

为了提高功率放大器(Power Amplifier,PA)的效率,提出一种基于双向牵引与谐波抑制的对称式Doherty功率放大器(Symmetrical Doherty Power Amplifier,SDPA)结构。该结构在经典DPA 的基础上,首先利用多谐波双向牵引技术获得功放的实际最佳阻抗,然后对主辅功放的二、三次谐波进行抑制,降低了漏极电压电流的重合,最后通过添加补偿线调节主辅功放的功率分配,使得功放整体获得最大的效率。为了验证上述谐波抑制理论与双向牵引技术的正确性,采用GaN 器件设计了一款应用在4G 基站的SDPA。测试结果显示:SDPA 在2.6 GHz 处的小信号增益为12.6 dB,2.5-2.7 GHz 频段内的增益平坦度为±0.75 dB,频带内的S11小于-11.9 dB,在三载波测试时经过数字预失真(Digital Pre-Distortion,DPD)系统纠正后的相邻信道泄漏比(Adjacent Channel Leakage Rate,ACLR)约为-45 dBc,SDPA 在峰值功率点附近的功率附加效率(Power Added Efficiency,PAE)接近60%,在回退点处的PAE约为48%。实验结果验证了该设计方案的可行性。     

260 GHz GaN高功率三倍频器设计

基于GaN太赫兹二极管芯片,采用非平衡式电路结构,设计了一款260 GHz三倍频器。采用GaN肖特基二极管芯片提高电路的耐受功率和输出功率;采用“减高+减宽”的输出波导结构抑制二次谐波;采用高低阻抗带线结构设计了倍频器的输入滤波器和输出滤波器。测试结果显示,该三倍频器在261 GHz峰值频率下,实现最大输出功率为69.1 mW,转换效率为3.3%,同时具有较好的谐波抑制特性。     

Design of Symmetrical Class E Power Amplifiers for Very Low Harmonic-Content Applications

Class E power amplifier circuits are very suitable for high efficiency power amplification applications in the radio-frequency and microwave ranges. However, due to the inherent asymmetrical driving arrangement, they suffer significant harmonic contents in the output voltage and current, and usually require substantial design efforts in achieving the desired load matching networks for applications requiring very low harmonic contents. In this paper, the design of a Class E power amplifier with resonant tank being symmetrically driven by two Class E circuits is studied. The symmetrical Class E circuit, under nominal operating conditions, has extremely low harmonic distortions, and the design of the impedance matching network for harmonic filtering becomes less critical. Practical steady-state design equations for Class E operation are derived and graphically presented. Experimental circuits are constructed for distortion evaluation. It has been found that this circuit offers total harmonic distortions which are about an order of magnitude lower than those of the conventional Class E power amplifier.     

A high-efficiency low-voltage class-E PA for IoT applications in sub-1 GHz frequency range

We present and propose a complete and iterative integrated-circuit and electro-magnetic (EM) co-design methodology and procedure for a low-voltage sub-1 GHz class-E PA. The presented class-E PA consists of the on-chip power transistor, the on-chip gate driving circuits, the off-chip tunable LC load network and the off-chip LC ladder low pass filter. The design methodology includes an explicit design equation based circuit components values'' analysis and numerical derivation, output power targeted transistor size and low pass filter design, and power efficiency oriented design optimization. The proposed design procedure includes the power efficiency oriented LC network tuning, the detailed circuit/EM co-simulation plan on integrated circuit level, package level and PCB level to ensure an accurate simulation to measurement match and first pass design success. The proposed PA is targeted to achieve more than 15 dBm output power delivery and 40% power efficiency at 433 MHz frequency band with 1.5 V low voltage supply. The LC load network is designed to be off-chip for the purpose of easy tuning and optimization. The same circuit can be extended to all sub-1 GHz applications with the same tuning and optimization on the load network at different frequencies. The amplifier is implemented in 0.13 μm CMOS technology with a core area occupation of 400 μm by 300 μm. Measurement results showed that it provided power delivery of 16.42 dBm at antenna with efficiency of 40.6%. A harmonics suppression of 44 dBc is achieved, making it suitable for massive deployment of IoT devices.     

基于谐波调谐的双频高效功率放大器设计

为了满足无线通信系统对低功耗双频功放的需求,分析高效功放的阻抗条件,提出了一种新型双频输出匹配电路,包括谐波控制电路和基波匹配电路两部分.首先,通过调谐晶体管的谐波阻抗减小漏极电压和漏极电流波形的重叠,从而提高功放的效率;其次,通过公式推导得出双频阻抗匹配电路参数,将晶体管在两个频率下的最佳基波阻抗匹配至50Ω.为验证...